Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21846

1

T1

10

T2

1

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3408

1

T2

9

T3

23

T5

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19725

1

T2

9

T3

10

T4

24

auto[1]

5529

1

T1

10

T2

1

T3

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	153	1			T3	10		T149	3		T137	1
values[0]	31	1			T326	1		T141	8		T233	17
values[1]	499	1			T13	1		T29	13		T47	8
values[2]	2818	1			T1	10		T10	14		T12	3
values[3]	702	1			T2	1		T128	5		T60	2
values[4]	850	1			T4	24		T13	1		T128	3
values[5]	681	1			T5	5		T14	1		T151	26
values[6]	684	1			T11	40		T29	19		T60	31
values[7]	645	1			T3	13		T47	1		T127	39
values[8]	570	1			T3	14		T125	4		T129	30
values[9]	1199	1			T2	9		T129	22		T48	25
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	552	1			T13	1		T31	10		T47	8
values[1]	2848	1			T1	10		T10	14		T12	3
values[2]	653	1			T2	1		T13	1		T128	5
values[3]	881	1			T4	24		T226	11		T38	8
values[4]	639	1			T5	5		T11	8		T14	1
values[5]	700	1			T3	13		T11	32		T47	1
values[6]	646	1			T3	14		T127	39		T60	2
values[7]	629	1			T125	4		T129	30		T92	16
values[8]	1088	1			T2	9		T3	10		T129	22
values[9]	41	1			T149	3		T298	1		T331	1
minimum	16577	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T135	1		T151	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	1		T47	8		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T1	10		T10	14		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T60	1		T153	20		T37	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T128	1		T125	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T130	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	13		T226	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T38	5		T159	1		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	1		T226	1		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	5		T11	4		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T47	1		T60	15		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	13		T11	20		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	14		T135	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T127	21		T60	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T125	1		T131	14		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T129	17		T92	16		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T48	14		T137	1		T160	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T2	1		T3	10		T129	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T331	1		T267	3		T335	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T149	1		T298	1		T340	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16351	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T173	1		T228	3		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	9		T151	11		T136	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T132	12		T141	7		T237	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T30	16		T150	23		T202	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	1		T153	5		T37	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T128	4		T125	9		T180	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T241	12		T17	2		T341	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	11		T226	10		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T38	3		T237	14		T322	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T226	4		T229	4		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	4		T29	9		T128	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T60	16		T144	2		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	12		T42	3		T144	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T141	13		T46	1		T334	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T127	18		T60	1		T226	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T125	3		T175	5		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T129	13		T132	9		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T48	11		T160	20		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	8		T129	8		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T335	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T149	2		T285	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	3		T29	5		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T233	8		T327	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T137	1		T246	3		T169	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T3	10		T149	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T326	1		T342	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T141	1		T233	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	9		T135	1		T151	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	1		T47	8		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T1	10		T10	14		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T153	20		T37	13		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T128	1		T125	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T60	1		T142	1		T241	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	13		T226	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T128	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T226	1		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	5		T151	12		T129	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T60	15		T48	1		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	24		T29	10		T299	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	1		T135	2		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	13		T127	21		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	14		T125	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T129	17		T92	16		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T48	14		T160	16		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T2	1		T129	14		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T246	6		T169	7		T320	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T149	2		T132	10		T235	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T342	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T141	7		T233	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	4		T151	11		T180	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T132	12		T252	10		T204	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T30	16		T31	9		T150	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T153	5		T37	10		T176	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T128	4		T125	9		T180	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T60	1		T142	1		T241	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	11		T226	10		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T128	2		T38	3		T237	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T226	4		T131	9		T229	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	14		T129	13		T202	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T60	16		T144	2		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	16		T29	9		T236	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T141	13		T46	1		T334	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	18		T60	1		T226	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T125	3		T175	5		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T129	13		T79	2		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T48	11		T160	20		T42	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	8		T129	8		T43	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	10		T135	1		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	1		T47	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T1	1		T10	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	2		T153	6		T37	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T128	5		T125	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T130	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T4	12		T226	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T38	6		T159	1		T339	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T226	5		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T11	5		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	1		T60	17		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T11	18		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	1		T135	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T127	20		T60	2		T226	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T125	4		T131	1		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T129	14		T92	1		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T48	12		T137	1		T160	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	9		T3	1		T129	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T331	1		T267	1		T335	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	3		T298	1		T340	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16489	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T173	1		T228	1		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T151	3		T136	3		T227	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T47	7		T175	8		T266	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T1	9		T10	13		T27	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T153	19		T37	8		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T125	7		T245	2		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T241	13		T17	3		T341	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	12		T131	13		T229	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	2		T237	16		T244	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T138	8		T229	2		T233	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	4		T11	3		T29	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T60	14		T266	11		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	12		T11	14		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	13		T46	2		T334	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T127	19		T133	9		T236	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	13		T175	8		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T129	16		T92	15		T41	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	13		T160	14		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	9		T129	13		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T267	2		T335	2		T324	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T29	8		T44	5		T126	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T228	2		T233	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T137	1		T246	7		T169	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T3	1		T149	3		T132	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T326	1		T342	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T141	8		T233	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	5		T135	1		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	1		T47	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T1	1		T10	1		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T153	6		T37	15		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T128	5		T125	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T60	2		T142	2		T241	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T4	12		T226	11		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T128	3		T38	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T226	5		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T151	15		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T60	17		T48	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	23		T29	10		T299	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	1		T135	2		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T127	20		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T125	4		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T129	14		T92	1		T79	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T48	12		T160	22		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T2	9		T129	9		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T246	2		T343	10		T320	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T3	9		T235	8		T318	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T233	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	8		T151	3		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T47	7		T228	2		T319	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T1	9		T10	13		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T153	19		T37	8		T138	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T125	7		T231	16		T143	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T241	13		T145	21		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	12		T245	2		T229	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	2		T237	16		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T131	13		T229	2		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	4		T151	11		T129	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T60	14		T138	8		T266	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	17		T29	9		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	2		T334	3		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	12		T127	19		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	13		T131	13		T175	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T129	16		T92	15		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	13		T160	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T129	13		T227	13		T43	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12