Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19387

1

T6

20

T7

154

T8

16

auto[ADC_CTRL_FILTER_COND_OUT]

5867

1

T1

10

T2

10

T3

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19624

1

T2

1

T5

5

T6

20

auto[1]

5630

1

T1

10

T2

9

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	345	1			T130	1		T134	1		T160	12
values[0]	33	1			T259	24		T310	8		T316	1
values[1]	769	1			T151	26		T226	11		T37	23
values[2]	711	1			T3	13		T5	5		T127	31
values[3]	608	1			T151	15		T172	1		T133	18
values[4]	623	1			T4	24		T13	1		T135	1
values[5]	666	1			T2	9		T11	12		T14	1
values[6]	604	1			T11	20		T129	22		T231	17
values[7]	834	1			T13	1		T31	10		T47	8
values[8]	676	1			T3	14		T30	28		T135	1
values[9]	2963	1			T1	10		T2	1		T3	10
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	697	1			T3	13		T136	10		T226	11
values[1]	2881	1			T1	10		T5	5		T10	14
values[2]	536	1			T4	24		T151	15		T226	5
values[3]	693	1			T2	9		T11	12		T13	1
values[4]	675	1			T14	1		T29	32		T128	3
values[5]	539	1			T11	20		T60	31		T129	22
values[6]	763	1			T13	1		T31	10		T47	8
values[7]	750	1			T3	24		T30	28		T47	1
values[8]	871	1			T11	8		T128	5		T60	2
values[9]	193	1			T2	1		T92	16		T166	1
minimum	16656	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	4		T37	13		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	13		T226	1		T227	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T127	17		T137	1		T133	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1514	1			T1	10		T5	5		T10	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T226	1		T134	1		T161	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	13		T151	4		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T227	14		T245	5		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	1		T11	7		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T29	9		T127	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T29	10		T128	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	13		T60	15		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T40	2		T133	10		T42	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T31	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T47	8		T132	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	12		T135	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	24		T47	1		T202	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	1		T129	17		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	4		T60	1		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T244	9		T169	1		T243	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T2	1		T92	16		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16277	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T151	12		T160	13		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T136	6		T37	10		T141	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T226	10		T180	2		T141	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	14		T133	9		T180	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1026	1			T150	23		T260	5		T275	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T226	4		T144	2		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	11		T151	11		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T259	2		T233	13		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	8		T11	5		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	4		T127	4		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	9		T128	2		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T11	7		T60	16		T129	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	7		T42	3		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T31	9		T149	2		T125	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	12		T233	8		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T30	16		T125	9		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T202	9		T48	11		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T128	4		T129	13		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	4		T60	1		T131	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T169	11		T243	2		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T295	2		T281	10		T344	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	3		T29	1		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T151	14		T160	11		T259	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T130	1		T160	3		T229	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	1		T227	9		T229	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T310	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	11		T316	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	13		T164	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T151	12		T226	1		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	17		T136	4		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	13		T5	5		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	9		T161	4		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T151	4		T172	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T226	1		T134	1		T245	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	13		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	1		T29	9		T127	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T11	7		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	13		T129	14		T231	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T40	2		T133	10		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T31	1		T60	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	8		T132	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	12		T135	1		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	14		T202	13		T48	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T128	1		T129	17		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1578	1			T1	10		T2	1		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T160	9		T229	12		T243	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T229	4		T235	9		T281	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T310	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	10		T141	2		T345	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T151	14		T226	10		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	14		T136	6		T180	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T237	14		T238	10		T256	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	9		T242	13		T238	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	11		T236	6		T239	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T226	4		T144	2		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	11		T153	5		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T29	4		T127	4		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	8		T11	5		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T11	7		T129	8		T293	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	7		T42	3		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T31	9		T60	16		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T132	12		T233	8		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	16		T125	9		T202	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T202	9		T48	11		T236	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	4		T129	13		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1065	1			T11	4		T60	1		T150	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	7		T37	15		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T226	11		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T127	15		T137	1		T133	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1365	1			T1	1		T5	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T226	5		T134	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	12		T151	12		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T227	1		T245	2		T203	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	9		T11	8		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	1		T29	5		T127	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	10		T128	3		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	10		T60	17		T129	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	2		T133	8		T42	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	1		T31	10		T149	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	1		T132	13		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T30	17		T135	1		T125	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	2		T47	1		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T128	5		T129	14		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	5		T60	2		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T244	1		T169	12		T243	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T2	1		T92	1		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16454	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T151	15		T160	12		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	3		T37	8		T207	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	12		T227	2		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T127	16		T133	8		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1175	1			T1	9		T5	4		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T161	3		T228	3		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	12		T151	3		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T227	13		T245	3		T259	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	4		T153	19		T129	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	8		T127	3		T175	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	9		T138	8		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	10		T60	14		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T133	9		T42	2		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T143	3		T241	13		T155	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	7		T266	2		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T30	11		T125	7		T202	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	22		T202	12		T48	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	16		T160	2		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	3		T131	13		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T244	8		T243	4		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T92	15		T308	17		T295	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T171	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T151	11		T160	12		T259	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T130	1		T160	10		T229	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T134	1		T227	1		T229	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T310	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T259	14		T316	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	15		T164	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T151	15		T226	11		T160	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	15		T136	7		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T5	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	10		T161	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T151	12		T172	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T226	5		T134	1		T245	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	12		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T29	5		T127	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	9		T11	8		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	10		T129	9		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	2		T133	8		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T13	1		T31	10		T60	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T132	13		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T30	17		T135	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T202	10		T48	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T128	5		T129	14		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1429	1			T1	1		T2	1		T3	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T160	2		T229	8		T279	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T227	8		T229	2		T235	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T259	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	8		T279	11		T311	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T151	11		T160	12		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	16		T136	3		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	12		T5	4		T237	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T133	8		T161	3		T238	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	3		T236	10		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T245	3		T228	3		T144	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	12		T153	19		T129	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T29	8		T127	3		T227	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	4		T29	9		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	10		T129	13		T231	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	9		T42	2		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T60	14		T143	3		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	7		T228	8		T318	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	11		T125	7		T202	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	13		T202	12		T48	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T129	16		T42	2		T244	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1214	1			T1	9		T3	9		T10	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12