Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21785

1

T1

10

T2

9

T3

14

auto[ADC_CTRL_FILTER_COND_OUT]

3469

1

T2

1

T3

23

T5

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19158

1

T2

1

T6

20

T7

149

auto[1]

6096

1

T1

10

T2

9

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	724	1			T7	5		T11	9		T127	31
values[0]	67	1			T40	2		T279	12		T237	13
values[1]	757	1			T3	13		T11	28		T30	28
values[2]	2804	1			T1	10		T10	14		T11	12
values[3]	751	1			T3	10		T47	1		T60	31
values[4]	591	1			T29	19		T128	5		T60	2
values[5]	763	1			T3	14		T5	5		T202	36
values[6]	762	1			T4	24		T129	31		T226	16
values[7]	548	1			T135	1		T151	15		T129	30
values[8]	570	1			T2	1		T135	1		T125	4
values[9]	907	1			T2	9		T13	2		T14	1
minimum	16010	1			T6	20		T7	149		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T11	40		T30	28		T47	8
values[1]	2778	1			T1	10		T3	10		T10	14
values[2]	832	1			T60	31		T129	22		T48	1
values[3]	633	1			T29	19		T128	5		T60	2
values[4]	684	1			T3	14		T4	24		T5	5
values[5]	709	1			T129	31		T226	5		T130	1
values[6]	539	1			T135	2		T151	15		T129	30
values[7]	682	1			T2	1		T31	10		T125	4
values[8]	836	1			T2	9		T13	2		T14	1
values[9]	129	1			T264	13		T300	18		T346	15
minimum	16662	1			T3	13		T6	20		T7	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	11		T151	12		T136	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	13		T30	12		T47	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T1	10		T10	14		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	10		T47	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T60	15		T129	14		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T159	1		T228	4		T142	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T202	13		T79	1		T131	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T29	10		T128	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	14		T4	13		T202	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	5		T172	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T130	1		T299	1		T175	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T129	18		T226	1		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	2		T151	4		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	17		T172	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	20		T172	1		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T31	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	1		T13	1		T29	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T14	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T264	1		T170	4		T347	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T300	10		T346	1		T301	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16334	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T3	13		T149	1		T226	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	9		T151	14		T136	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	7		T30	16		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T127	4		T60	1		T150	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	2		T246	6		T167	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T60	16		T129	8		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T142	8		T176	4		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T202	9		T79	2		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	9		T128	4		T60	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	11		T202	10		T226	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T236	6		T142	8		T176	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T175	4		T207	6		T283	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T129	13		T226	4		T42	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T151	11		T292	10		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T129	13		T141	7		T207	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T153	5		T236	8		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	9		T125	3		T37	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	8		T29	4		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T128	2		T127	14		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T264	12		T224	7		T282	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T300	8		T346	14		T301	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	3		T29	1		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T149	2		T226	7		T235	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	520	1			T7	5		T11	9		T48	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T127	17		T125	8		T300	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T40	2		T279	12		T237	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T348	1		T217	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	4		T151	12		T136	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	13		T11	13		T30	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T1	10		T10	14		T11	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	1		T41	3		T246	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T60	15		T129	14		T48	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	10		T47	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	1		T79	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	10		T128	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	14		T202	17		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	5		T172	1		T92	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	13		T226	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T129	18		T226	1		T131	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	1		T151	4		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T129	17		T134	1		T41	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	1		T172	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T125	1		T37	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T2	1		T13	1		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	1		T14	1		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15859	1			T6	20		T7	149		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T238	19		T293	4		T349	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T127	14		T125	9		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T237	2		T281	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T217	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	4		T151	14		T136	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	7		T30	16		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T11	5		T127	4		T60	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T41	2		T246	6		T238	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T60	16		T129	8		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	8		T176	4		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T79	2		T44	6		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T29	9		T128	4		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T202	19		T131	9		T133	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T236	6		T141	2		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	11		T226	10		T175	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T129	13		T226	4		T42	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T151	11		T292	10		T283	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T129	13		T141	7		T207	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T141	13		T233	13		T264	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	3		T37	10		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	8		T29	4		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	9		T128	2		T180	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	13		T151	15		T136	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	10		T30	17		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T1	1		T10	1		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T47	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T60	17		T129	9		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T159	1		T228	1		T142	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T202	10		T79	3		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	10		T128	5		T60	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T4	12		T202	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T172	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T130	1		T299	1		T175	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T129	14		T226	5		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T135	2		T151	12		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T129	14		T172	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	6		T172	1		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	1		T31	10		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	9		T13	1		T29	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	1		T14	1		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T264	13		T170	4		T347	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T300	10		T346	15		T301	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16492	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T3	1		T149	3		T226	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	7		T151	11		T136	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	10		T30	11		T47	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T1	9		T10	13		T27	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	9		T41	1		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T60	14		T129	13		T133	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T228	3		T142	10		T176	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T202	12		T131	13		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	9		T231	16		T92	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	13		T4	12		T202	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T5	4		T138	8		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T175	2		T143	8		T93	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T129	17		T131	13		T42	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T151	3		T143	3		T292	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T129	16		T228	8		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T153	19		T236	12		T168	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	8		T227	13		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T29	8		T138	9		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	16		T125	7		T266	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T224	11		T305	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T300	8		T301	1		T302	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T245	1		T237	12		T291	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T3	12		T235	13		T321	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	502	1			T7	5		T11	9		T48	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T127	15		T125	10		T300	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T40	2		T279	1		T237	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T348	1		T217	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	5		T151	15		T136	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T11	10		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	1		T10	1		T11	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T135	1		T41	4		T246	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T60	17		T129	9		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T47	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	1		T79	3		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	10		T128	5		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T202	21		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T172	1		T92	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	12		T226	11		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T129	14		T226	5		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T135	1		T151	12		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T129	14		T134	1		T41	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	1		T172	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T125	4		T37	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	9		T13	1		T29	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T14	1		T31	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16010	1			T6	20		T7	149		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T138	9		T238	20		T293	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T127	16		T125	7		T300	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T279	11		T237	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T217	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	3		T151	11		T136	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	12		T11	10		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1104	1			T1	9		T10	13		T11	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T41	1		T246	2		T145	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T60	14		T129	13		T48	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	9		T142	10		T176	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T44	5		T17	1		T278	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	9		T231	16		T228	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	13		T202	15		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	4		T92	15		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	12		T175	2		T93	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	17		T131	13		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T151	3		T143	8		T292	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T129	16		T228	8		T207	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T143	3		T233	12		T168	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	8		T227	13		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T29	8		T153	19		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T266	13		T163	2		T148	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12