Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22023

1

T1

10

T2

10

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3231

1

T3

14

T11

20

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19414

1

T2

10

T3

23

T4

24

auto[1]

5840

1

T1

10

T3

14

T10

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	344	1			T60	31		T160	24		T266	14
values[0]	57	1			T125	17		T254	1		T140	1
values[1]	647	1			T4	24		T149	3		T136	10
values[2]	608	1			T3	13		T13	1		T47	1
values[3]	749	1			T3	14		T13	1		T29	13
values[4]	631	1			T2	9		T3	10		T5	5
values[5]	683	1			T48	1		T79	3		T130	2
values[6]	453	1			T11	8		T153	25		T38	8
values[7]	886	1			T2	1		T11	32		T29	19
values[8]	677	1			T14	1		T30	28		T128	8
values[9]	3097	1			T1	10		T10	14		T12	3
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	560	1			T3	13		T149	3		T136	10
values[1]	652	1			T13	2		T47	1		T151	26
values[2]	679	1			T2	9		T3	14		T29	13
values[3]	663	1			T3	10		T5	5		T31	10
values[4]	628	1			T48	1		T79	3		T130	1
values[5]	579	1			T11	8		T153	25		T202	22
values[6]	3033	1			T1	10		T2	1		T10	14
values[7]	724	1			T14	1		T128	8		T127	31
values[8]	776	1			T202	14		T48	25		T226	8
values[9]	229	1			T60	31		T135	1		T160	24
minimum	16731	1			T4	24		T6	20		T7	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	13		T149	1		T41	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	4		T253	1		T191	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T151	12		T226	1		T92	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	2		T47	1		T231	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T29	9		T47	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	14		T245	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	10		T5	5		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	1		T60	1		T129	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T79	1		T130	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T48	1		T159	1		T42	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T153	20		T38	5		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	4		T202	13		T131	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T1	10		T2	1		T10	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	7		T30	12		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	1		T128	2		T127	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	1		T259	11		T244	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T48	14		T226	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T202	4		T172	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T141	1		T247	7		T308	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T60	15		T135	1		T160	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16373	1			T4	13		T6	20		T7	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T138	10		T254	1		T319	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T149	2		T41	2		T43	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	6		T235	9		T242	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T151	14		T226	10		T180	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T175	5		T292	10		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	8		T29	4		T127	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T141	13		T45	1		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T131	2		T148	6		T142	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T31	9		T60	1		T129	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T79	2		T229	12		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	4		T142	8		T237	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	5		T38	3		T238	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	4		T202	9		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T11	7		T29	9		T150	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	5		T30	16		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T128	6		T127	14		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T259	13		T167	10		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T48	11		T226	7		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T202	10		T132	12		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T141	2		T247	4		T308	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T60	16		T160	11		T300	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	11		T11	3		T29	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T321	15		T261	7		T350	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T229	9		T144	14		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T60	15		T160	13		T266	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T125	8		T140	1		T176	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T254	1		T351	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	13		T149	1		T41	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T136	4		T138	10		T253	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	13		T151	12		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T47	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	9		T47	8		T127	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T3	14		T13	1		T231	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T3	10		T5	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	1		T60	1		T129	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T79	1		T130	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	1		T130	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	20		T38	5		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	4		T131	14		T227	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T2	1		T11	13		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	7		T154	1		T202	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	1		T128	2		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T30	12		T134	1		T236	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T1	10		T10	14		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T135	1		T202	4		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T229	11		T144	2		T247	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T60	16		T160	11		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T125	9		T176	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T351	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T4	11		T149	2		T41	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	6		T235	9		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	14		T226	10		T180	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T292	10		T313	7		T293	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T29	4		T127	4		T60	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T175	5		T141	13		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	8		T226	4		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T31	9		T60	1		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T79	2		T131	2		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	1		T237	14		T86	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T153	5		T38	3		T352	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T11	4		T131	9		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	7		T29	9		T125	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	5		T202	9		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T128	6		T129	8		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	16		T236	6		T212	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T127	14		T150	23		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T202	10		T132	12		T133	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T149	3		T41	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	7		T253	1		T191	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	15		T226	11		T92	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T47	1		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	9		T29	5		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T245	1		T141	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T5	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T31	10		T60	2		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T79	3		T130	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	1		T159	1		T42	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T153	6		T38	6		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	5		T202	10		T131	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T1	1		T2	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	8		T30	17		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	1		T128	8		T127	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T134	1		T259	14		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T48	12		T226	8		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T202	11		T172	1		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T141	3		T247	5		T308	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T60	17		T135	1		T160	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16476	1			T4	12		T6	20		T7	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T138	1		T254	1		T319	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T3	12		T41	1		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	3		T235	8		T258	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T151	11		T92	15		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T231	16		T227	8		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T29	8		T47	7		T127	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	13		T245	1		T279	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	9		T5	4		T138	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T129	17		T266	2		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T175	8		T229	8		T142	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T42	2		T142	8		T279	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T153	19		T38	2		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	3		T202	12		T131	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T1	9		T10	13		T11	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	4		T30	11		T236	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T127	16		T151	3		T129	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T259	10		T244	9		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	13		T42	2		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T202	3		T133	8		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T247	6		T308	2		T353	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T60	14		T160	12		T266	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T4	12		T125	7		T161	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T138	9		T319	15		T308	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T229	12		T144	3		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T60	17		T160	12		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T125	10		T140	1		T176	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	1		T351	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	12		T149	3		T41	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	7		T138	1		T253	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T151	15		T226	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T47	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	5		T47	1		T127	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T13	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	9		T3	1		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	10		T60	2		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T79	3		T130	1		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	1		T130	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T153	6		T38	6		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	5		T131	10		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	1		T11	10		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	8		T154	1		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T128	8		T129	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	17		T134	1		T236	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T1	1		T10	1		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T135	1		T202	11		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T229	8		T144	13		T244	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T60	14		T160	12		T266	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T125	7		T176	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T351	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	12		T41	1		T161	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	3		T138	9		T235	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	12		T151	11		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T227	8		T143	3		T292	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T29	8		T47	7		T127	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	13		T231	16		T245	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	9		T5	4		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T129	17		T266	2		T163	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	8		T175	8		T229	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T279	11		T237	16		T86	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T153	19		T38	2		T338	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	3		T131	13		T227	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T11	10		T29	9		T129	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	4		T202	12		T131	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T129	13		T241	13		T167	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T30	11		T236	10		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T1	9		T10	13		T27	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T202	3		T133	8		T259	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12