Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T60	2		T253	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T14	1		T172	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	5		T60	17		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T128	5		T153	6		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	1		T60	2		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T11	8		T125	10		T226	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	12		T245	1		T175	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	10		T159	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	1		T135	1		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T254	1		T42	10		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	10		T127	15		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T4	12		T5	1		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	1		T10	1		T11	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T31	10		T149	3		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T127	5		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T125	4		T37	15		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T128	3		T135	1		T202	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	1		T11	5		T30	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T44	12		T247	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T236	9		T252	11		T256	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16442	1			T6	20		T7	154		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T162	1		T205	1		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	13		T175	8		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	9		T145	12		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	8		T60	14		T138	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T153	19		T227	8		T266	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	2		T92	15		T131	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	4		T125	7		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T48	13		T245	2		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T142	10		T176	9		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	3		T245	1		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T42	2		T144	13		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	9		T127	16		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	12		T5	4		T151	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T1	9		T10	13		T11	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T138	9		T133	8		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T127	3		T129	46		T231	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	8		T131	13		T266	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T202	3		T133	9		T145	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	12		T11	3		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T44	5		T247	2		T261	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T236	12		T256	11		T199	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T257	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T248	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T249	1		T250	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T60	2		T140	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T253	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T14	1		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	5		T47	1		T60	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T153	6		T164	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T60	2		T154	1		T38	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T11	8		T125	10		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T172	1		T175	5		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	10		T226	11		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T135	1		T48	12		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T159	1		T42	10		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T29	10		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	1		T151	12		T226	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T127	15		T134	1		T41	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	12		T202	10		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	1		T10	1		T11	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	10		T149	3		T125	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	1		T128	3		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T3	1		T11	5		T30	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T267	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	13		T175	8		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	9		T145	12		T207	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	8		T60	14		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T153	19		T266	13		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T38	2		T92	15		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	4		T125	7		T227	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T175	2		T228	3		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T235	8		T238	10		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	13		T136	3		T245	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T42	2		T142	10		T144	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	9		T151	11		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	4		T151	3		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T127	16		T41	1		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	12		T202	12		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T1	9		T10	13		T11	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T131	13		T266	2		T237	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T129	17		T202	3		T231	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T3	12		T11	3		T30	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12