CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25254 | 1 | T1 | 10 | T2 | 10 | T3 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 21508 | 1 | T1 | 10 | T2 | 1 | T3 | 23 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3746 | 1 | T2 | 9 | T3 | 14 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19574 | 1 | T2 | 10 | T3 | 24 | T4 | 24 | ||||
auto[1] | 5680 | 1 | T1 | 10 | T3 | 13 | T5 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21283 | 1 | T1 | 10 | T2 | 2 | T3 | 37 | ||||
auto[1] | 3971 | 1 | T2 | 8 | T4 | 11 | T11 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 8 | 1 | T268 | 8 | - | - | - | - | ||||
values[0] | 67 | 1 | T79 | 3 | T269 | 1 | T270 | 18 | ||||
values[1] | 681 | 1 | T2 | 9 | T4 | 24 | T14 | 1 | ||||
values[2] | 625 | 1 | T11 | 8 | T30 | 28 | T60 | 33 | ||||
values[3] | 689 | 1 | T127 | 8 | T129 | 22 | T226 | 8 | ||||
values[4] | 813 | 1 | T11 | 12 | T13 | 1 | T153 | 25 | ||||
values[5] | 2794 | 1 | T1 | 10 | T2 | 1 | T10 | 14 | ||||
values[6] | 583 | 1 | T31 | 10 | T226 | 16 | T37 | 23 | ||||
values[7] | 799 | 1 | T3 | 13 | T11 | 20 | T127 | 31 | ||||
values[8] | 663 | 1 | T3 | 14 | T29 | 19 | T128 | 3 | ||||
values[9] | 1110 | 1 | T3 | 10 | T5 | 5 | T13 | 1 | ||||
minimum | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 832 | 1 | T2 | 9 | T14 | 1 | T29 | 13 | ||||
values[1] | 650 | 1 | T4 | 24 | T11 | 8 | T60 | 33 | ||||
values[2] | 930 | 1 | T11 | 12 | T153 | 25 | T129 | 22 | ||||
values[3] | 2702 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
values[4] | 650 | 1 | T202 | 14 | T37 | 23 | T172 | 1 | ||||
values[5] | 706 | 1 | T2 | 1 | T3 | 13 | T151 | 15 | ||||
values[6] | 719 | 1 | T11 | 20 | T29 | 19 | T31 | 10 | ||||
values[7] | 566 | 1 | T3 | 24 | T60 | 2 | T125 | 4 | ||||
values[8] | 880 | 1 | T5 | 5 | T13 | 1 | T128 | 3 | ||||
values[9] | 183 | 1 | T99 | 26 | T19 | 5 | T271 | 13 | ||||
minimum | 16436 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T14 | 1 | T30 | 12 | T151 | 12 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 268 | 1 | T2 | 1 | T29 | 9 | T135 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T202 | 13 | T39 | 1 | T138 | 9 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 225 | 1 | T4 | 13 | T11 | 4 | T60 | 16 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 234 | 1 | T172 | 1 | T133 | 9 | T42 | 4 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 281 | 1 | T11 | 7 | T153 | 20 | T129 | 14 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1430 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T127 | 4 | T154 | 1 | T131 | 14 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 187 | 1 | T202 | 4 | T172 | 1 | T139 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T37 | 13 | T132 | 1 | T159 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 202 | 1 | T2 | 1 | T3 | 13 | T151 | 4 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 173 | 1 | T160 | 13 | T41 | 3 | T175 | 9 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T31 | 1 | T47 | 8 | T149 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 251 | 1 | T11 | 13 | T29 | 10 | T127 | 17 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 168 | 1 | T3 | 10 | T48 | 1 | T131 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 210 | 1 | T3 | 14 | T60 | 1 | T125 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T5 | 5 | T128 | 1 | T125 | 8 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 280 | 1 | T13 | 1 | T135 | 1 | T134 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 75 | 1 | T99 | 14 | T19 | 4 | T271 | 13 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 46 | 1 | T272 | 5 | T273 | 11 | T274 | 5 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16272 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 2 | 1 | T128 | 1 | T169 | 1 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 194 | 1 | T30 | 16 | T151 | 14 | T48 | 11 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T2 | 8 | T29 | 4 | T129 | 26 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 75 | 1 | T202 | 9 | T42 | 4 | T229 | 4 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 199 | 1 | T4 | 11 | T11 | 4 | T60 | 17 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T133 | 9 | T42 | 3 | T175 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 234 | 1 | T11 | 5 | T153 | 5 | T129 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 942 | 1 | T150 | 23 | T260 | 5 | T275 | 19 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T127 | 4 | T259 | 2 | T230 | 3 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 144 | 1 | T202 | 10 | T148 | 6 | T144 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T37 | 10 | T132 | 12 | T141 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T151 | 11 | T226 | 14 | T180 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 152 | 1 | T160 | 11 | T41 | 2 | T229 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 122 | 1 | T31 | 9 | T149 | 2 | T17 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T11 | 7 | T29 | 9 | T127 | 14 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T131 | 2 | T133 | 7 | T160 | 9 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 58 | 1 | T60 | 1 | T125 | 3 | T132 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T128 | 2 | T125 | 9 | T38 | 3 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 271 | 1 | T180 | 2 | T241 | 12 | T167 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 22 | 1 | T99 | 12 | T19 | 1 | T276 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 40 | 1 | T273 | 13 | T274 | 1 | T277 | 10 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T11 | 3 | T29 | 1 | T48 | 1 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T128 | 4 | T169 | 7 | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 5 | 43 | 89.58 | 5 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 1 | 1 | T268 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 1 | 1 | T269 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 34 | 1 | T79 | 1 | T270 | 9 | T278 | 11 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 136 | 1 | T14 | 1 | T151 | 12 | T48 | 14 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 193 | 1 | T2 | 1 | T4 | 13 | T29 | 9 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T30 | 12 | T202 | 13 | T136 | 4 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T11 | 4 | T60 | 16 | T135 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 197 | 1 | T172 | 1 | T42 | 8 | T175 | 9 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T127 | 4 | T129 | 14 | T226 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 200 | 1 | T13 | 1 | T172 | 1 | T41 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T11 | 7 | T153 | 20 | T154 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1459 | 1 | T1 | 10 | T2 | 1 | T10 | 14 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T132 | 1 | T41 | 3 | T141 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T31 | 1 | T226 | 2 | T130 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T37 | 13 | T159 | 1 | T175 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 216 | 1 | T3 | 13 | T149 | 1 | T151 | 4 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 241 | 1 | T11 | 13 | T127 | 17 | T231 | 17 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 157 | 1 | T128 | 1 | T47 | 8 | T48 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 285 | 1 | T3 | 14 | T29 | 10 | T60 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 270 | 1 | T3 | 10 | T5 | 5 | T125 | 8 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 332 | 1 | T13 | 1 | T135 | 1 | T138 | 10 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16271 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 7 | 1 | T268 | 7 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 32 | 1 | T79 | 2 | T270 | 9 | T278 | 5 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 167 | 1 | T151 | 14 | T48 | 11 | T132 | 10 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 185 | 1 | T2 | 8 | T4 | 11 | T29 | 4 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 79 | 1 | T30 | 16 | T202 | 9 | T136 | 6 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T11 | 4 | T60 | 17 | T129 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T42 | 4 | T175 | 5 | T246 | 6 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 129 | 1 | T127 | 4 | T129 | 8 | T226 | 7 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 140 | 1 | T42 | 3 | T45 | 1 | T235 | 18 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 242 | 1 | T11 | 5 | T153 | 5 | T126 | 14 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 983 | 1 | T150 | 23 | T202 | 10 | T260 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 164 | 1 | T132 | 12 | T41 | 2 | T141 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T31 | 9 | T226 | 14 | T44 | 6 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T37 | 10 | T175 | 4 | T229 | 12 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T149 | 2 | T151 | 11 | T131 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T11 | 7 | T127 | 14 | T160 | 11 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 97 | 1 | T128 | 2 | T133 | 7 | T160 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 124 | 1 | T29 | 9 | T60 | 1 | T125 | 3 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 221 | 1 | T125 | 9 | T38 | 3 | T43 | 4 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 287 | 1 | T132 | 9 | T180 | 2 | T241 | 12 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T11 | 3 | T29 | 1 | T48 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 235 | 1 | T14 | 1 | T30 | 17 | T151 | 15 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 277 | 1 | T2 | 9 | T29 | 5 | T135 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T202 | 10 | T39 | 1 | T138 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 245 | 1 | T4 | 12 | T11 | 5 | T60 | 19 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 225 | 1 | T172 | 1 | T133 | 10 | T42 | 5 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 287 | 1 | T11 | 8 | T153 | 6 | T129 | 9 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1271 | 1 | T1 | 1 | T10 | 1 | T12 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 194 | 1 | T127 | 5 | T154 | 1 | T131 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 179 | 1 | T202 | 11 | T172 | 1 | T139 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 182 | 1 | T37 | 15 | T132 | 13 | T159 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 223 | 1 | T2 | 1 | T3 | 1 | T151 | 12 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 187 | 1 | T160 | 12 | T41 | 4 | T175 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T31 | 10 | T47 | 1 | T149 | 3 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 202 | 1 | T11 | 10 | T29 | 10 | T127 | 15 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 170 | 1 | T3 | 1 | T48 | 1 | T131 | 3 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 105 | 1 | T3 | 1 | T60 | 2 | T125 | 4 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 219 | 1 | T5 | 1 | T128 | 3 | T125 | 10 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 331 | 1 | T13 | 1 | T135 | 1 | T134 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 33 | 1 | T99 | 13 | T19 | 4 | T271 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 58 | 1 | T272 | 1 | T273 | 14 | T274 | 5 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16423 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T128 | 5 | T169 | 8 | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 98 | 1 | T30 | 11 | T151 | 11 | T48 | 13 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 222 | 1 | T29 | 8 | T129 | 33 | T161 | 3 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 103 | 1 | T202 | 12 | T138 | 8 | T42 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T4 | 12 | T11 | 3 | T60 | 14 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 190 | 1 | T133 | 8 | T42 | 2 | T175 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 228 | 1 | T11 | 4 | T153 | 19 | T129 | 13 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 1101 | 1 | T1 | 9 | T10 | 13 | T27 | 7 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 136 | 1 | T127 | 3 | T131 | 13 | T227 | 15 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T202 | 3 | T148 | 7 | T143 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 137 | 1 | T37 | 8 | T279 | 11 | T238 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 158 | 1 | T3 | 12 | T151 | 3 | T44 | 5 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 138 | 1 | T160 | 12 | T41 | 1 | T175 | 8 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 145 | 1 | T47 | 7 | T279 | 11 | T17 | 3 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 214 | 1 | T11 | 10 | T29 | 9 | T127 | 16 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 128 | 1 | T3 | 9 | T133 | 9 | T160 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T3 | 13 | T92 | 15 | T138 | 9 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 110 | 1 | T5 | 4 | T125 | 7 | T38 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 220 | 1 | T245 | 2 | T241 | 13 | T167 | 10 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 64 | 1 | T99 | 13 | T19 | 1 | T271 | 12 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 28 | 1 | T272 | 4 | T273 | 10 | T274 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 7 | 41 | 85.42 | 7 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [maximum] | * | -- | -- | 2 | |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_IN]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 8 | 1 | T268 | 8 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 1 | 1 | T269 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 36 | 1 | T79 | 3 | T270 | 10 | T278 | 6 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 207 | 1 | T14 | 1 | T151 | 15 | T48 | 12 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 219 | 1 | T2 | 9 | T4 | 12 | T29 | 5 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 112 | 1 | T30 | 17 | T202 | 10 | T136 | 7 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 238 | 1 | T11 | 5 | T60 | 19 | T135 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 186 | 1 | T172 | 1 | T42 | 10 | T175 | 6 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 172 | 1 | T127 | 5 | T129 | 9 | T226 | 8 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 181 | 1 | T13 | 1 | T172 | 1 | T41 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 294 | 1 | T11 | 8 | T153 | 6 | T154 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1316 | 1 | T1 | 1 | T2 | 1 | T10 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 203 | 1 | T132 | 13 | T41 | 4 | T141 | 3 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 182 | 1 | T31 | 10 | T226 | 16 | T130 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 180 | 1 | T37 | 15 | T159 | 1 | T175 | 6 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 223 | 1 | T3 | 1 | T149 | 3 | T151 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T11 | 10 | T127 | 15 | T231 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 126 | 1 | T128 | 3 | T47 | 1 | T48 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 178 | 1 | T3 | 1 | T29 | 10 | T60 | 2 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 295 | 1 | T3 | 1 | T5 | 1 | T125 | 10 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 369 | 1 | T13 | 1 | T135 | 1 | T138 | 1 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 30 | 1 | T270 | 8 | T278 | 10 | T280 | 12 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 96 | 1 | T151 | 11 | T48 | 13 | T163 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 159 | 1 | T4 | 12 | T29 | 8 | T129 | 16 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 98 | 1 | T30 | 11 | T202 | 12 | T136 | 3 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T11 | 3 | T60 | 14 | T129 | 17 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 152 | 1 | T42 | 2 | T175 | 8 | T246 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T127 | 3 | T129 | 13 | T131 | 13 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T42 | 2 | T228 | 3 | T45 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 179 | 1 | T11 | 4 | T153 | 19 | T245 | 1 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 1126 | 1 | T1 | 9 | T10 | 13 | T27 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 149 | 1 | T41 | 1 | T228 | 8 | T259 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 117 | 1 | T44 | 5 | T142 | 10 | T145 | 12 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 104 | 1 | T37 | 8 | T175 | 10 | T229 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 177 | 1 | T3 | 12 | T151 | 3 | T236 | 12 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 207 | 1 | T11 | 10 | T127 | 16 | T231 | 16 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 128 | 1 | T47 | 7 | T133 | 9 | T160 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 231 | 1 | T3 | 13 | T29 | 9 | T92 | 15 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 196 | 1 | T3 | 9 | T5 | 4 | T125 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 250 | 1 | T138 | 9 | T245 | 2 | T241 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | auto[0] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |