Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21849

1

T1

10

T3

14

T5

5

auto[ADC_CTRL_FILTER_COND_OUT]

3405

1

T2

10

T3

23

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19308

1

T2

9

T3

13

T6

20

auto[1]

5946

1

T1

10

T2

1

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T281	5		T282	16		-	-
values[0]	73	1			T140	1		T234	24		T244	10
values[1]	699	1			T3	27		T128	3		T129	30
values[2]	605	1			T3	10		T5	5		T29	13
values[3]	762	1			T2	1		T125	17		T153	25
values[4]	2850	1			T1	10		T10	14		T12	3
values[5]	880	1			T13	1		T29	19		T30	28
values[6]	674	1			T60	2		T202	14		T172	2
values[7]	548	1			T4	24		T47	8		T135	1
values[8]	821	1			T2	9		T13	1		T14	1
values[9]	899	1			T11	40		T31	10		T47	1
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	925	1			T3	27		T29	13		T128	3
values[1]	598	1			T2	1		T3	10		T5	5
values[2]	748	1			T125	17		T37	23		T79	3
values[3]	2806	1			T1	10		T10	14		T12	3
values[4]	944	1			T29	19		T30	28		T48	25
values[5]	628	1			T4	24		T60	2		T135	1
values[6]	715	1			T13	1		T47	8		T127	8
values[7]	686	1			T2	9		T14	1		T128	5
values[8]	601	1			T11	20		T31	10		T47	1
values[9]	162	1			T11	20		T226	8		T133	18
minimum	16441	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	14		T29	9		T129	31
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	13		T128	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T153	20		T136	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T3	10		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T131	14		T138	9		T160	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T125	8		T37	13		T79	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T1	10		T10	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T151	4		T231	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T29	10		T30	12		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T159	1		T164	1		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T172	1		T92	16		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	13		T60	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T47	8		T127	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T60	15		T135	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	1		T266	14		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T14	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	7		T47	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	4		T31	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T133	9		T100	1		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T11	13		T226	1		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16280	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	4		T129	21		T226	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T128	2		T131	2		T132	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T153	5		T136	6		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T127	14		T149	2		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T160	9		T43	4		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T125	9		T37	10		T79	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T60	1		T150	23		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T151	11		T41	2		T175	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T29	9		T30	16		T48	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T229	11		T176	8		T167	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T42	3		T46	1		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	11		T60	1		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T127	4		T125	3		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	16		T236	6		T180	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T283	1		T256	10		T284	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	8		T128	4		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	5		T241	12		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	4		T31	9		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T133	9		T100	10		T281	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T11	7		T226	7		T285	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	3		T29	1		T48	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T281	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T140	1		T234	12		T244	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T212	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	14		T129	17		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	13		T128	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	5		T29	9		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	10		T127	17		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T153	20		T136	4		T131	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T125	8		T37	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T1	10		T10	14		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T151	4		T231	17		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T13	1		T29	10		T30	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T135	1		T159	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T172	1		T92	16		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T60	1		T202	4		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	8		T39	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	13		T135	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T127	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T14	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	7		T47	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	17		T31	1		T151	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T281	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T282	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T234	12		T286	14		T287	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T212	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T129	13		T226	10		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T128	2		T131	2		T42	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T29	4		T129	8		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	14		T149	2		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T153	5		T136	6		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T125	9		T37	10		T238	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T60	1		T150	23		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T151	11		T79	2		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	9		T30	16		T48	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T236	8		T229	15		T167	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T160	11		T42	3		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T60	1		T202	10		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T259	15		T207	8		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	11		T131	9		T180	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T127	4		T125	3		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	8		T128	4		T60	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	5		T133	9		T144	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	11		T31	9		T151	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	1		T29	5		T129	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	1		T128	3		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T153	6		T136	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T3	1		T127	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	1		T138	1		T160	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T125	10		T37	15		T79	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T1	1		T10	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	12		T231	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T29	10		T30	17		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T159	1		T164	1		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T172	1		T92	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	12		T60	2		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	1		T47	1		T127	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T60	17		T135	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T154	1		T266	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	9		T14	1		T128	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	8		T47	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	5		T31	10		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T133	10		T100	11		T281	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T11	10		T226	8		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16433	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	13		T29	8		T129	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	12		T42	2		T266	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	4		T153	19		T136	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	9		T127	16		T202	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T131	13		T138	8		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T125	7		T37	8		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T1	9		T10	13		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T151	3		T231	16		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T29	9		T30	11		T48	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T229	8		T167	1		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T92	15		T42	2		T266	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	12		T202	3		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	7		T127	3		T129	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T60	14		T245	2		T236	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T266	13		T256	11		T288	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T151	11		T138	9		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	4		T228	8		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	3		T176	19		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T133	8		T289	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T11	10		T290	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T291	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T281	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T282	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T140	1		T234	13		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T212	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T129	14		T226	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T128	3		T131	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T29	5		T129	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T127	15		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T153	6		T136	7		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T125	10		T37	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	1		T10	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T151	12		T231	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	1		T29	10		T30	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	1		T159	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T172	1		T92	1		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	2		T202	11		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T47	1		T39	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	12		T135	1		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T127	5		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	9		T14	1		T128	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	8		T47	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T11	15		T31	10		T151	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T234	11		T244	9		T286	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	13		T129	16		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	12		T42	2		T266	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	4		T29	8		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	9		T127	16		T202	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	19		T136	3		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T125	7		T37	8		T279	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T1	9		T10	13		T27	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T151	3		T231	16		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T29	9		T30	11		T48	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T236	12		T229	10		T167	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T92	15		T160	12		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T202	3		T38	2		T44	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T47	7		T259	12		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	12		T131	13		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T127	3		T129	17		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T60	14		T138	9		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	4		T133	8		T266	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	13		T151	11		T176	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12