Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21803

1

T1

10

T3

14

T5

5

auto[ADC_CTRL_FILTER_COND_OUT]

3451

1

T2

10

T3

23

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19286

1

T2

9

T3

13

T6

20

auto[1]

5968

1

T1

10

T2

1

T3

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	107	1			T31	10		T100	11		T251	1
values[0]	54	1			T3	14		T244	10		T286	19
values[1]	782	1			T3	13		T128	3		T129	52
values[2]	547	1			T3	10		T5	5		T29	13
values[3]	759	1			T2	1		T125	17		T153	25
values[4]	2853	1			T1	10		T10	14		T12	3
values[5]	828	1			T29	19		T30	28		T48	25
values[6]	748	1			T60	2		T135	1		T202	14
values[7]	549	1			T4	24		T47	8		T135	1
values[8]	748	1			T2	9		T13	1		T14	1
values[9]	857	1			T11	40		T47	1		T151	26
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	819	1			T3	13		T29	13		T129	52
values[1]	556	1			T2	1		T3	10		T5	5
values[2]	812	1			T125	17		T153	25		T231	17
values[3]	2752	1			T1	10		T10	14		T12	3
values[4]	946	1			T29	19		T30	28		T48	25
values[5]	670	1			T60	2		T135	1		T202	14
values[6]	664	1			T4	24		T13	1		T47	8
values[7]	717	1			T2	9		T14	1		T128	5
values[8]	670	1			T11	20		T31	10		T47	1
values[9]	75	1			T11	20		T226	8		T166	1
minimum	16573	1			T3	14		T6	20		T7	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T29	9		T129	31		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	13		T137	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	5		T136	4		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T3	10		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T153	20		T131	14		T138	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T125	8		T231	17		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T1	10		T10	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	4		T137	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T29	10		T30	12		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T159	1		T164	1		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T172	1		T92	16		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T60	1		T135	1		T202	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	1		T47	8		T127	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	13		T60	15		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T154	1		T129	18		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T14	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	7		T47	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	4		T31	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T100	1		T281	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T11	13		T226	1		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16311	1			T3	14		T6	20		T7	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T128	1		T159	1		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	4		T129	21		T226	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	2		T132	10		T42	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T136	6		T132	12		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T127	14		T149	2		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T153	5		T160	9		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T125	9		T37	10		T79	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T60	1		T150	23		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T151	11		T41	2		T175	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T29	9		T30	16		T48	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T229	15		T176	8		T167	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	3		T44	6		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T60	1		T202	10		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T127	4		T125	3		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	11		T60	16		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T129	13		T241	12		T283	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	8		T128	4		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	5		T133	9		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	4		T31	9		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T100	10		T281	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T11	7		T226	7		T285	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	3		T29	1		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T128	2		T292	10		T210	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T100	1		T251	1		T293	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T31	1		T249	1		T289	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T3	14		T244	10		T286	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T129	31		T130	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	13		T128	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	5		T29	9		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T127	17		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	20		T136	4		T138	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T125	8		T37	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T1	10		T10	14		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T151	4		T231	17		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T29	10		T30	12		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T159	1		T229	12		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T172	1		T92	16		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	1		T135	1		T202	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T47	8		T39	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	13		T135	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T127	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	1		T14	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	7		T47	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	17		T151	12		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T100	10		T293	4		T294	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T31	9		T289	3		T282	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T286	14		T287	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	21		T142	8		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	2		T131	2		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T29	4		T226	10		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T127	14		T149	2		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T153	5		T136	6		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T125	9		T37	10		T79	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T60	1		T150	23		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	11		T41	2		T175	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T29	9		T30	16		T48	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T229	15		T167	8		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	3		T44	6		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T60	1		T202	10		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T259	15		T207	8		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	11		T131	9		T180	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T127	4		T125	3		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	8		T128	4		T60	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	5		T133	9		T241	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	11		T151	14		T226	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T29	5		T129	23		T226	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T137	1		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T136	7		T132	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T3	1		T127	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T153	6		T131	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T125	10		T231	1		T37	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T1	1		T10	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T151	12		T137	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T29	10		T30	17		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T159	1		T164	1		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T172	1		T92	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T60	2		T135	1		T202	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	1		T47	1		T127	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	12		T60	17		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T154	1		T129	14		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	9		T14	1		T128	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	8		T47	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	5		T31	10		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T100	11		T281	5		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	10		T226	8		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16458	1			T3	1		T6	20		T7	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T128	3		T159	1		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T29	8		T129	29		T142	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	12		T42	2		T266	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	4		T136	3		T227	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	9		T127	16		T202	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T153	19		T131	13		T138	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T125	7		T231	16		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T1	9		T10	13		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T151	3		T41	1		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T29	9		T30	11		T48	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T229	10		T167	1		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T92	15		T42	2		T266	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T202	3		T38	2		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T47	7		T127	3		T227	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	12		T60	14		T245	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T129	17		T241	13		T295	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	11		T138	9		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	4		T133	8		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	3		T176	19		T283	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T11	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T3	13		T175	8		T287	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T292	12		T210	2		T296	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T100	11		T251	1		T293	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T31	10		T249	1		T289	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T3	1		T244	1		T286	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T129	23		T130	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T128	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T29	5		T226	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T127	15		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T153	6		T136	7		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	1		T125	10		T37	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T1	1		T10	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T151	12		T231	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T29	10		T30	17		T48	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T159	1		T229	17		T167	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T172	1		T92	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	2		T135	1		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T47	1		T39	1		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	12		T135	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T127	5		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	9		T14	1		T128	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	8		T47	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T11	15		T151	15		T226	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T293	2		T294	16		T297	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T3	13		T244	9		T286	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T129	29		T175	8		T142	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	12		T42	2		T266	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	4		T29	8		T175	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	9		T127	16		T202	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T153	19		T136	3		T138	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	7		T37	8		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T1	9		T10	13		T27	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	3		T231	16		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T29	9		T30	11		T48	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T229	10		T167	1		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T92	15		T42	2		T266	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T202	3		T38	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T47	7		T259	12		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	12		T131	13		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T127	3		T129	17		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T60	14		T138	9		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	4		T133	8		T266	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	13		T151	11		T176	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12