Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25254 1 T1 10 T2 10 T3 37


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 21792 1 T1 10 T2 9 T3 37
auto[ADC_CTRL_FILTER_COND_OUT] 3462 1 T2 1 T11 20 T13 1


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19193 1 T2 1 T3 13 T6 20
auto[1] 6061 1 T1 10 T2 9 T3 24


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 21283 1 T1 10 T2 2 T3 37
auto[1] 3971 1 T2 8 T4 11 T11 19


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 459 1 T7 5 T11 9 T48 11
values[0] 102 1 T40 2 T253 1 T166 1
values[1] 733 1 T3 13 T11 28 T30 28
values[2] 2792 1 T1 10 T10 14 T11 12
values[3] 758 1 T3 10 T47 1 T60 31
values[4] 546 1 T29 19 T128 5 T60 2
values[5] 818 1 T3 14 T5 5 T202 22
values[6] 730 1 T4 24 T129 31 T202 14
values[7] 532 1 T135 1 T151 15 T129 30
values[8] 636 1 T2 1 T135 1 T125 4
values[9] 1138 1 T2 9 T13 2 T14 1
minimum 16010 1 T6 20 T7 149 T8 16


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 1028 1 T3 13 T11 40 T30 28
values[1] 2754 1 T1 10 T3 10 T10 14
values[2] 830 1 T60 31 T129 22 T48 1
values[3] 649 1 T5 5 T29 19 T128 5
values[4] 678 1 T3 14 T4 24 T202 14
values[5] 636 1 T129 31 T226 5 T130 2
values[6] 609 1 T2 1 T135 1 T125 4
values[7] 638 1 T31 10 T135 1 T37 23
values[8] 830 1 T2 9 T13 2 T14 1
values[9] 168 1 T266 14 T298 1 T264 13
minimum 16434 1 T6 20 T7 154 T8 16


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 21340 1 T1 1 T2 10 T3 3
auto[1] 3914 1 T1 9 T3 34 T4 12


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 240 1 T3 13 T11 11 T149 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 291 1 T11 13 T30 12 T47 8
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1443 1 T1 10 T3 10 T10 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T135 1 T191 1 T41 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T60 15 T129 14 T132 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 266 1 T48 1 T159 1 T133 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T5 5 T202 13 T79 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T29 10 T128 1 T60 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 234 1 T3 14 T4 13 T202 4
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T226 1 T172 1 T138 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T129 18 T130 1 T299 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T226 1 T130 1 T131 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T135 1 T125 1 T129 17
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T2 1 T151 4 T172 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T135 1 T172 1 T263 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T31 1 T37 13 T227 14
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 267 1 T2 1 T13 1 T29 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T13 1 T14 1 T128 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 50 1 T266 14 T298 1 T264 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 48 1 T300 7 T301 2 T302 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16283 1 T6 20 T7 154 T8 16
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T11 9 T149 2 T151 14
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 314 1 T11 7 T30 16 T60 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1012 1 T127 4 T150 23 T48 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T41 2 T167 8 T258 7
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T60 16 T129 8 T132 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 271 1 T133 9 T142 8 T176 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T202 9 T79 2 T131 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 101 1 T29 9 T128 4 T60 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T4 11 T202 10 T133 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T226 10 T236 6 T142 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T129 13 T42 3 T175 4
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T226 4 T42 4 T175 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T125 3 T129 13 T207 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T151 11 T229 4 T141 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T141 13 T144 1 T264 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T31 9 T37 10 T236 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T2 8 T29 4 T153 5
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T128 2 T127 14 T125 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 25 1 T264 12 T293 1 T303 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 45 1 T300 4 T301 1 T302 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 151 1 T11 3 T29 1 T48 1


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 412 1 T7 5 T11 9 T48 11
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 33 1 T304 18 T305 15 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 29 1 T40 2 T253 1 T166 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 37 1 T306 1 T23 2 T307 20
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T3 13 T11 4 T149 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T11 13 T30 12 T136 4
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1431 1 T1 10 T10 14 T11 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T47 8 T60 1 T135 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 224 1 T3 10 T47 1 T60 15
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T159 1 T133 9 T191 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T79 1 T164 1 T162 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T29 10 T128 1 T60 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 275 1 T3 14 T5 5 T202 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T172 1 T92 16 T138 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T4 13 T129 18 T202 4
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T226 2 T131 14 T41 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T135 1 T129 17 T134 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T151 4 T130 1 T229 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T135 1 T125 1 T153 20
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T2 1 T37 13 T172 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 336 1 T2 1 T13 1 T29 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 346 1 T13 1 T14 1 T31 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15859 1 T6 20 T7 149 T8 16
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T305 14 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 10 1 T281 10 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 26 1 T306 13 T217 13 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T11 4 T149 2 T151 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T11 7 T30 16 T136 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 984 1 T11 5 T127 4 T150 23
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T60 1 T41 2 T242 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T60 16 T129 8 T48 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T133 9 T142 8 T176 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 74 1 T79 2 T44 6 T142 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T29 9 T128 4 T60 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T202 9 T131 9 T133 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T132 12 T236 6 T141 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T4 11 T129 13 T202 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T226 14 T42 4 T175 5
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T129 13 T207 8 T292 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 89 1 T151 11 T229 12 T141 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T125 3 T153 5 T141 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T37 10 T43 4 T233 21
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 232 1 T2 8 T29 4 T229 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 224 1 T31 9 T128 2 T127 14
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 151 1 T11 3 T29 1 T48 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T3 1 T11 13 T149 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 372 1 T11 10 T30 17 T47 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1347 1 T1 1 T3 1 T10 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T135 1 T191 1 T41 4
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T60 17 T129 9 T132 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 326 1 T48 1 T159 1 T133 10
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T5 1 T202 10 T79 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T29 10 T128 5 T60 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T3 1 T4 12 T202 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T226 11 T172 1 T138 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T129 14 T130 1 T299 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T226 5 T130 1 T131 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T135 1 T125 4 T129 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T2 1 T151 12 T172 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 208 1 T135 1 T172 1 T263 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T31 10 T37 15 T227 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 236 1 T2 9 T13 1 T29 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T13 1 T14 1 T128 3
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 36 1 T266 1 T298 1 T264 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 58 1 T300 5 T301 2 T302 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16423 1 T6 20 T7 154 T8 16
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T3 12 T11 7 T151 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 233 1 T11 10 T30 11 T47 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1108 1 T1 9 T3 9 T10 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T41 1 T145 8 T167 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T60 14 T129 13 T228 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T133 8 T142 10 T176 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T5 4 T202 12 T131 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T29 9 T231 16 T92 15
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T3 13 T4 12 T202 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 108 1 T138 8 T245 2 T236 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T129 17 T42 2 T175 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T131 13 T42 2 T175 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T129 16 T228 8 T143 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T151 3 T229 2 T233 20
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 109 1 T168 6 T247 2 T19 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T37 8 T227 13 T236 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 216 1 T29 8 T153 19 T229 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T127 16 T125 7 T138 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 39 1 T266 13 T293 11 T303 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 35 1 T300 6 T301 1 T302 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 11 1 T279 11 - - - -


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 412 1 T7 5 T11 9 T48 11
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T304 1 T305 15 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 17 1 T40 2 T253 1 T166 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 32 1 T306 14 T23 2 T307 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T3 1 T11 5 T149 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 280 1 T11 10 T30 17 T136 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1308 1 T1 1 T10 1 T11 8
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T47 1 T60 2 T135 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 240 1 T3 1 T47 1 T60 17
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T159 1 T133 10 T191 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T79 3 T164 1 T162 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T29 10 T128 5 T60 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T3 1 T5 1 T202 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T172 1 T92 1 T138 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T4 12 T129 14 T202 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T226 16 T131 1 T41 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 200 1 T135 1 T129 14 T134 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T151 12 T130 1 T229 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T135 1 T125 4 T153 6
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T2 1 T37 15 T172 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 298 1 T2 9 T13 1 T29 5
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 294 1 T13 1 T14 1 T31 10
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16010 1 T6 20 T7 149 T8 16
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 31 1 T304 17 T305 14 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 22 1 T279 22 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 31 1 T307 19 T217 12 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T3 12 T11 3 T151 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T11 10 T30 11 T136 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1107 1 T1 9 T10 13 T11 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T47 7 T41 1 T167 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T3 9 T60 14 T129 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 135 1 T133 8 T142 10 T145 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 76 1 T228 3 T44 5 T17 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T29 9 T231 16 T144 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 235 1 T3 13 T5 4 T202 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T92 15 T138 8 T227 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T4 12 T129 17 T202 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T131 13 T42 2 T175 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T129 16 T143 8 T207 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 86 1 T151 3 T229 8 T247 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T153 19 T228 8 T143 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T37 8 T227 13 T43 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 270 1 T29 8 T266 13 T229 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 276 1 T127 16 T125 7 T138 9


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 21340 1 T1 1 T2 10 T3 3
auto[1] auto[0] 3914 1 T1 9 T3 34 T4 12