CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25254 | 1 | T1 | 10 | T2 | 10 | T3 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[ADC_CTRL_FILTER_COND_IN] | 21966 | 1 | T1 | 10 | T2 | 9 | T3 | 23 | ||||
auto[ADC_CTRL_FILTER_COND_OUT] | 3288 | 1 | T2 | 1 | T3 | 14 | T11 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19448 | 1 | T2 | 10 | T3 | 23 | T5 | 5 | ||||
auto[1] | 5806 | 1 | T1 | 10 | T3 | 14 | T4 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21283 | 1 | T1 | 10 | T2 | 2 | T3 | 37 | ||||
auto[1] | 3971 | 1 | T2 | 8 | T4 | 11 | T11 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 0 | 12 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
maximum | 40 | 1 | T266 | 14 | T217 | 26 | - | - | ||||
values[0] | 44 | 1 | T254 | 1 | T161 | 4 | T140 | 1 | ||||
values[1] | 643 | 1 | T4 | 24 | T149 | 3 | T125 | 17 | ||||
values[2] | 603 | 1 | T3 | 13 | T13 | 1 | T47 | 1 | ||||
values[3] | 821 | 1 | T3 | 24 | T13 | 1 | T29 | 13 | ||||
values[4] | 587 | 1 | T2 | 9 | T5 | 5 | T31 | 10 | ||||
values[5] | 657 | 1 | T48 | 1 | T130 | 2 | T131 | 3 | ||||
values[6] | 489 | 1 | T11 | 20 | T153 | 25 | T38 | 8 | ||||
values[7] | 871 | 1 | T2 | 1 | T29 | 19 | T135 | 1 | ||||
values[8] | 707 | 1 | T11 | 20 | T14 | 1 | T30 | 28 | ||||
values[9] | 3370 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
minimum | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 12 | 1 | 11 | 91.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
maximum | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 827 | 1 | T3 | 13 | T4 | 24 | T149 | 3 | ||||
values[1] | 653 | 1 | T13 | 2 | T47 | 1 | T151 | 26 | ||||
values[2] | 695 | 1 | T3 | 14 | T47 | 8 | T127 | 8 | ||||
values[3] | 678 | 1 | T2 | 9 | T3 | 10 | T5 | 5 | ||||
values[4] | 642 | 1 | T48 | 1 | T79 | 3 | T130 | 1 | ||||
values[5] | 563 | 1 | T11 | 8 | T153 | 25 | T38 | 8 | ||||
values[6] | 3059 | 1 | T1 | 10 | T2 | 1 | T10 | 14 | ||||
values[7] | 673 | 1 | T128 | 8 | T127 | 31 | T151 | 15 | ||||
values[8] | 771 | 1 | T14 | 1 | T48 | 25 | T226 | 8 | ||||
values[9] | 252 | 1 | T60 | 31 | T135 | 1 | T202 | 14 | ||||
minimum | 16441 | 1 | T6 | 20 | T7 | 154 | T8 | 16 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 182 | 1 | T3 | 13 | T4 | 13 | T149 | 1 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 276 | 1 | T136 | 4 | T138 | 10 | T253 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 132 | 1 | T151 | 12 | T226 | 1 | T92 | 16 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 260 | 1 | T13 | 2 | T47 | 1 | T172 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 139 | 1 | T47 | 8 | T127 | 4 | T60 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 243 | 1 | T3 | 14 | T231 | 17 | T227 | 3 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 267 | 1 | T2 | 1 | T3 | 10 | T5 | 5 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 160 | 1 | T31 | 1 | T60 | 1 | T129 | 18 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 173 | 1 | T79 | 1 | T130 | 1 | T159 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 167 | 1 | T48 | 1 | T42 | 8 | T166 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 221 | 1 | T153 | 20 | T38 | 5 | T133 | 10 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T11 | 4 | T131 | 28 | T41 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1539 | 1 | T1 | 10 | T10 | 14 | T11 | 13 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T2 | 1 | T11 | 7 | T154 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 258 | 1 | T128 | 2 | T127 | 17 | T151 | 4 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T129 | 14 | T244 | 10 | T167 | 11 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 284 | 1 | T14 | 1 | T48 | 14 | T226 | 1 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 147 | 1 | T172 | 1 | T132 | 1 | T133 | 9 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 7 | 1 | T141 | 1 | T308 | 3 | T309 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 98 | 1 | T60 | 15 | T135 | 1 | T202 | 4 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16282 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 156 | 1 | T4 | 11 | T149 | 2 | T125 | 9 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 213 | 1 | T136 | 6 | T235 | 9 | T242 | 13 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T151 | 14 | T226 | 10 | T180 | 5 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 156 | 1 | T175 | 5 | T292 | 10 | T155 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 138 | 1 | T127 | 4 | T60 | 1 | T226 | 4 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 175 | 1 | T229 | 4 | T141 | 13 | T45 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 120 | 1 | T2 | 8 | T29 | 4 | T131 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 131 | 1 | T31 | 9 | T60 | 1 | T129 | 13 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 141 | 1 | T79 | 2 | T229 | 12 | T142 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 161 | 1 | T42 | 4 | T142 | 8 | T237 | 14 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 118 | 1 | T153 | 5 | T38 | 3 | T133 | 7 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 105 | 1 | T11 | 4 | T131 | 9 | T237 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1145 | 1 | T11 | 7 | T29 | 9 | T30 | 16 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 200 | 1 | T11 | 5 | T202 | 9 | T236 | 14 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 178 | 1 | T128 | 6 | T127 | 14 | T151 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 83 | 1 | T129 | 8 | T167 | 10 | T212 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 206 | 1 | T48 | 11 | T226 | 7 | T42 | 3 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 134 | 1 | T132 | 12 | T133 | 9 | T160 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 16 | 1 | T141 | 2 | T308 | 3 | T310 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 131 | 1 | T60 | 16 | T202 | 10 | T311 | 13 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 159 | 1 | T11 | 3 | T29 | 1 | T48 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 3 | 45 | 93.75 | 3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [maximum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T217 | 13 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 14 | 1 | T266 | 14 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 20 | 1 | T161 | 4 | T140 | 1 | T176 | 11 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 5 | 1 | T254 | 1 | T312 | 1 | T240 | 3 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 137 | 1 | T4 | 13 | T149 | 1 | T125 | 8 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 246 | 1 | T136 | 4 | T138 | 10 | T253 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 140 | 1 | T3 | 13 | T151 | 12 | T226 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 176 | 1 | T13 | 1 | T47 | 1 | T172 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 160 | 1 | T3 | 10 | T29 | 9 | T127 | 4 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 319 | 1 | T3 | 14 | T13 | 1 | T231 | 17 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 212 | 1 | T2 | 1 | T5 | 5 | T47 | 8 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T31 | 1 | T60 | 1 | T129 | 18 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 200 | 1 | T130 | 1 | T131 | 1 | T159 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 154 | 1 | T48 | 1 | T130 | 1 | T227 | 14 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T153 | 20 | T38 | 5 | T159 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T11 | 11 | T131 | 14 | T42 | 8 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 308 | 1 | T29 | 10 | T135 | 1 | T125 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 163 | 1 | T2 | 1 | T154 | 1 | T202 | 13 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T11 | 13 | T14 | 1 | T30 | 12 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 170 | 1 | T129 | 14 | T134 | 1 | T236 | 11 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1668 | 1 | T1 | 10 | T10 | 14 | T12 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 269 | 1 | T60 | 15 | T135 | 1 | T202 | 4 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16271 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T217 | 13 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 8 | 1 | T176 | 8 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 11 | 1 | T312 | 10 | T240 | 1 | - | - | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 105 | 1 | T4 | 11 | T149 | 2 | T125 | 9 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 155 | 1 | T136 | 6 | T235 | 9 | T242 | 13 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T151 | 14 | T226 | 10 | T180 | 5 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 140 | 1 | T292 | 10 | T313 | 7 | T258 | 7 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 99 | 1 | T29 | 4 | T127 | 4 | T60 | 1 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 243 | 1 | T175 | 5 | T141 | 13 | T45 | 1 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 147 | 1 | T2 | 8 | T226 | 4 | T79 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 84 | 1 | T31 | 9 | T60 | 1 | T129 | 13 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 150 | 1 | T131 | 2 | T229 | 12 | T142 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 153 | 1 | T237 | 14 | T155 | 6 | T86 | 2 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 89 | 1 | T153 | 5 | T38 | 3 | T155 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 110 | 1 | T11 | 9 | T131 | 9 | T42 | 4 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 256 | 1 | T29 | 9 | T125 | 3 | T129 | 13 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 144 | 1 | T202 | 9 | T236 | 8 | T259 | 2 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 175 | 1 | T11 | 7 | T30 | 16 | T128 | 6 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 158 | 1 | T129 | 8 | T236 | 6 | T230 | 1 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1142 | 1 | T127 | 14 | T150 | 23 | T151 | 11 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T60 | 16 | T202 | 10 | T132 | 12 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 151 | 1 | T11 | 3 | T29 | 1 | T48 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 6 | 42 | 87.50 | 6 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [maximum] | * | -- | -- | 4 | |
* | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | -- | -- | 2 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 215 | 1 | T3 | 1 | T4 | 12 | T149 | 3 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 254 | 1 | T136 | 7 | T138 | 1 | T253 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 134 | 1 | T151 | 15 | T226 | 11 | T92 | 1 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 203 | 1 | T13 | 2 | T47 | 1 | T172 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 184 | 1 | T47 | 1 | T127 | 5 | T60 | 2 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 223 | 1 | T3 | 1 | T231 | 1 | T227 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 171 | 1 | T2 | 9 | T3 | 1 | T5 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 165 | 1 | T31 | 10 | T60 | 2 | T129 | 14 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 183 | 1 | T79 | 3 | T130 | 1 | T159 | 2 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 199 | 1 | T48 | 1 | T42 | 10 | T166 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 163 | 1 | T153 | 6 | T38 | 6 | T133 | 8 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T11 | 5 | T131 | 11 | T41 | 2 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1497 | 1 | T1 | 1 | T10 | 1 | T11 | 10 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 248 | 1 | T2 | 1 | T11 | 8 | T154 | 1 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 232 | 1 | T128 | 8 | T127 | 15 | T151 | 12 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 108 | 1 | T129 | 9 | T244 | 1 | T167 | 11 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 259 | 1 | T14 | 1 | T48 | 12 | T226 | 8 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 168 | 1 | T172 | 1 | T132 | 13 | T133 | 10 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 21 | 1 | T141 | 3 | T308 | 4 | T309 | 1 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 150 | 1 | T60 | 17 | T135 | 1 | T202 | 11 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16431 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 123 | 1 | T3 | 12 | T4 | 12 | T125 | 7 | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 235 | 1 | T136 | 3 | T138 | 9 | T235 | 8 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 103 | 1 | T151 | 11 | T92 | 15 | T245 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 213 | 1 | T227 | 8 | T175 | 8 | T143 | 3 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 93 | 1 | T47 | 7 | T127 | 3 | T160 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 195 | 1 | T3 | 13 | T231 | 16 | T227 | 2 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 216 | 1 | T3 | 9 | T5 | 4 | T29 | 8 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 126 | 1 | T129 | 17 | T266 | 2 | T163 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 131 | 1 | T175 | 8 | T229 | 8 | T142 | 10 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 129 | 1 | T42 | 2 | T142 | 8 | T279 | 11 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 176 | 1 | T153 | 19 | T38 | 2 | T133 | 9 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 92 | 1 | T11 | 3 | T131 | 26 | T227 | 13 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 1187 | 1 | T1 | 9 | T10 | 13 | T11 | 10 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 127 | 1 | T11 | 4 | T202 | 12 | T236 | 22 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 204 | 1 | T127 | 16 | T151 | 3 | T266 | 11 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 129 | 1 | T129 | 13 | T244 | 9 | T167 | 10 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 231 | 1 | T48 | 13 | T42 | 2 | T229 | 8 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 113 | 1 | T133 | 8 | T160 | 12 | T143 | 8 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 2 | 1 | T308 | 2 | - | - | - | - | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 79 | 1 | T60 | 14 | T202 | 3 | T266 | 13 | ||||
auto[1] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 10 | 1 | T176 | 10 | - | - | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 48 | 4 | 44 | 91.67 | 4 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] | [minimum] | * | -- | -- | 2 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] | [minimum] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 | |
[auto[1]] | [values[0]] | [auto[ADC_CTRL_FILTER_COND_OUT]] | 0 | 1 | 1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 14 | 1 | T217 | 14 | - | - | - | - | ||||
auto[0] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 1 | 1 | T266 | 1 | - | - | - | - | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 13 | 1 | T161 | 1 | T140 | 1 | T176 | 9 | ||||
auto[0] | values[0] | auto[ADC_CTRL_FILTER_COND_OUT] | 16 | 1 | T254 | 1 | T312 | 11 | T240 | 4 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 148 | 1 | T4 | 12 | T149 | 3 | T125 | 10 | ||||
auto[0] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 192 | 1 | T136 | 7 | T138 | 1 | T253 | 1 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 180 | 1 | T3 | 1 | T151 | 15 | T226 | 11 | ||||
auto[0] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 177 | 1 | T13 | 1 | T47 | 1 | T172 | 1 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 143 | 1 | T3 | 1 | T29 | 5 | T127 | 5 | ||||
auto[0] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 291 | 1 | T3 | 1 | T13 | 1 | T231 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 198 | 1 | T2 | 9 | T5 | 1 | T47 | 1 | ||||
auto[0] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 115 | 1 | T31 | 10 | T60 | 2 | T129 | 14 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 195 | 1 | T130 | 1 | T131 | 3 | T159 | 1 | ||||
auto[0] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 188 | 1 | T48 | 1 | T130 | 1 | T227 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 130 | 1 | T153 | 6 | T38 | 6 | T159 | 1 | ||||
auto[0] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 145 | 1 | T11 | 13 | T131 | 10 | T42 | 10 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 313 | 1 | T29 | 10 | T135 | 1 | T125 | 4 | ||||
auto[0] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 184 | 1 | T2 | 1 | T154 | 1 | T202 | 10 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 214 | 1 | T11 | 10 | T14 | 1 | T30 | 17 | ||||
auto[0] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 196 | 1 | T129 | 9 | T134 | 1 | T236 | 7 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1520 | 1 | T1 | 1 | T10 | 1 | T12 | 3 | ||||
auto[0] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 345 | 1 | T60 | 17 | T135 | 1 | T202 | 11 | ||||
auto[0] | minimum | auto[ADC_CTRL_FILTER_COND_IN] | 16422 | 1 | T6 | 20 | T7 | 154 | T8 | 16 | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_IN] | 12 | 1 | T217 | 12 | - | - | - | - | ||||
auto[1] | maximum | auto[ADC_CTRL_FILTER_COND_OUT] | 13 | 1 | T266 | 13 | - | - | - | - | ||||
auto[1] | values[0] | auto[ADC_CTRL_FILTER_COND_IN] | 15 | 1 | T161 | 3 | T176 | 10 | T224 | 2 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_IN] | 94 | 1 | T4 | 12 | T125 | 7 | T41 | 1 | ||||
auto[1] | values[1] | auto[ADC_CTRL_FILTER_COND_OUT] | 209 | 1 | T136 | 3 | T138 | 9 | T235 | 8 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_IN] | 107 | 1 | T3 | 12 | T151 | 11 | T245 | 2 | ||||
auto[1] | values[2] | auto[ADC_CTRL_FILTER_COND_OUT] | 139 | 1 | T227 | 8 | T143 | 3 | T292 | 12 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_IN] | 116 | 1 | T3 | 9 | T29 | 8 | T127 | 3 | ||||
auto[1] | values[3] | auto[ADC_CTRL_FILTER_COND_OUT] | 271 | 1 | T3 | 13 | T231 | 16 | T227 | 2 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_IN] | 161 | 1 | T5 | 4 | T47 | 7 | T138 | 8 | ||||
auto[1] | values[4] | auto[ADC_CTRL_FILTER_COND_OUT] | 113 | 1 | T129 | 17 | T266 | 2 | T163 | 2 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_IN] | 155 | 1 | T175 | 8 | T229 | 8 | T142 | 10 | ||||
auto[1] | values[5] | auto[ADC_CTRL_FILTER_COND_OUT] | 119 | 1 | T227 | 13 | T279 | 11 | T237 | 16 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_IN] | 110 | 1 | T153 | 19 | T38 | 2 | T155 | 8 | ||||
auto[1] | values[6] | auto[ADC_CTRL_FILTER_COND_OUT] | 104 | 1 | T11 | 7 | T131 | 13 | T42 | 2 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_IN] | 251 | 1 | T29 | 9 | T129 | 16 | T37 | 8 | ||||
auto[1] | values[7] | auto[ADC_CTRL_FILTER_COND_OUT] | 123 | 1 | T202 | 12 | T131 | 13 | T236 | 12 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_IN] | 165 | 1 | T11 | 10 | T30 | 11 | T241 | 13 | ||||
auto[1] | values[8] | auto[ADC_CTRL_FILTER_COND_OUT] | 132 | 1 | T129 | 13 | T236 | 10 | T244 | 9 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_IN] | 1290 | 1 | T1 | 9 | T10 | 13 | T27 | 7 | ||||
auto[1] | values[9] | auto[ADC_CTRL_FILTER_COND_OUT] | 215 | 1 | T60 | 14 | T202 | 3 | T133 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 4 | 2 | 2 | 50.00 | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | NUMBER | STATUS |
* | [auto[1]] | -- | -- | 2 |
wakeup_cp | clk_gate_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | auto[0] | 21340 | 1 | T1 | 1 | T2 | 10 | T3 | 3 | ||||
auto[1] | auto[0] | 3914 | 1 | T1 | 9 | T3 | 34 | T4 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |