Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19397

1

T6

20

T7

154

T8

16

auto[ADC_CTRL_FILTER_COND_OUT]

5857

1

T1

10

T2

10

T3

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19630

1

T2

1

T5

5

T6

20

auto[1]

5624

1

T1

10

T2

9

T3

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T168	11		T284	25		-	-
values[0]	46	1			T259	24		T279	12		T310	8
values[1]	871	1			T151	26		T136	10		T226	11
values[2]	561	1			T3	13		T5	5		T127	31
values[3]	689	1			T151	15		T226	5		T172	1
values[4]	582	1			T4	24		T13	1		T14	1
values[5]	679	1			T2	9		T11	12		T29	32
values[6]	620	1			T11	20		T129	22		T231	17
values[7]	747	1			T13	1		T31	10		T47	8
values[8]	706	1			T3	14		T30	28		T125	17
values[9]	3295	1			T1	10		T2	1		T3	10
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	959	1			T3	13		T151	26		T226	11
values[1]	2845	1			T1	10		T5	5		T10	14
values[2]	556	1			T4	24		T151	15		T226	5
values[3]	672	1			T2	9		T11	12		T13	1
values[4]	642	1			T14	1		T29	32		T128	3
values[5]	582	1			T11	20		T60	31		T149	3
values[6]	760	1			T13	1		T31	10		T47	8
values[7]	748	1			T3	24		T30	28		T47	1
values[8]	849	1			T11	8		T128	5		T135	1
values[9]	209	1			T2	1		T60	2		T92	16
minimum	16432	1			T6	20		T7	154		T8	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	13		T130	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T3	13		T151	12		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	17		T136	4		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1522	1			T1	10		T5	5		T10	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T226	1		T161	4		T245	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	13		T151	4		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T134	1		T227	14		T245	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	1		T11	7		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T29	9		T127	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	10		T128	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	13		T60	15		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T138	9		T40	2		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	1		T31	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T47	8		T132	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T30	12		T154	1		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	24		T47	1		T125	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T128	1		T135	1		T129	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	4		T131	14		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T130	1		T244	9		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	1		T60	1		T92	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16272	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	10		T141	2		T207	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T151	14		T226	10		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T127	14		T136	6		T133	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1018	1			T150	23		T260	5		T275	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T226	4		T144	2		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	11		T151	11		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T233	13		T169	11		T314	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	8		T11	5		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	4		T127	4		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	9		T128	2		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	7		T60	16		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	7		T42	3		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	9		T125	3		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	12		T233	8		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	16		T38	3		T79	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T125	9		T202	9		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T128	4		T129	13		T131	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	4		T131	9		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T169	11		T243	2		T204	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T60	1		T235	9		T295	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	3		T29	1		T48	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T284	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T168	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T279	12		T310	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	11		T315	1		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	4		T37	13		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T151	12		T226	1		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T127	17		T137	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	13		T5	5		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T226	1		T133	9		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	4		T172	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	1		T245	5		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	13		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	9		T127	4		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	1		T11	7		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	13		T129	14		T231	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	2		T133	10		T42	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T31	1		T60	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	8		T132	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	12		T154	1		T202	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	14		T125	8		T202	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T128	1		T135	1		T129	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1678	1			T1	10		T2	1		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T310	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	6		T37	10		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T151	14		T226	10		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T127	14		T180	5		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T237	14		T256	10		T309	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T226	4		T133	9		T242	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	11		T236	6		T239	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	2		T259	2		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T4	11		T153	5		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	4		T127	4		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	8		T11	5		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T11	7		T129	8		T317	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	7		T42	3		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T31	9		T60	16		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T132	12		T233	8		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	16		T202	10		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T125	9		T202	9		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T128	4		T129	13		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1134	1			T11	4		T60	1		T150	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	15		T130	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T3	1		T151	15		T226	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T127	15		T136	7		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1355	1			T1	1		T5	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T226	5		T161	1		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	12		T151	12		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T134	1		T227	1		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	9		T11	8		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T29	5		T127	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	10		T128	3		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	10		T60	17		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	1		T40	2		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	1		T31	10		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	1		T132	13		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T30	17		T154	1		T38	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	2		T47	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T128	5		T135	1		T129	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	5		T131	10		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T130	1		T244	1		T169	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T2	1		T60	2		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16432	1			T6	20		T7	154		T8	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	8		T207	7		T279	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	12		T151	11		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T127	16		T136	3		T133	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1185	1			T1	9		T5	4		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T161	3		T245	1		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	12		T151	3		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T227	13		T245	2		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	4		T153	19		T129	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	8		T127	3		T175	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	9		T41	1		T44	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	10		T60	14		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	8		T133	9		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T202	3		T143	3		T241	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	7		T266	2		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	11		T38	2		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	22		T125	7		T202	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	16		T160	2		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	3		T131	13		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T244	8		T243	4		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T92	15		T235	8		T308	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T284	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T168	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T279	1		T310	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T259	14		T315	1		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T136	7		T37	15		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T151	15		T226	11		T160	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T127	15		T137	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T5	1		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T226	5		T133	10		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	12		T172	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T245	2		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	12		T13	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T29	5		T127	5		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	9		T11	8		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	10		T129	9		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	2		T133	8		T42	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	1		T31	10		T60	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	1		T132	13		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T30	17		T154	1		T202	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T125	10		T202	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T128	5		T135	1		T129	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1513	1			T1	1		T2	1		T3	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T168	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T279	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T259	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	3		T37	8		T311	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T151	11		T160	12		T227	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T127	16		T229	8		T207	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	12		T5	4		T237	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T133	8		T161	3		T279	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T151	3		T236	10		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T245	3		T228	3		T144	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	12		T153	19		T129	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T29	8		T127	3		T227	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	4		T29	9		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	10		T129	13		T231	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T133	9		T42	2		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	14		T143	3		T155	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	7		T228	8		T318	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	11		T202	3		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	13		T125	7		T202	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T129	16		T160	2		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1299	1			T1	9		T3	9		T10	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12