Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25254

1

T1

10

T2

10

T3

37

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21786

1

T1

10

T2

9

T3

37

auto[ADC_CTRL_FILTER_COND_OUT]

3468

1

T2

1

T11

20

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19535

1

T2

10

T3

37

T6

20

auto[1]

5719

1

T1

10

T4

24

T5

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21283

1

T1

10

T2

2

T3

37

auto[1]

3971

1

T2

8

T4

11

T11

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	328	1			T60	31		T133	17		T145	13
values[0]	10	1			T3	10		-	-		-	-
values[1]	595	1			T3	27		T4	24		T128	3
values[2]	592	1			T149	3		T153	25		T154	1
values[3]	666	1			T128	5		T127	31		T60	2
values[4]	564	1			T13	1		T14	1		T60	2
values[5]	2896	1			T1	10		T10	14		T12	3
values[6]	851	1			T11	20		T47	1		T125	17
values[7]	661	1			T31	10		T202	14		T48	1
values[8]	762	1			T2	1		T5	5		T11	8
values[9]	907	1			T2	9		T11	12		T127	8
minimum	16422	1			T6	20		T7	154		T8	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	554	1			T3	13		T128	3		T135	2
values[1]	579	1			T60	2		T149	3		T153	25
values[2]	639	1			T128	5		T127	31		T39	1
values[3]	2680	1			T1	10		T10	14		T12	3
values[4]	893	1			T30	28		T125	21		T151	26
values[5]	764	1			T11	20		T47	1		T129	22
values[6]	630	1			T11	8		T31	10		T202	14
values[7]	849	1			T2	10		T5	5		T13	1
values[8]	776	1			T11	12		T127	8		T60	31
values[9]	242	1			T227	9		T176	14		T237	31
minimum	16648	1			T3	24		T4	24		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

3914

1

T1

9

T3

34

T4

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	13		T128	1		T129	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	2		T130	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	1		T154	1		T159	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	1		T153	20		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T175	9		T162	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T128	1		T127	17		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T1	10		T10	14		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T60	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T226	2		T92	16		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T30	12		T125	9		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T47	1		T231	17		T37	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	13		T129	14		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	4		T202	4		T136	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	1		T172	1		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	1		T5	5		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T13	1		T29	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	7		T133	9		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T127	4		T60	15		T79	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T227	9		T176	10		T237	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T233	13		T206	1		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16341	1			T3	24		T4	13		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T47	8		T241	14		T237	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T128	2		T129	13		T132	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T132	10		T41	2		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T149	2		T42	3		T141	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	1		T153	5		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T234	12		T126	14		T292	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T128	4		T127	14		T142	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T150	23		T151	11		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T60	1		T180	5		T235	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T226	11		T236	14		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T30	16		T125	12		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	10		T142	1		T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	7		T129	8		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	4		T202	10		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	9		T160	11		T42	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	8		T29	9		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	4		T131	9		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	5		T133	9		T148	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T127	4		T60	16		T79	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T176	4		T237	14		T238	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T233	13		T222	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	11		T11	3		T29	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T241	12		T237	2		T277	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T176	10		T237	17		T319	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T60	15		T133	10		T145	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T3	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	27		T4	13		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	8		T135	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T149	1		T154	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T153	20		T172	1		T229	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T159	1		T162	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T128	1		T127	17		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T137	1		T245	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T60	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1475	1			T1	10		T10	14		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T30	12		T125	1		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T47	1		T231	17		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	13		T125	8		T129	31
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T202	4		T136	4		T37	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	1		T48	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	5		T11	4		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T13	1		T29	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T2	1		T11	7		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T127	4		T79	1		T227	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16271	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T176	4		T237	14		T320	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T60	16		T133	7		T239	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	11		T128	2		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	10		T41	2		T241	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T149	2		T42	3		T141	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T153	5		T229	11		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T234	12		T126	14		T292	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T128	4		T127	14		T60	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T207	6		T242	13		T33	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	1		T176	8		T235	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T150	23		T151	11		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	16		T125	3		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T175	4		T142	1		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	7		T125	9		T129	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T202	10		T136	6		T37	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	9		T160	11		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	4		T29	9		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	4		T131	9		T132	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	8		T11	5		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	4		T79	2		T229	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T29	1		T48	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T128	3		T129	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T135	2		T130	1		T132	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T149	3		T154	1		T159	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T60	2		T153	6		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T175	1		T162	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T128	5		T127	15		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	1		T10	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T60	2		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T226	13		T92	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T30	17		T125	14		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T47	1		T231	1		T37	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	10		T129	9		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	5		T202	11		T136	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	10		T172	1		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	9		T5	1		T29	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T13	1		T29	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	8		T133	10		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T127	5		T60	17		T79	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T227	1		T176	5		T237	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T233	14		T206	1		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16475	1			T3	2		T4	12		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T47	1		T241	13		T237	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	12		T129	17		T138	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	1		T300	6		T321	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T42	2		T230	3		T295	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T153	19		T229	8		T219	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T175	8		T234	11		T244	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T127	16		T142	18		T176	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T1	9		T10	13		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T228	3		T235	8		T322	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T92	15		T227	2		T236	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T30	11		T125	7		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T231	16		T37	8		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	10		T129	13		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	3		T202	3		T136	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T160	12		T42	2		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	4		T29	9		T175	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	8		T131	13		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	4		T133	8		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T127	3		T60	14		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T227	8		T176	9		T237	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T233	12		T222	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T3	22		T4	12		T291	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T47	7		T241	13		T237	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T176	5		T237	15		T319	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T60	17		T133	8		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T3	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	2		T4	12		T128	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	1		T135	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T149	3		T154	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T153	6		T172	1		T229	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T159	1		T162	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T128	5		T127	15		T60	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T137	1		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T60	2		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T1	1		T10	1		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T30	17		T125	4		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T47	1		T231	1		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	10		T125	10		T129	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T202	11		T136	7		T37	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	10		T48	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	1		T11	5		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T13	1		T29	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T2	9		T11	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T127	5		T79	3		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16422	1			T6	20		T7	154		T8	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T176	9		T237	16		T319	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T60	14		T133	9		T145	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T3	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	25		T4	12		T129	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	7		T41	1		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T42	2		T46	2		T230	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	19		T229	8		T233	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T234	11		T244	9		T126	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	16		T142	18		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T245	2		T175	8		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T228	3		T176	10		T235	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T1	9		T10	13		T27	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	11		T151	11		T48	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T231	16		T227	2		T175	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	10		T125	7		T129	29
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T202	3		T136	3		T37	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	13		T160	12		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	4		T11	3		T29	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	8		T131	13		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	4		T133	8		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T127	3		T227	13		T229	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21340

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

3914

1

T1

9

T3

34

T4

12