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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.09


Total test records in report: 919
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T240 /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3308775691 Aug 06 07:33:02 PM PDT 24 Aug 06 07:38:46 PM PDT 24 179860660757 ps
T792 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2797730632 Aug 06 07:38:01 PM PDT 24 Aug 06 07:45:27 PM PDT 24 219744486377 ps
T793 /workspace/coverage/default/13.adc_ctrl_filters_both.1628244977 Aug 06 07:32:58 PM PDT 24 Aug 06 07:38:51 PM PDT 24 536581487756 ps
T794 /workspace/coverage/default/31.adc_ctrl_stress_all.760811250 Aug 06 07:36:11 PM PDT 24 Aug 06 07:48:16 PM PDT 24 328520794730 ps
T795 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2730398774 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 472080940 ps
T63 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3182328342 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 522807823 ps
T87 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.453310075 Aug 06 07:31:18 PM PDT 24 Aug 06 07:31:20 PM PDT 24 416853242 ps
T25 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.669097924 Aug 06 07:31:32 PM PDT 24 Aug 06 07:31:34 PM PDT 24 711636530 ps
T32 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3940314138 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:47 PM PDT 24 4279407041 ps
T64 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2596997997 Aug 06 07:31:52 PM PDT 24 Aug 06 07:31:53 PM PDT 24 540513320 ps
T69 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3815572029 Aug 06 07:31:16 PM PDT 24 Aug 06 07:31:18 PM PDT 24 697770851 ps
T796 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3872909072 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:35 PM PDT 24 377047244 ps
T61 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4054005158 Aug 06 07:31:09 PM PDT 24 Aug 06 07:31:29 PM PDT 24 7751534371 ps
T56 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4165421338 Aug 06 07:31:57 PM PDT 24 Aug 06 07:32:07 PM PDT 24 2475959169 ps
T62 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2861848909 Aug 06 07:31:57 PM PDT 24 Aug 06 07:32:02 PM PDT 24 5007530671 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.66506348 Aug 06 07:31:36 PM PDT 24 Aug 06 07:31:39 PM PDT 24 1298154854 ps
T72 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.273287802 Aug 06 07:31:16 PM PDT 24 Aug 06 07:31:18 PM PDT 24 646012196 ps
T103 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1930292567 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 520531552 ps
T57 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2668802865 Aug 06 07:31:36 PM PDT 24 Aug 06 07:31:47 PM PDT 24 4428338792 ps
T797 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2212944765 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:57 PM PDT 24 469180387 ps
T104 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3873296646 Aug 06 07:31:11 PM PDT 24 Aug 06 07:31:13 PM PDT 24 501486314 ps
T105 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2383736352 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:57 PM PDT 24 545644255 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1981731707 Aug 06 07:31:09 PM PDT 24 Aug 06 07:31:10 PM PDT 24 335366156 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4164422769 Aug 06 07:31:14 PM PDT 24 Aug 06 07:31:16 PM PDT 24 347334662 ps
T798 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1859324752 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:01 PM PDT 24 508179719 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.248780851 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:38 PM PDT 24 1213219730 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.808790082 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:44 PM PDT 24 2621257162 ps
T65 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2547434740 Aug 06 07:31:11 PM PDT 24 Aug 06 07:31:24 PM PDT 24 8777168886 ps
T59 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2310649814 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:59 PM PDT 24 2233826120 ps
T120 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3521694816 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:39 PM PDT 24 2045076166 ps
T799 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.438522216 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:00 PM PDT 24 360559761 ps
T800 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.114863133 Aug 06 07:32:13 PM PDT 24 Aug 06 07:32:14 PM PDT 24 479796247 ps
T75 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3258888238 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 476706114 ps
T58 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3118610869 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:59 PM PDT 24 4935162571 ps
T121 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2879356956 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:56 PM PDT 24 411854723 ps
T70 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2146595427 Aug 06 07:31:58 PM PDT 24 Aug 06 07:32:00 PM PDT 24 920752582 ps
T801 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3170479693 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:57 PM PDT 24 334406418 ps
T802 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1653565145 Aug 06 07:31:12 PM PDT 24 Aug 06 07:31:13 PM PDT 24 405192300 ps
T803 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2046390095 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:01 PM PDT 24 375070198 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4231899999 Aug 06 07:31:12 PM PDT 24 Aug 06 07:31:13 PM PDT 24 502735199 ps
T805 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2576589223 Aug 06 07:31:54 PM PDT 24 Aug 06 07:32:00 PM PDT 24 2383439622 ps
T806 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.176900118 Aug 06 07:32:20 PM PDT 24 Aug 06 07:32:21 PM PDT 24 435073895 ps
T807 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1381732986 Aug 06 07:31:55 PM PDT 24 Aug 06 07:32:06 PM PDT 24 4099383264 ps
T808 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2446286388 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:14 PM PDT 24 378989967 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2721557501 Aug 06 07:31:58 PM PDT 24 Aug 06 07:32:02 PM PDT 24 2046119084 ps
T74 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.746474710 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 619429010 ps
T109 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2015867591 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:02 PM PDT 24 320792926 ps
T110 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4053867879 Aug 06 07:31:18 PM PDT 24 Aug 06 07:31:51 PM PDT 24 50247417405 ps
T111 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.905005917 Aug 06 07:31:36 PM PDT 24 Aug 06 07:31:37 PM PDT 24 415009368 ps
T810 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3278125257 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:00 PM PDT 24 400834856 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3916634490 Aug 06 07:31:09 PM PDT 24 Aug 06 07:32:45 PM PDT 24 42870988485 ps
T811 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.438974055 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:34 PM PDT 24 379834271 ps
T812 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.827716221 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:59 PM PDT 24 4796066763 ps
T354 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1921633723 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:43 PM PDT 24 9062270830 ps
T813 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1138438490 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 336796027 ps
T814 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1900150660 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:02 PM PDT 24 401128274 ps
T815 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.110051910 Aug 06 07:32:19 PM PDT 24 Aug 06 07:32:20 PM PDT 24 507609487 ps
T816 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1116158488 Aug 06 07:31:37 PM PDT 24 Aug 06 07:31:38 PM PDT 24 505671040 ps
T817 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3804597340 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:56 PM PDT 24 416278810 ps
T113 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.779823667 Aug 06 07:31:58 PM PDT 24 Aug 06 07:31:59 PM PDT 24 324577358 ps
T818 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.23099286 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:40 PM PDT 24 4673022900 ps
T819 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3739341999 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:37 PM PDT 24 334961321 ps
T820 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3610767019 Aug 06 07:31:14 PM PDT 24 Aug 06 07:31:15 PM PDT 24 295781299 ps
T821 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4073919856 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 322982654 ps
T822 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3224504767 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:57 PM PDT 24 325530535 ps
T823 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2853720383 Aug 06 07:32:01 PM PDT 24 Aug 06 07:32:02 PM PDT 24 293183160 ps
T824 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.670501969 Aug 06 07:31:57 PM PDT 24 Aug 06 07:31:58 PM PDT 24 571777712 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3019329598 Aug 06 07:31:32 PM PDT 24 Aug 06 07:31:36 PM PDT 24 1263483726 ps
T115 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3333616407 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:55 PM PDT 24 513894260 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.52631139 Aug 06 07:31:37 PM PDT 24 Aug 06 07:31:38 PM PDT 24 567589579 ps
T826 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1745144705 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:57 PM PDT 24 513936948 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2333017853 Aug 06 07:31:13 PM PDT 24 Aug 06 07:31:36 PM PDT 24 28958099911 ps
T827 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2091952253 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 473409580 ps
T828 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.179781058 Aug 06 07:32:15 PM PDT 24 Aug 06 07:32:16 PM PDT 24 380440678 ps
T829 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.841772033 Aug 06 07:32:18 PM PDT 24 Aug 06 07:32:19 PM PDT 24 292819548 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2374860218 Aug 06 07:31:14 PM PDT 24 Aug 06 07:31:15 PM PDT 24 1294896667 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3446808652 Aug 06 07:31:55 PM PDT 24 Aug 06 07:32:00 PM PDT 24 4474001638 ps
T832 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1040050022 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:56 PM PDT 24 549423018 ps
T833 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2878255600 Aug 06 07:31:17 PM PDT 24 Aug 06 07:31:19 PM PDT 24 640726553 ps
T834 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3806833240 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:56 PM PDT 24 371327718 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3779297752 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:36 PM PDT 24 817692051 ps
T117 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3012719197 Aug 06 07:31:36 PM PDT 24 Aug 06 07:31:37 PM PDT 24 446332838 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2446420227 Aug 06 07:31:57 PM PDT 24 Aug 06 07:32:01 PM PDT 24 3932304371 ps
T71 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3146081140 Aug 06 07:31:37 PM PDT 24 Aug 06 07:31:40 PM PDT 24 466994880 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.942576851 Aug 06 07:31:09 PM PDT 24 Aug 06 07:31:12 PM PDT 24 808401517 ps
T838 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3381292534 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:37 PM PDT 24 510846235 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1272471578 Aug 06 07:31:53 PM PDT 24 Aug 06 07:31:55 PM PDT 24 489548634 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1312034007 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:34 PM PDT 24 451025464 ps
T841 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1226658272 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:57 PM PDT 24 364396135 ps
T118 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.619348423 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 361553725 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2925637254 Aug 06 07:31:32 PM PDT 24 Aug 06 07:31:33 PM PDT 24 310694437 ps
T843 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2455768252 Aug 06 07:31:09 PM PDT 24 Aug 06 07:31:12 PM PDT 24 1260719608 ps
T844 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3867199551 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:12 PM PDT 24 365746671 ps
T845 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.978769860 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:37 PM PDT 24 405169528 ps
T846 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3336213587 Aug 06 07:31:32 PM PDT 24 Aug 06 07:31:34 PM PDT 24 464498334 ps
T847 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2326534841 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:55 PM PDT 24 455069154 ps
T848 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1157563846 Aug 06 07:31:14 PM PDT 24 Aug 06 07:31:15 PM PDT 24 409460365 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1724188913 Aug 06 07:32:01 PM PDT 24 Aug 06 07:32:03 PM PDT 24 508091094 ps
T850 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2267482805 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:00 PM PDT 24 624096844 ps
T851 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3739091539 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 485936693 ps
T852 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1051754191 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:09 PM PDT 24 5400549956 ps
T853 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1731710281 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:02 PM PDT 24 518476330 ps
T854 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3895536132 Aug 06 07:31:54 PM PDT 24 Aug 06 07:32:06 PM PDT 24 4411090626 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4476292 Aug 06 07:31:58 PM PDT 24 Aug 06 07:32:01 PM PDT 24 2002658123 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3967276067 Aug 06 07:31:09 PM PDT 24 Aug 06 07:31:11 PM PDT 24 301914335 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1524626594 Aug 06 07:31:54 PM PDT 24 Aug 06 07:32:16 PM PDT 24 8425836776 ps
T858 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1674407780 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:57 PM PDT 24 338066034 ps
T859 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.828270752 Aug 06 07:31:53 PM PDT 24 Aug 06 07:31:54 PM PDT 24 518327970 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.739457222 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:37 PM PDT 24 453410439 ps
T861 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1354228483 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:48 PM PDT 24 9193433292 ps
T862 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.200188391 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:57 PM PDT 24 2003909908 ps
T863 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3040072834 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:01 PM PDT 24 321060854 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2810534742 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:52 PM PDT 24 4256939763 ps
T865 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.813922000 Aug 06 07:32:15 PM PDT 24 Aug 06 07:32:17 PM PDT 24 329399300 ps
T866 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2177402722 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:45 PM PDT 24 7703751303 ps
T867 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.41034342 Aug 06 07:31:35 PM PDT 24 Aug 06 07:34:51 PM PDT 24 53286708365 ps
T868 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1896281740 Aug 06 07:31:57 PM PDT 24 Aug 06 07:31:58 PM PDT 24 359509617 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2045190340 Aug 06 07:31:57 PM PDT 24 Aug 06 07:31:59 PM PDT 24 436264833 ps
T870 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.351884231 Aug 06 07:31:53 PM PDT 24 Aug 06 07:31:55 PM PDT 24 590633317 ps
T871 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4185286627 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:55 PM PDT 24 432874912 ps
T872 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3011237565 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 298735535 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3045052839 Aug 06 07:31:57 PM PDT 24 Aug 06 07:31:59 PM PDT 24 570503905 ps
T874 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1049420946 Aug 06 07:31:17 PM PDT 24 Aug 06 07:31:27 PM PDT 24 4018609653 ps
T875 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.959766960 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 473750232 ps
T876 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3961227316 Aug 06 07:31:57 PM PDT 24 Aug 06 07:31:59 PM PDT 24 475826809 ps
T877 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1349499103 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 2017111704 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2836868558 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:35 PM PDT 24 502254930 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2446065798 Aug 06 07:31:17 PM PDT 24 Aug 06 07:31:40 PM PDT 24 8505169228 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1760322750 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:57 PM PDT 24 4356660632 ps
T881 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.466898130 Aug 06 07:32:19 PM PDT 24 Aug 06 07:32:20 PM PDT 24 550642182 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2219494789 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:56 PM PDT 24 297941149 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1471561494 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:00 PM PDT 24 429691800 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3122352885 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:44 PM PDT 24 4655518860 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3807917563 Aug 06 07:31:55 PM PDT 24 Aug 06 07:32:00 PM PDT 24 4280195717 ps
T886 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3591007212 Aug 06 07:31:52 PM PDT 24 Aug 06 07:32:03 PM PDT 24 4370189337 ps
T887 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2552585052 Aug 06 07:31:55 PM PDT 24 Aug 06 07:31:59 PM PDT 24 4835927011 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1079557931 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:37 PM PDT 24 340547057 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2057275652 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:34 PM PDT 24 548640468 ps
T890 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2146319460 Aug 06 07:31:57 PM PDT 24 Aug 06 07:32:00 PM PDT 24 471112561 ps
T891 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1125759381 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 502428492 ps
T76 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1821760583 Aug 06 07:31:54 PM PDT 24 Aug 06 07:32:01 PM PDT 24 4322294234 ps
T892 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.283360077 Aug 06 07:31:56 PM PDT 24 Aug 06 07:32:00 PM PDT 24 4552085990 ps
T893 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.346105552 Aug 06 07:32:00 PM PDT 24 Aug 06 07:32:01 PM PDT 24 555789143 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1079047281 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 383399067 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3300842549 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:38 PM PDT 24 1473639861 ps
T896 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4002900596 Aug 06 07:31:53 PM PDT 24 Aug 06 07:31:55 PM PDT 24 741537422 ps
T897 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.913937790 Aug 06 07:31:35 PM PDT 24 Aug 06 07:31:39 PM PDT 24 520931004 ps
T898 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2472901904 Aug 06 07:31:32 PM PDT 24 Aug 06 07:31:34 PM PDT 24 565660816 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1512926661 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:55 PM PDT 24 483493645 ps
T900 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.633302168 Aug 06 07:31:33 PM PDT 24 Aug 06 07:31:45 PM PDT 24 8264750735 ps
T901 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2518950412 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:58 PM PDT 24 4275615073 ps
T902 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3055989221 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 498014193 ps
T903 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2655414804 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:59 PM PDT 24 759649962 ps
T904 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.956384108 Aug 06 07:31:12 PM PDT 24 Aug 06 07:31:14 PM PDT 24 5254276542 ps
T905 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3886725379 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:55 PM PDT 24 493203378 ps
T906 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1947457083 Aug 06 07:32:20 PM PDT 24 Aug 06 07:32:21 PM PDT 24 323187510 ps
T907 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1567868173 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 488630241 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2943730240 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:58 PM PDT 24 473926866 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3541438363 Aug 06 07:31:54 PM PDT 24 Aug 06 07:31:56 PM PDT 24 332961487 ps
T910 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.384624200 Aug 06 07:31:52 PM PDT 24 Aug 06 07:31:54 PM PDT 24 570595453 ps
T911 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4094276441 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:12 PM PDT 24 399706522 ps
T912 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3044448099 Aug 06 07:31:10 PM PDT 24 Aug 06 07:31:11 PM PDT 24 1057542303 ps
T913 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.891756251 Aug 06 07:31:34 PM PDT 24 Aug 06 07:31:35 PM PDT 24 513249318 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1395053965 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:06 PM PDT 24 4844008505 ps
T915 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2408475795 Aug 06 07:31:56 PM PDT 24 Aug 06 07:31:57 PM PDT 24 515470165 ps
T916 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2131908431 Aug 06 07:31:58 PM PDT 24 Aug 06 07:32:00 PM PDT 24 577830376 ps
T917 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3972498776 Aug 06 07:32:12 PM PDT 24 Aug 06 07:32:13 PM PDT 24 450004007 ps
T918 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3868650225 Aug 06 07:31:54 PM PDT 24 Aug 06 07:32:01 PM PDT 24 8451473756 ps
T919 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2906322243 Aug 06 07:31:59 PM PDT 24 Aug 06 07:32:00 PM PDT 24 606638772 ps

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3620601692
Short name T3
Test name
Test status
Simulation time 543090634035 ps
CPU time 275.44 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:42:06 PM PDT 24
Peak memory 201452 kb
Host smart-f753ebe2-fc24-4187-812c-92fba98491da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620601692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3620601692
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.210103296
Short name T11
Test name
Test status
Simulation time 277019969749 ps
CPU time 201.51 seconds
Started Aug 06 07:33:45 PM PDT 24
Finished Aug 06 07:37:06 PM PDT 24
Peak memory 217784 kb
Host smart-85dd4196-47ff-4b83-a50a-3f233ccc5a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210103296 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.210103296
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3170649153
Short name T48
Test name
Test status
Simulation time 550404849616 ps
CPU time 1794.91 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 08:06:48 PM PDT 24
Peak memory 218212 kb
Host smart-886a7d3b-bacb-4b97-aefe-d3cbac418138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170649153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3170649153
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3509885304
Short name T60
Test name
Test status
Simulation time 524708199864 ps
CPU time 509.92 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:41:51 PM PDT 24
Peak memory 201376 kb
Host smart-1ec2b5ad-b7bd-42b0-a3cb-773ef1e9e959
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509885304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3509885304
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3933286239
Short name T207
Test name
Test status
Simulation time 477718489690 ps
CPU time 521.15 seconds
Started Aug 06 07:35:23 PM PDT 24
Finished Aug 06 07:44:04 PM PDT 24
Peak memory 201820 kb
Host smart-2d1d2455-e147-4029-8903-71a17bbb94a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933286239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3933286239
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3350831755
Short name T131
Test name
Test status
Simulation time 1583365668667 ps
CPU time 1033.64 seconds
Started Aug 06 07:33:16 PM PDT 24
Finished Aug 06 07:50:29 PM PDT 24
Peak memory 209984 kb
Host smart-906c88be-e6e2-42e9-b4e7-ca47237c02a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350831755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3350831755
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3256887276
Short name T44
Test name
Test status
Simulation time 362874646661 ps
CPU time 170.11 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:36:21 PM PDT 24
Peak memory 217984 kb
Host smart-2cc70ea7-bcdb-4bad-a7f9-49fbc654a82b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256887276 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3256887276
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2838458865
Short name T151
Test name
Test status
Simulation time 325371966511 ps
CPU time 654.13 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:43:54 PM PDT 24
Peak memory 201464 kb
Host smart-15d7427c-92c0-4bbd-a92f-bdc783536559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838458865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2838458865
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3074714906
Short name T233
Test name
Test status
Simulation time 332645206816 ps
CPU time 164.2 seconds
Started Aug 06 07:35:24 PM PDT 24
Finished Aug 06 07:38:08 PM PDT 24
Peak memory 201496 kb
Host smart-5f571121-1149-48b9-8e14-3f44b72e683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074714906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3074714906
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3815572029
Short name T69
Test name
Test status
Simulation time 697770851 ps
CPU time 2.64 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 209864 kb
Host smart-709878a4-60ec-4616-afba-a2197785a9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815572029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3815572029
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1937826992
Short name T176
Test name
Test status
Simulation time 507545881285 ps
CPU time 312.37 seconds
Started Aug 06 07:33:20 PM PDT 24
Finished Aug 06 07:38:33 PM PDT 24
Peak memory 201388 kb
Host smart-40923afc-e85a-4357-a019-9a061eb13aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937826992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1937826992
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3454838283
Short name T141
Test name
Test status
Simulation time 496063882109 ps
CPU time 1082.61 seconds
Started Aug 06 07:32:31 PM PDT 24
Finished Aug 06 07:50:34 PM PDT 24
Peak memory 200584 kb
Host smart-6d9cd0c9-f2b5-4c48-9f6e-3d9187f50dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454838283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3454838283
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3447073124
Short name T66
Test name
Test status
Simulation time 3924673003 ps
CPU time 9.68 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:22 PM PDT 24
Peak memory 217196 kb
Host smart-6b8bd6c2-5414-4d6e-9869-27e51920f8f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447073124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3447073124
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2755372296
Short name T227
Test name
Test status
Simulation time 691384467481 ps
CPU time 825.51 seconds
Started Aug 06 07:35:21 PM PDT 24
Finished Aug 06 07:49:07 PM PDT 24
Peak memory 201452 kb
Host smart-ee43cef7-84c6-4a42-98eb-c7904541ffa3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755372296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2755372296
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3393751813
Short name T202
Test name
Test status
Simulation time 335388249669 ps
CPU time 162.86 seconds
Started Aug 06 07:39:48 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 201416 kb
Host smart-3dd25590-c8d1-4353-b9d4-b5a0c7647afd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393751813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3393751813
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3782828985
Short name T237
Test name
Test status
Simulation time 491684891175 ps
CPU time 1204.46 seconds
Started Aug 06 07:32:41 PM PDT 24
Finished Aug 06 07:52:46 PM PDT 24
Peak memory 201452 kb
Host smart-24a5d086-f86b-4ea1-bad8-cf971d1d799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782828985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3782828985
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2109783299
Short name T129
Test name
Test status
Simulation time 543515662249 ps
CPU time 1238.14 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:54:09 PM PDT 24
Peak memory 201620 kb
Host smart-985a9f3b-ddbc-400f-9cac-8390116f3d58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109783299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2109783299
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1384165524
Short name T167
Test name
Test status
Simulation time 330090966567 ps
CPU time 199.29 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:35:52 PM PDT 24
Peak memory 201440 kb
Host smart-537b896e-64ac-463d-a839-52e692eaa536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384165524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1384165524
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1000199995
Short name T125
Test name
Test status
Simulation time 358854684197 ps
CPU time 784.16 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:45:24 PM PDT 24
Peak memory 201412 kb
Host smart-0e95ea7c-3ee4-4307-80bf-207816cffa6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000199995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1000199995
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4053867879
Short name T110
Test name
Test status
Simulation time 50247417405 ps
CPU time 32.49 seconds
Started Aug 06 07:31:18 PM PDT 24
Finished Aug 06 07:31:51 PM PDT 24
Peak memory 201548 kb
Host smart-242b59e9-8c6e-43a6-a8a9-98186977c209
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053867879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4053867879
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1239013457
Short name T229
Test name
Test status
Simulation time 506631471793 ps
CPU time 580.37 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 201432 kb
Host smart-f41fc378-d1be-4b49-b264-db2c8072c35d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239013457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1239013457
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.837569729
Short name T17
Test name
Test status
Simulation time 193393734683 ps
CPU time 92.11 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:39:50 PM PDT 24
Peak memory 210172 kb
Host smart-c0c7ce1a-3487-41cf-963d-2ee1ee391be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837569729 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.837569729
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.445097031
Short name T1
Test name
Test status
Simulation time 193910699258 ps
CPU time 260.32 seconds
Started Aug 06 07:35:54 PM PDT 24
Finished Aug 06 07:40:14 PM PDT 24
Peak memory 201432 kb
Host smart-214edf12-8194-49a5-803a-ab1f65a88460
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445097031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.445097031
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3624440144
Short name T293
Test name
Test status
Simulation time 513540297107 ps
CPU time 1159.1 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:51:38 PM PDT 24
Peak memory 201432 kb
Host smart-521b8f23-76d5-4e1c-af2c-a45bd1b5d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624440144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3624440144
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4075358207
Short name T136
Test name
Test status
Simulation time 164593045141 ps
CPU time 391.8 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:39:32 PM PDT 24
Peak memory 201460 kb
Host smart-e3bf8510-9e49-4af2-90e5-22a00e6effda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075358207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4075358207
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.590891988
Short name T281
Test name
Test status
Simulation time 502570378132 ps
CPU time 320.17 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:43:53 PM PDT 24
Peak memory 201452 kb
Host smart-9cf4901a-d08f-4d2d-885d-cc9d0fc70759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590891988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.590891988
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4252613390
Short name T284
Test name
Test status
Simulation time 335692169539 ps
CPU time 154.55 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:39:46 PM PDT 24
Peak memory 201468 kb
Host smart-b1357617-ee41-48cc-a60e-129789f945e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252613390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4252613390
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1048292004
Short name T259
Test name
Test status
Simulation time 496159818196 ps
CPU time 291.92 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:37:16 PM PDT 24
Peak memory 201516 kb
Host smart-010875a4-2e22-482a-9e55-20a57456e2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048292004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1048292004
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2547434740
Short name T65
Test name
Test status
Simulation time 8777168886 ps
CPU time 12.58 seconds
Started Aug 06 07:31:11 PM PDT 24
Finished Aug 06 07:31:24 PM PDT 24
Peak memory 201600 kb
Host smart-e2e4db7d-3263-4855-b0c4-5280977e6bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547434740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2547434740
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.63225387
Short name T192
Test name
Test status
Simulation time 381426793 ps
CPU time 1.15 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:32:20 PM PDT 24
Peak memory 201168 kb
Host smart-d896b462-c033-492e-b792-990f092d9a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63225387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.63225387
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2015714532
Short name T786
Test name
Test status
Simulation time 355726117032 ps
CPU time 491.5 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:40:30 PM PDT 24
Peak memory 201532 kb
Host smart-e7f58463-3ebe-4a24-81a8-64cd620c1e51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015714532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2015714532
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1616186734
Short name T228
Test name
Test status
Simulation time 608700636338 ps
CPU time 1459.9 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 08:01:50 PM PDT 24
Peak memory 201420 kb
Host smart-d061d3bd-c21a-4b0d-91d4-11c9dd90250b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616186734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1616186734
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3290468068
Short name T300
Test name
Test status
Simulation time 515867622950 ps
CPU time 306.47 seconds
Started Aug 06 07:32:27 PM PDT 24
Finished Aug 06 07:37:34 PM PDT 24
Peak memory 201492 kb
Host smart-425e3ad3-0469-4de9-ad77-2ab19e00902b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290468068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3290468068
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.389192071
Short name T295
Test name
Test status
Simulation time 344886462791 ps
CPU time 97.39 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:34:39 PM PDT 24
Peak memory 209924 kb
Host smart-396bbb00-74f9-487b-afb7-0f7c985d2fa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389192071 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.389192071
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4205470932
Short name T134
Test name
Test status
Simulation time 499239304456 ps
CPU time 269.2 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:37:32 PM PDT 24
Peak memory 201420 kb
Host smart-fe573cd4-90fa-4754-a87e-948a2657e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205470932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4205470932
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2411590063
Short name T217
Test name
Test status
Simulation time 359849827616 ps
CPU time 547.62 seconds
Started Aug 06 07:38:48 PM PDT 24
Finished Aug 06 07:47:56 PM PDT 24
Peak memory 201820 kb
Host smart-d39a3701-bf1b-48db-9248-91e3ec546783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411590063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2411590063
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4165421338
Short name T56
Test name
Test status
Simulation time 2475959169 ps
CPU time 10.37 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:32:07 PM PDT 24
Peak memory 201468 kb
Host smart-4cad2d4d-e45c-499e-a5a3-07730a19c391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165421338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4165421338
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2188457314
Short name T149
Test name
Test status
Simulation time 157716409057 ps
CPU time 184.28 seconds
Started Aug 06 07:34:48 PM PDT 24
Finished Aug 06 07:37:52 PM PDT 24
Peak memory 201440 kb
Host smart-ec009172-0d67-421d-8ab0-b002442f280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188457314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2188457314
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.669745478
Short name T320
Test name
Test status
Simulation time 528267896193 ps
CPU time 1125.26 seconds
Started Aug 06 07:37:47 PM PDT 24
Finished Aug 06 07:56:32 PM PDT 24
Peak memory 201436 kb
Host smart-d2eebf30-7855-4da7-8355-a0d080a4a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669745478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.669745478
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.540649271
Short name T244
Test name
Test status
Simulation time 353919142843 ps
CPU time 829.02 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 201428 kb
Host smart-8ecbcf0d-2b0b-41ec-81da-e73955027abe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540649271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.540649271
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3964123685
Short name T128
Test name
Test status
Simulation time 325023360700 ps
CPU time 769.18 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:45:08 PM PDT 24
Peak memory 201436 kb
Host smart-43f07f0a-a784-4211-ba5d-f6b4f3417b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964123685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3964123685
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2014290861
Short name T252
Test name
Test status
Simulation time 334836408253 ps
CPU time 199.73 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:37:25 PM PDT 24
Peak memory 201384 kb
Host smart-21265379-80be-4a80-ad7d-b929dc5dd1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014290861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2014290861
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.194585153
Short name T278
Test name
Test status
Simulation time 342010499211 ps
CPU time 733.66 seconds
Started Aug 06 07:34:48 PM PDT 24
Finished Aug 06 07:47:01 PM PDT 24
Peak memory 201408 kb
Host smart-de54d1dd-2ac0-4077-90bd-3f37c2a8eb09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194585153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.194585153
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1544676271
Short name T282
Test name
Test status
Simulation time 165854697367 ps
CPU time 369.76 seconds
Started Aug 06 07:38:02 PM PDT 24
Finished Aug 06 07:44:12 PM PDT 24
Peak memory 201424 kb
Host smart-0fa9a0fe-3314-4aaf-bafe-1d929102fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544676271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1544676271
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3308775691
Short name T240
Test name
Test status
Simulation time 179860660757 ps
CPU time 343.3 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:38:46 PM PDT 24
Peak memory 210224 kb
Host smart-65b97e8e-aaa5-4328-97cf-ce9452aa88d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308775691 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3308775691
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3254547874
Short name T250
Test name
Test status
Simulation time 487747536743 ps
CPU time 574.59 seconds
Started Aug 06 07:33:18 PM PDT 24
Finished Aug 06 07:42:52 PM PDT 24
Peak memory 201440 kb
Host smart-6619cb31-09ed-4056-88ee-cd696a60ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254547874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3254547874
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3216839924
Short name T310
Test name
Test status
Simulation time 493490963301 ps
CPU time 638.69 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 201412 kb
Host smart-a55624b8-84ca-4c12-a4f3-e82adad4a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216839924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3216839924
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1400810237
Short name T308
Test name
Test status
Simulation time 351678128661 ps
CPU time 757.89 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:46:22 PM PDT 24
Peak memory 201440 kb
Host smart-d8a6ab4c-9120-4bd6-97fc-d55477be726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400810237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1400810237
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1310878256
Short name T323
Test name
Test status
Simulation time 551673375082 ps
CPU time 1276.94 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:59:50 PM PDT 24
Peak memory 201420 kb
Host smart-c4afbe63-a08e-4621-bf8c-2de44ba1b406
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310878256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1310878256
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1899277224
Short name T267
Test name
Test status
Simulation time 392262039015 ps
CPU time 218.79 seconds
Started Aug 06 07:33:03 PM PDT 24
Finished Aug 06 07:36:42 PM PDT 24
Peak memory 201428 kb
Host smart-6cd0237f-72b8-4b7e-b068-cbe5a6e96b1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899277224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1899277224
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3869971595
Short name T212
Test name
Test status
Simulation time 85177211353 ps
CPU time 190.7 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:38:49 PM PDT 24
Peak memory 210172 kb
Host smart-a1e23270-31ec-43f4-889d-c390ab6e26a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869971595 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3869971595
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.155310844
Short name T223
Test name
Test status
Simulation time 67273265484 ps
CPU time 136.02 seconds
Started Aug 06 07:36:15 PM PDT 24
Finished Aug 06 07:38:31 PM PDT 24
Peak memory 210252 kb
Host smart-80a80eea-cf86-492c-b360-f6dc964312b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155310844 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.155310844
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.4040243810
Short name T305
Test name
Test status
Simulation time 338988779084 ps
CPU time 757.21 seconds
Started Aug 06 07:39:45 PM PDT 24
Finished Aug 06 07:52:22 PM PDT 24
Peak memory 201464 kb
Host smart-6bac34ee-6f74-4290-8425-ccb83ad33029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040243810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.4040243810
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1176773789
Short name T351
Test name
Test status
Simulation time 327051517341 ps
CPU time 186.77 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:35:31 PM PDT 24
Peak memory 201448 kb
Host smart-acbb660e-9974-4278-b649-e1b8a0d7d3fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176773789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1176773789
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.69990553
Short name T150
Test name
Test status
Simulation time 488473549256 ps
CPU time 610.46 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:43:09 PM PDT 24
Peak memory 201436 kb
Host smart-269f073a-e1d0-471b-9a81-9596443f190b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69990553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt
_fixed.69990553
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3100674914
Short name T41
Test name
Test status
Simulation time 76054532601 ps
CPU time 129.41 seconds
Started Aug 06 07:37:13 PM PDT 24
Finished Aug 06 07:39:23 PM PDT 24
Peak memory 209796 kb
Host smart-bcc45cd9-ab30-4380-8fa8-e87b07af2cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100674914 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3100674914
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1246238883
Short name T279
Test name
Test status
Simulation time 564951776520 ps
CPU time 343.75 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:45:31 PM PDT 24
Peak memory 201452 kb
Host smart-d45fb304-740d-40a8-b7c9-3db961a51f16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246238883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1246238883
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.561849413
Short name T239
Test name
Test status
Simulation time 532731638299 ps
CPU time 1215.16 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 08:00:25 PM PDT 24
Peak memory 201792 kb
Host smart-14c36f25-508a-4b24-9314-9f40d7fbcecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561849413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
561849413
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.742550395
Short name T222
Test name
Test status
Simulation time 332240874291 ps
CPU time 118.78 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:34:42 PM PDT 24
Peak memory 201412 kb
Host smart-96fc2a48-7982-4560-b067-2129e2c66b3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742550395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.742550395
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2676410083
Short name T268
Test name
Test status
Simulation time 330439393735 ps
CPU time 733.08 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:45:14 PM PDT 24
Peak memory 201436 kb
Host smart-5e3f3db7-5e07-4677-8932-a18afbd16e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676410083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2676410083
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.273287802
Short name T72
Test name
Test status
Simulation time 646012196 ps
CPU time 1.82 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 201684 kb
Host smart-60d2ef07-3996-4187-9938-4d641158d743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273287802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.273287802
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2832039694
Short name T257
Test name
Test status
Simulation time 324931853294 ps
CPU time 178.69 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:35:58 PM PDT 24
Peak memory 201460 kb
Host smart-b6f7d181-b21a-47b9-bdfb-cc6af68099d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832039694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2832039694
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1411639243
Short name T168
Test name
Test status
Simulation time 542288043330 ps
CPU time 342.95 seconds
Started Aug 06 07:33:04 PM PDT 24
Finished Aug 06 07:38:47 PM PDT 24
Peak memory 201460 kb
Host smart-4da49f11-23ba-48f1-ad2a-8edce0a719a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411639243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1411639243
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.584329284
Short name T342
Test name
Test status
Simulation time 331146566580 ps
CPU time 414.8 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:44:06 PM PDT 24
Peak memory 201424 kb
Host smart-4989055b-90b3-4a0f-9dc7-2ef8abae9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584329284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.584329284
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1550559025
Short name T236
Test name
Test status
Simulation time 341538687977 ps
CPU time 213.14 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:35:56 PM PDT 24
Peak memory 201324 kb
Host smart-0e768b58-63c0-4c41-8bc6-1586446d6b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550559025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1550559025
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2492532681
Short name T19
Test name
Test status
Simulation time 24226098392 ps
CPU time 53.1 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:40:40 PM PDT 24
Peak memory 210120 kb
Host smart-6dd33265-2fa2-473b-a0c4-449577b6d78d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492532681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2492532681
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3398457813
Short name T266
Test name
Test status
Simulation time 562641508029 ps
CPU time 322.84 seconds
Started Aug 06 07:39:48 PM PDT 24
Finished Aug 06 07:45:11 PM PDT 24
Peak memory 201464 kb
Host smart-e108e5aa-7e15-465f-98ab-08b53250f7b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398457813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3398457813
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3426336645
Short name T14
Test name
Test status
Simulation time 166357555064 ps
CPU time 101.46 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:33:59 PM PDT 24
Peak memory 201428 kb
Host smart-0c5ea2e9-ba0f-448d-9a5e-f095785b0f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426336645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3426336645
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3467289162
Short name T248
Test name
Test status
Simulation time 398981320462 ps
CPU time 441.24 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:40:23 PM PDT 24
Peak memory 201428 kb
Host smart-e2036975-0c2b-490d-bf72-3566e42b9fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467289162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3467289162
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.733530586
Short name T247
Test name
Test status
Simulation time 329310945048 ps
CPU time 673.31 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:44:34 PM PDT 24
Peak memory 201484 kb
Host smart-eebe96e3-de44-40ac-9ab2-8121a40fdbc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733530586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.733530586
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3150459093
Short name T210
Test name
Test status
Simulation time 1333137569479 ps
CPU time 348 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:39:18 PM PDT 24
Peak memory 210144 kb
Host smart-e381aaa8-e5a7-4e9a-828f-87233c735594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150459093 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3150459093
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.22842252
Short name T286
Test name
Test status
Simulation time 334955499273 ps
CPU time 78.53 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:35:25 PM PDT 24
Peak memory 201412 kb
Host smart-688265cc-6ec0-45c6-ad37-052e9d806ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22842252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.22842252
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1735165214
Short name T269
Test name
Test status
Simulation time 166060808369 ps
CPU time 356.24 seconds
Started Aug 06 07:34:34 PM PDT 24
Finished Aug 06 07:40:31 PM PDT 24
Peak memory 201488 kb
Host smart-dd828782-4f0b-4bd0-9486-8ee7ca1b52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735165214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1735165214
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4209449681
Short name T215
Test name
Test status
Simulation time 121322863016 ps
CPU time 390.37 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 201828 kb
Host smart-7f66c50f-0104-4b4b-9667-9b3f0a2877f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209449681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4209449681
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.109132544
Short name T29
Test name
Test status
Simulation time 397701327022 ps
CPU time 277.77 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:36:50 PM PDT 24
Peak memory 201472 kb
Host smart-64b29794-c7a6-4946-a8a6-1d7388a86c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109132544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.109132544
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3444193147
Short name T213
Test name
Test status
Simulation time 73929241266 ps
CPU time 277.99 seconds
Started Aug 06 07:35:57 PM PDT 24
Finished Aug 06 07:40:35 PM PDT 24
Peak memory 201760 kb
Host smart-b77908d3-35e0-4107-948d-5361c1c6a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444193147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3444193147
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3091899998
Short name T51
Test name
Test status
Simulation time 119711917431 ps
CPU time 477.27 seconds
Started Aug 06 07:32:10 PM PDT 24
Finished Aug 06 07:40:08 PM PDT 24
Peak memory 201844 kb
Host smart-eb014c68-a383-49a2-a296-fce11d7eb524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091899998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3091899998
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3422158625
Short name T133
Test name
Test status
Simulation time 334581618128 ps
CPU time 828.09 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:46:46 PM PDT 24
Peak memory 201420 kb
Host smart-5d529417-957b-48b6-91e6-c65d2d835b5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422158625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3422158625
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.878509173
Short name T328
Test name
Test status
Simulation time 327222331695 ps
CPU time 715.73 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:44:57 PM PDT 24
Peak memory 201500 kb
Host smart-3d7ac757-3bea-4123-aff7-8e6963d315f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878509173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.878509173
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2832507006
Short name T225
Test name
Test status
Simulation time 328757991510 ps
CPU time 641.7 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:44:26 PM PDT 24
Peak memory 201424 kb
Host smart-616d39ef-5e44-4b59-b423-0309f261f07b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832507006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2832507006
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.354801760
Short name T335
Test name
Test status
Simulation time 59697308201 ps
CPU time 62.88 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:36:44 PM PDT 24
Peak memory 210056 kb
Host smart-cdcbf0ed-f437-47f9-afb1-9e5c62f0a78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354801760 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.354801760
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.737855603
Short name T324
Test name
Test status
Simulation time 385528367622 ps
CPU time 460.59 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:40:00 PM PDT 24
Peak memory 201396 kb
Host smart-0ad0c6a1-ec96-4d95-b05c-423d52d1b6d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737855603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.737855603
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3848471654
Short name T333
Test name
Test status
Simulation time 178096469209 ps
CPU time 92.87 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:38:26 PM PDT 24
Peak memory 201480 kb
Host smart-723b4feb-87e8-4d5e-8894-79a7b2c21320
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848471654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3848471654
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.63281945
Short name T171
Test name
Test status
Simulation time 584291745247 ps
CPU time 648.71 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 201460 kb
Host smart-58d3898a-c393-40b5-8a59-9eaf0a8acb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63281945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.63281945
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.72847772
Short name T291
Test name
Test status
Simulation time 381451668045 ps
CPU time 831.58 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 201384 kb
Host smart-ecc8b9ed-9286-4380-9f5a-22d6557f1f1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72847772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gatin
g.72847772
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4234265774
Short name T356
Test name
Test status
Simulation time 130246125928 ps
CPU time 696.14 seconds
Started Aug 06 07:40:07 PM PDT 24
Finished Aug 06 07:51:43 PM PDT 24
Peak memory 201800 kb
Host smart-e809e4b8-9487-4dd1-b8d0-0ef7a965ad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234265774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4234265774
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.347682575
Short name T216
Test name
Test status
Simulation time 121123143370 ps
CPU time 435.52 seconds
Started Aug 06 07:32:44 PM PDT 24
Finished Aug 06 07:40:00 PM PDT 24
Peak memory 201884 kb
Host smart-260723fa-a819-49da-9279-a2342a5f8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347682575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.347682575
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2878255600
Short name T833
Test name
Test status
Simulation time 640726553 ps
CPU time 2.79 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201484 kb
Host smart-83e88d07-5722-4e53-88f8-fa42519f9bfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878255600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2878255600
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3044448099
Short name T912
Test name
Test status
Simulation time 1057542303 ps
CPU time 1.31 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201348 kb
Host smart-ed4b801e-f799-4af1-bd83-4e4e908d5bf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044448099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3044448099
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4231899999
Short name T804
Test name
Test status
Simulation time 502735199 ps
CPU time 1.1 seconds
Started Aug 06 07:31:12 PM PDT 24
Finished Aug 06 07:31:13 PM PDT 24
Peak memory 201676 kb
Host smart-f0d330cd-dabb-4914-9f97-e543aa6aef7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231899999 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4231899999
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4164422769
Short name T107
Test name
Test status
Simulation time 347334662 ps
CPU time 1.48 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:16 PM PDT 24
Peak memory 201332 kb
Host smart-b74a2314-4910-4f9a-858c-3719f05aa2a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164422769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4164422769
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3967276067
Short name T856
Test name
Test status
Simulation time 301914335 ps
CPU time 1.4 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201360 kb
Host smart-3b61b7a5-7692-45e6-bac5-397dae54c5b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967276067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3967276067
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1049420946
Short name T874
Test name
Test status
Simulation time 4018609653 ps
CPU time 9.62 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:27 PM PDT 24
Peak memory 201584 kb
Host smart-794054cc-032d-4fd1-a58f-1f1a7e4ceb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049420946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1049420946
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2455768252
Short name T843
Test name
Test status
Simulation time 1260719608 ps
CPU time 2.62 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:12 PM PDT 24
Peak memory 210788 kb
Host smart-6ba3a622-bca4-46cd-9d4a-fbfa5c0be17a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455768252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2455768252
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3873296646
Short name T104
Test name
Test status
Simulation time 501486314 ps
CPU time 1.94 seconds
Started Aug 06 07:31:11 PM PDT 24
Finished Aug 06 07:31:13 PM PDT 24
Peak memory 201512 kb
Host smart-96db2e06-1923-43bb-87ab-6d5b859e6b75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873296646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3873296646
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3916634490
Short name T112
Test name
Test status
Simulation time 42870988485 ps
CPU time 95.96 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:32:45 PM PDT 24
Peak memory 201576 kb
Host smart-cbdd79bd-c7c1-48b3-8d4f-937f0bda3d7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916634490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3916634490
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2374860218
Short name T830
Test name
Test status
Simulation time 1294896667 ps
CPU time 1.2 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 201364 kb
Host smart-48d1a94a-e992-4818-80e9-ce86cd3f667d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374860218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2374860218
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.453310075
Short name T87
Test name
Test status
Simulation time 416853242 ps
CPU time 1.79 seconds
Started Aug 06 07:31:18 PM PDT 24
Finished Aug 06 07:31:20 PM PDT 24
Peak memory 201464 kb
Host smart-bd5c6840-19c9-419a-a1c0-75372d26a689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453310075 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.453310075
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1653565145
Short name T802
Test name
Test status
Simulation time 405192300 ps
CPU time 1.73 seconds
Started Aug 06 07:31:12 PM PDT 24
Finished Aug 06 07:31:13 PM PDT 24
Peak memory 201328 kb
Host smart-102134a9-d581-45b6-9cd2-fee8b53787a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653565145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1653565145
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1157563846
Short name T848
Test name
Test status
Simulation time 409460365 ps
CPU time 0.83 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 201364 kb
Host smart-eb6ae665-e691-4ea2-a41b-9e5731abf2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157563846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1157563846
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.956384108
Short name T904
Test name
Test status
Simulation time 5254276542 ps
CPU time 2.39 seconds
Started Aug 06 07:31:12 PM PDT 24
Finished Aug 06 07:31:14 PM PDT 24
Peak memory 201752 kb
Host smart-1a32d2d9-75fd-469b-80f1-f27168100865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956384108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.956384108
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4054005158
Short name T61
Test name
Test status
Simulation time 7751534371 ps
CPU time 19.23 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:29 PM PDT 24
Peak memory 201616 kb
Host smart-1ca8caa2-0b93-4bef-bd3d-295adde80fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054005158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.4054005158
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4002900596
Short name T896
Test name
Test status
Simulation time 741537422 ps
CPU time 1.04 seconds
Started Aug 06 07:31:53 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201396 kb
Host smart-73d4db8b-0de9-4dae-afbe-d16874f86ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002900596 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4002900596
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2879356956
Short name T121
Test name
Test status
Simulation time 411854723 ps
CPU time 1.16 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201324 kb
Host smart-992b55eb-5ecf-43a2-84ad-993168a364e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879356956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2879356956
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3224504767
Short name T822
Test name
Test status
Simulation time 325530535 ps
CPU time 0.81 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201348 kb
Host smart-dbf463fa-bfd1-47e8-8a75-69b196958d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224504767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3224504767
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3895536132
Short name T854
Test name
Test status
Simulation time 4411090626 ps
CPU time 10.99 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:32:06 PM PDT 24
Peak memory 201560 kb
Host smart-5af98111-2175-42ef-9abd-a57b0e820d40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895536132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3895536132
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1349499103
Short name T877
Test name
Test status
Simulation time 2017111704 ps
CPU time 2.69 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 218064 kb
Host smart-26b10d11-dccd-4f37-89b1-045bc3c3178d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349499103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1349499103
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3591007212
Short name T886
Test name
Test status
Simulation time 4370189337 ps
CPU time 10.66 seconds
Started Aug 06 07:31:52 PM PDT 24
Finished Aug 06 07:32:03 PM PDT 24
Peak memory 201660 kb
Host smart-36d33f98-ed81-44a2-9ea5-2017fec42acf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591007212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3591007212
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1471561494
Short name T883
Test name
Test status
Simulation time 429691800 ps
CPU time 1.82 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201508 kb
Host smart-0369c83d-1451-4d43-a783-80e4cc3f3bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471561494 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1471561494
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2408475795
Short name T915
Test name
Test status
Simulation time 515470165 ps
CPU time 1.25 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201364 kb
Host smart-8042a70d-3d48-48bc-9338-a3c72ff20389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408475795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2408475795
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3804597340
Short name T817
Test name
Test status
Simulation time 416278810 ps
CPU time 1.1 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201360 kb
Host smart-e8ff0d05-85e9-45cc-87a8-52ccbf959d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804597340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3804597340
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2146319460
Short name T890
Test name
Test status
Simulation time 471112561 ps
CPU time 2.66 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 217952 kb
Host smart-001e76ca-573e-4d86-a55a-4738a1d5836b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146319460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2146319460
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2446420227
Short name T836
Test name
Test status
Simulation time 3932304371 ps
CPU time 3.8 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201616 kb
Host smart-6e288868-cdbb-40db-b49d-f511ce906967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446420227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2446420227
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1567868173
Short name T907
Test name
Test status
Simulation time 488630241 ps
CPU time 1.31 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201500 kb
Host smart-eb47c059-15c6-4701-b10b-a7ca474d75b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567868173 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1567868173
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2383736352
Short name T105
Test name
Test status
Simulation time 545644255 ps
CPU time 1.55 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201308 kb
Host smart-39069317-b9d8-46a1-a8e5-d71fee78d9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383736352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2383736352
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3011237565
Short name T872
Test name
Test status
Simulation time 298735535 ps
CPU time 1.29 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201532 kb
Host smart-84dc59dd-f41d-4b65-88db-d9d627461578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011237565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3011237565
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1760322750
Short name T880
Test name
Test status
Simulation time 4356660632 ps
CPU time 2.4 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201612 kb
Host smart-7b177558-b3af-49cd-a40b-6e9ef4957989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760322750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1760322750
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.746474710
Short name T74
Test name
Test status
Simulation time 619429010 ps
CPU time 1.59 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201608 kb
Host smart-f33bd58f-f006-4606-a964-f2255d179dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746474710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.746474710
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1524626594
Short name T857
Test name
Test status
Simulation time 8425836776 ps
CPU time 22.07 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:32:16 PM PDT 24
Peak memory 201624 kb
Host smart-84e2f579-3340-46f1-b4ab-8645ea3dcd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524626594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1524626594
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.828270752
Short name T859
Test name
Test status
Simulation time 518327970 ps
CPU time 1.24 seconds
Started Aug 06 07:31:53 PM PDT 24
Finished Aug 06 07:31:54 PM PDT 24
Peak memory 201496 kb
Host smart-8228e0cb-19d1-4be9-a302-5f58fcc60afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828270752 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.828270752
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1930292567
Short name T103
Test name
Test status
Simulation time 520531552 ps
CPU time 1.13 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201340 kb
Host smart-3328e46a-19a8-4ec9-9e03-2f3c614a09e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930292567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1930292567
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2906322243
Short name T919
Test name
Test status
Simulation time 606638772 ps
CPU time 0.7 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201380 kb
Host smart-204c7fee-7242-4a4f-9b05-44298b5de4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906322243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2906322243
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2576589223
Short name T805
Test name
Test status
Simulation time 2383439622 ps
CPU time 6.21 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201392 kb
Host smart-f14aee38-53a4-4f97-9097-c6959b839219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576589223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2576589223
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2655414804
Short name T903
Test name
Test status
Simulation time 759649962 ps
CPU time 2.51 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201640 kb
Host smart-07ca319c-c9b6-42c9-ad42-5109a4cef4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655414804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2655414804
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2552585052
Short name T887
Test name
Test status
Simulation time 4835927011 ps
CPU time 4.36 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201596 kb
Host smart-c3d37be4-679f-4372-813d-936a46d3fe4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552585052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2552585052
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1079047281
Short name T894
Test name
Test status
Simulation time 383399067 ps
CPU time 1.78 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201480 kb
Host smart-a6d5cdf7-b86f-4c0a-9527-961eca6dac27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079047281 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1079047281
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.351884231
Short name T870
Test name
Test status
Simulation time 590633317 ps
CPU time 1.41 seconds
Started Aug 06 07:31:53 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201344 kb
Host smart-4523eecd-a607-45b4-8383-1b222aa88583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351884231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.351884231
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3739091539
Short name T851
Test name
Test status
Simulation time 485936693 ps
CPU time 1.86 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201240 kb
Host smart-9d4c022e-4ba6-49d8-98e4-c36ab26f3f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739091539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3739091539
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3118610869
Short name T58
Test name
Test status
Simulation time 4935162571 ps
CPU time 3.06 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201616 kb
Host smart-8932e7cb-e98e-4427-a40e-dda438825a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118610869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3118610869
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2943730240
Short name T908
Test name
Test status
Simulation time 473926866 ps
CPU time 1.72 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201620 kb
Host smart-20a2aef4-77b2-49ff-bdb6-248c8384a346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943730240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2943730240
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3446808652
Short name T831
Test name
Test status
Simulation time 4474001638 ps
CPU time 4.13 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201676 kb
Host smart-5ef662d5-bfda-4bb9-b7fc-ab36fd095459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446808652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3446808652
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3182328342
Short name T63
Test name
Test status
Simulation time 522807823 ps
CPU time 1.33 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201344 kb
Host smart-0b42c0dd-af97-40fe-ad8d-de4b3fbc3fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182328342 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3182328342
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1512926661
Short name T899
Test name
Test status
Simulation time 483493645 ps
CPU time 0.95 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201340 kb
Host smart-62e9be8e-e05c-41e5-a6f7-31ab47fd3895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512926661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1512926661
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.670501969
Short name T824
Test name
Test status
Simulation time 571777712 ps
CPU time 0.77 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201400 kb
Host smart-b694405a-6d11-4691-811f-f94008a6ad65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670501969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.670501969
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4476292
Short name T855
Test name
Test status
Simulation time 2002658123 ps
CPU time 2.92 seconds
Started Aug 06 07:31:58 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201200 kb
Host smart-7d4b77b4-32c8-4563-8e89-21c411e8fb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4476292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctr
l_same_csr_outstanding.4476292
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1226658272
Short name T841
Test name
Test status
Simulation time 364396135 ps
CPU time 1.97 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201684 kb
Host smart-23be0a07-838e-4276-8629-4178524b4fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226658272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1226658272
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3868650225
Short name T918
Test name
Test status
Simulation time 8451473756 ps
CPU time 6.9 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201644 kb
Host smart-338d8145-d0c3-4ebd-9eca-53b69a401cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868650225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3868650225
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2091952253
Short name T827
Test name
Test status
Simulation time 473409580 ps
CPU time 1.85 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201464 kb
Host smart-bdbc65f9-4866-4cd4-8650-507c45326fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091952253 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2091952253
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2131908431
Short name T916
Test name
Test status
Simulation time 577830376 ps
CPU time 1.14 seconds
Started Aug 06 07:31:58 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201360 kb
Host smart-12586f78-0d49-4aae-9bc4-627381604ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131908431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2131908431
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1724188913
Short name T849
Test name
Test status
Simulation time 508091094 ps
CPU time 1.78 seconds
Started Aug 06 07:32:01 PM PDT 24
Finished Aug 06 07:32:03 PM PDT 24
Peak memory 201380 kb
Host smart-9a620c33-530e-4e9b-8bfd-a7df45f11535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724188913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1724188913
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3807917563
Short name T885
Test name
Test status
Simulation time 4280195717 ps
CPU time 4.89 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201620 kb
Host smart-2424af22-dcce-4bb8-8658-c071e3bd8a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807917563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3807917563
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3541438363
Short name T909
Test name
Test status
Simulation time 332961487 ps
CPU time 2.16 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201692 kb
Host smart-f1e01d1c-d6eb-42e9-8122-ad54c642dd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541438363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3541438363
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1381732986
Short name T807
Test name
Test status
Simulation time 4099383264 ps
CPU time 11.02 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:32:06 PM PDT 24
Peak memory 201672 kb
Host smart-4d190d5b-616d-49ce-998f-8f4369fe10ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381732986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1381732986
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3961227316
Short name T876
Test name
Test status
Simulation time 475826809 ps
CPU time 2.11 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201492 kb
Host smart-c528069e-dcc8-43b8-8e0f-c60f58791ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961227316 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3961227316
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.779823667
Short name T113
Test name
Test status
Simulation time 324577358 ps
CPU time 0.89 seconds
Started Aug 06 07:31:58 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201300 kb
Host smart-513a0b8c-7cbd-4294-ae24-625764bdaa67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779823667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.779823667
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2212944765
Short name T797
Test name
Test status
Simulation time 469180387 ps
CPU time 0.95 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201192 kb
Host smart-c2d8f534-52ec-45c3-be6a-142854069354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212944765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2212944765
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.827716221
Short name T812
Test name
Test status
Simulation time 4796066763 ps
CPU time 3.48 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201616 kb
Host smart-fe0ae512-3ac6-409f-aa29-63c57b3b92bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827716221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.827716221
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2146595427
Short name T70
Test name
Test status
Simulation time 920752582 ps
CPU time 2.41 seconds
Started Aug 06 07:31:58 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 217476 kb
Host smart-6a37e5e0-71cc-44ce-abae-78cb7e262f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146595427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2146595427
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2518950412
Short name T901
Test name
Test status
Simulation time 4275615073 ps
CPU time 3.89 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201624 kb
Host smart-429d95b6-0acc-446e-8b01-191978c4eba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518950412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2518950412
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1040050022
Short name T832
Test name
Test status
Simulation time 549423018 ps
CPU time 1.18 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201464 kb
Host smart-3faae733-7afd-4e7e-afda-a12624cdac24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040050022 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1040050022
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2015867591
Short name T109
Test name
Test status
Simulation time 320792926 ps
CPU time 1.6 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201300 kb
Host smart-76453bea-cdd8-4736-b06f-b7012c2f1194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015867591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2015867591
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.346105552
Short name T893
Test name
Test status
Simulation time 555789143 ps
CPU time 0.79 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201300 kb
Host smart-9c1b341d-eb34-4855-a664-ae241a3dc0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346105552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.346105552
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.200188391
Short name T862
Test name
Test status
Simulation time 2003909908 ps
CPU time 1.73 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201384 kb
Host smart-548453f3-6d16-482b-b026-64d60d095fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200188391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.200188391
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3045052839
Short name T873
Test name
Test status
Simulation time 570503905 ps
CPU time 1.76 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201720 kb
Host smart-263fa175-ce3c-4da5-a381-e40c8641999f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045052839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3045052839
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.283360077
Short name T892
Test name
Test status
Simulation time 4552085990 ps
CPU time 3.86 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201636 kb
Host smart-0dc58e27-517f-4ce2-bc09-f2dd5b70260c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283360077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.283360077
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2045190340
Short name T869
Test name
Test status
Simulation time 436264833 ps
CPU time 1.1 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201460 kb
Host smart-598e3edf-2572-4757-b585-1865fb187177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045190340 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2045190340
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.619348423
Short name T118
Test name
Test status
Simulation time 361553725 ps
CPU time 1.48 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201224 kb
Host smart-fff13626-0ea7-44ae-8668-d2fe5adf81f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619348423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.619348423
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2326534841
Short name T847
Test name
Test status
Simulation time 455069154 ps
CPU time 1.16 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201380 kb
Host smart-8e948520-5704-4130-8509-e20af41e5bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326534841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2326534841
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2721557501
Short name T809
Test name
Test status
Simulation time 2046119084 ps
CPU time 3.93 seconds
Started Aug 06 07:31:58 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201328 kb
Host smart-5ce6d3ba-bc74-4f76-9072-ff20d373d1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721557501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2721557501
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3040072834
Short name T863
Test name
Test status
Simulation time 321060854 ps
CPU time 2.32 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201616 kb
Host smart-803609c1-82f4-49c0-b1a0-3c0f62be6756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040072834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3040072834
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2861848909
Short name T62
Test name
Test status
Simulation time 5007530671 ps
CPU time 4.45 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201644 kb
Host smart-1701a104-4c19-4f94-88a4-f5de29841d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861848909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2861848909
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.248780851
Short name T108
Test name
Test status
Simulation time 1213219730 ps
CPU time 2.91 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:38 PM PDT 24
Peak memory 201552 kb
Host smart-197e1ba0-8546-447d-b7e4-f0170a478f3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248780851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.248780851
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2333017853
Short name T116
Test name
Test status
Simulation time 28958099911 ps
CPU time 22.27 seconds
Started Aug 06 07:31:13 PM PDT 24
Finished Aug 06 07:31:36 PM PDT 24
Peak memory 201796 kb
Host smart-108bbcd3-9956-42ea-9fb3-abb45d7081e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333017853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2333017853
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.942576851
Short name T837
Test name
Test status
Simulation time 808401517 ps
CPU time 2.41 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:12 PM PDT 24
Peak memory 201300 kb
Host smart-38c760c1-8331-4548-aafb-65e96807b4a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942576851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.942576851
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.52631139
Short name T825
Test name
Test status
Simulation time 567589579 ps
CPU time 1.49 seconds
Started Aug 06 07:31:37 PM PDT 24
Finished Aug 06 07:31:38 PM PDT 24
Peak memory 209876 kb
Host smart-2ca2f36b-1afa-4de4-b7e2-f35893dca19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52631139 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.52631139
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1981731707
Short name T106
Test name
Test status
Simulation time 335366156 ps
CPU time 0.97 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:10 PM PDT 24
Peak memory 201360 kb
Host smart-2ab4cf36-66f7-40e6-8f9f-9b3761c3eb62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981731707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1981731707
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3610767019
Short name T820
Test name
Test status
Simulation time 295781299 ps
CPU time 1.29 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 201364 kb
Host smart-40593fbb-9ad0-4142-8e23-b1e73acf7258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610767019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3610767019
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2810534742
Short name T864
Test name
Test status
Simulation time 4256939763 ps
CPU time 17.91 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:52 PM PDT 24
Peak memory 201552 kb
Host smart-a36481f8-91b1-4aa0-9bea-5663cf3fbb18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810534742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2810534742
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2446065798
Short name T879
Test name
Test status
Simulation time 8505169228 ps
CPU time 22.46 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:40 PM PDT 24
Peak memory 201652 kb
Host smart-48ee30b7-3c0f-457d-aa25-bf03fa6a739e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446065798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2446065798
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4185286627
Short name T871
Test name
Test status
Simulation time 432874912 ps
CPU time 0.9 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201388 kb
Host smart-ee5053c3-286a-4345-9836-a24b4e41bf58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185286627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4185286627
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1896281740
Short name T868
Test name
Test status
Simulation time 359509617 ps
CPU time 0.85 seconds
Started Aug 06 07:31:57 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201324 kb
Host smart-97360697-025c-4936-9ca2-5d6064d5068a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896281740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1896281740
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1745144705
Short name T826
Test name
Test status
Simulation time 513936948 ps
CPU time 0.95 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201320 kb
Host smart-bb8dbf47-37d4-4599-bfe6-00ec0a430fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745144705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1745144705
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3806833240
Short name T834
Test name
Test status
Simulation time 371327718 ps
CPU time 1.46 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201300 kb
Host smart-1c2caad6-993f-411a-a4cf-fe8bcd38a3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806833240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3806833240
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3886725379
Short name T905
Test name
Test status
Simulation time 493203378 ps
CPU time 0.75 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201376 kb
Host smart-f3ac3806-732a-4184-8fc4-65bbdbfaac99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886725379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3886725379
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2046390095
Short name T803
Test name
Test status
Simulation time 375070198 ps
CPU time 0.83 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201296 kb
Host smart-a86e9ecf-d093-4b14-bbc2-6f3ecfbf58d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046390095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2046390095
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1731710281
Short name T853
Test name
Test status
Simulation time 518476330 ps
CPU time 1.93 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201288 kb
Host smart-1d1d9368-9ba8-4e9c-8ce7-9b787c05a9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731710281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1731710281
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3170479693
Short name T801
Test name
Test status
Simulation time 334406418 ps
CPU time 1.23 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201320 kb
Host smart-cdb92acf-38f3-4f25-b719-6b7b3d027883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170479693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3170479693
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1900150660
Short name T814
Test name
Test status
Simulation time 401128274 ps
CPU time 1.58 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201296 kb
Host smart-e1a92208-7c72-45c5-a27e-8b1c68b21341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900150660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1900150660
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1859324752
Short name T798
Test name
Test status
Simulation time 508179719 ps
CPU time 1.67 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201296 kb
Host smart-49c0ee02-5760-41c4-94e9-478fec68e598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859324752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1859324752
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.66506348
Short name T122
Test name
Test status
Simulation time 1298154854 ps
CPU time 2.45 seconds
Started Aug 06 07:31:36 PM PDT 24
Finished Aug 06 07:31:39 PM PDT 24
Peak memory 201520 kb
Host smart-d114e542-0fb8-44e9-938e-d050803d28ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66506348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasi
ng.66506348
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.41034342
Short name T867
Test name
Test status
Simulation time 53286708365 ps
CPU time 195.97 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:34:51 PM PDT 24
Peak memory 201544 kb
Host smart-24f0bc0c-e1ea-4f2f-978d-eed22a0a3528
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ba
sh.41034342
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3779297752
Short name T835
Test name
Test status
Simulation time 817692051 ps
CPU time 1.67 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:36 PM PDT 24
Peak memory 201328 kb
Host smart-0ecd146e-26e3-4379-b3fa-0348d93abd6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779297752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3779297752
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2057275652
Short name T889
Test name
Test status
Simulation time 548640468 ps
CPU time 1.53 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 209820 kb
Host smart-b511be68-3f14-4525-9efa-dfae825b97b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057275652 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2057275652
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3012719197
Short name T117
Test name
Test status
Simulation time 446332838 ps
CPU time 1.31 seconds
Started Aug 06 07:31:36 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201340 kb
Host smart-1bd806e6-f147-4aad-9b9b-68841f63468a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012719197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3012719197
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2925637254
Short name T842
Test name
Test status
Simulation time 310694437 ps
CPU time 0.87 seconds
Started Aug 06 07:31:32 PM PDT 24
Finished Aug 06 07:31:33 PM PDT 24
Peak memory 201256 kb
Host smart-69305670-bf3a-401a-87bf-a473735c257e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925637254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2925637254
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3122352885
Short name T884
Test name
Test status
Simulation time 4655518860 ps
CPU time 10.96 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:44 PM PDT 24
Peak memory 201556 kb
Host smart-f90813d0-cb25-4a80-8493-b5c9bf8b18f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122352885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3122352885
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.978769860
Short name T845
Test name
Test status
Simulation time 405169528 ps
CPU time 2.9 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201624 kb
Host smart-4694ac46-9f87-4cf2-9e7c-c9c754497fec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978769860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.978769860
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1354228483
Short name T861
Test name
Test status
Simulation time 9193433292 ps
CPU time 12.83 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:48 PM PDT 24
Peak memory 201688 kb
Host smart-87530a4e-f4c0-4abb-8f50-9eb3a6cbbe9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354228483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1354228483
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3278125257
Short name T810
Test name
Test status
Simulation time 400834856 ps
CPU time 0.78 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201304 kb
Host smart-2112e6a1-6c70-4e60-a433-922c91802319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278125257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3278125257
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.438522216
Short name T799
Test name
Test status
Simulation time 360559761 ps
CPU time 0.86 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201352 kb
Host smart-39213f83-cc6d-4169-b791-1d2684425f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438522216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.438522216
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2853720383
Short name T823
Test name
Test status
Simulation time 293183160 ps
CPU time 1.24 seconds
Started Aug 06 07:32:01 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 201388 kb
Host smart-996e0387-5d9a-49e0-ba4f-5d00d068d3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853720383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2853720383
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.466898130
Short name T881
Test name
Test status
Simulation time 550642182 ps
CPU time 0.95 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:32:20 PM PDT 24
Peak memory 201360 kb
Host smart-45a42374-816f-4dc9-ba1d-69a14865673a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466898130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.466898130
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.841772033
Short name T829
Test name
Test status
Simulation time 292819548 ps
CPU time 0.79 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:19 PM PDT 24
Peak memory 201348 kb
Host smart-5acacd7e-68b6-4f2f-aff8-06c5b3e72c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841772033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.841772033
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1138438490
Short name T813
Test name
Test status
Simulation time 336796027 ps
CPU time 0.92 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201328 kb
Host smart-52013b33-16e8-4494-b864-d64e4632feff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138438490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1138438490
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2446286388
Short name T808
Test name
Test status
Simulation time 378989967 ps
CPU time 1.52 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:14 PM PDT 24
Peak memory 201400 kb
Host smart-37624882-d32e-416d-b59d-16fef1d8ff09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446286388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2446286388
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3867199551
Short name T844
Test name
Test status
Simulation time 365746671 ps
CPU time 0.74 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:12 PM PDT 24
Peak memory 201348 kb
Host smart-5c5e5dde-78e3-416f-921f-dcbc6196a60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867199551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3867199551
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3972498776
Short name T917
Test name
Test status
Simulation time 450004007 ps
CPU time 0.73 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201248 kb
Host smart-ed75564e-da91-4e0d-96eb-01358006c29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972498776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3972498776
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4073919856
Short name T821
Test name
Test status
Simulation time 322982654 ps
CPU time 0.81 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201316 kb
Host smart-aa61cc23-f94d-4f87-a557-5b45a65246fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073919856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4073919856
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3019329598
Short name T114
Test name
Test status
Simulation time 1263483726 ps
CPU time 3.41 seconds
Started Aug 06 07:31:32 PM PDT 24
Finished Aug 06 07:31:36 PM PDT 24
Peak memory 201556 kb
Host smart-53a5c6f6-36b0-4123-91af-25c6a861141a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019329598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3019329598
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3300842549
Short name T895
Test name
Test status
Simulation time 1473639861 ps
CPU time 4.86 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:38 PM PDT 24
Peak memory 201412 kb
Host smart-a2fa13f6-076d-4c6b-b73c-85d8230807c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300842549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3300842549
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.669097924
Short name T25
Test name
Test status
Simulation time 711636530 ps
CPU time 2.32 seconds
Started Aug 06 07:31:32 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 201248 kb
Host smart-b732a899-1f9c-412b-b92d-650037d255a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669097924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.669097924
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3336213587
Short name T846
Test name
Test status
Simulation time 464498334 ps
CPU time 1.9 seconds
Started Aug 06 07:31:32 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 201472 kb
Host smart-18163bce-1559-4783-b333-a65b22717d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336213587 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3336213587
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1312034007
Short name T840
Test name
Test status
Simulation time 451025464 ps
CPU time 0.92 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 201324 kb
Host smart-5497d3a3-884b-4485-a5a3-5e8a01366ed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312034007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1312034007
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3872909072
Short name T796
Test name
Test status
Simulation time 377047244 ps
CPU time 0.83 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:35 PM PDT 24
Peak memory 201352 kb
Host smart-c8b9720c-2068-4179-b7a7-01fe48c98288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872909072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3872909072
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.808790082
Short name T119
Test name
Test status
Simulation time 2621257162 ps
CPU time 9.36 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:44 PM PDT 24
Peak memory 201400 kb
Host smart-b19cd503-4f62-401f-8a8b-594351939f9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808790082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.808790082
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3146081140
Short name T71
Test name
Test status
Simulation time 466994880 ps
CPU time 2.93 seconds
Started Aug 06 07:31:37 PM PDT 24
Finished Aug 06 07:31:40 PM PDT 24
Peak memory 201588 kb
Host smart-b8cf69ae-da54-458c-933c-a1940c9c99e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146081140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3146081140
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1921633723
Short name T354
Test name
Test status
Simulation time 9062270830 ps
CPU time 7.13 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:43 PM PDT 24
Peak memory 201664 kb
Host smart-198bebfc-e4e7-4aff-a9a3-63cc3ad31d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921633723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1921633723
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.110051910
Short name T815
Test name
Test status
Simulation time 507609487 ps
CPU time 0.9 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:32:20 PM PDT 24
Peak memory 201344 kb
Host smart-687a40e4-2779-4bf0-9b9a-028c28d063f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110051910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.110051910
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2730398774
Short name T795
Test name
Test status
Simulation time 472080940 ps
CPU time 1.04 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201336 kb
Host smart-3a1efbb3-b172-4209-bd5a-8af3e9600714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730398774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2730398774
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.114863133
Short name T800
Test name
Test status
Simulation time 479796247 ps
CPU time 1.22 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:32:14 PM PDT 24
Peak memory 201320 kb
Host smart-7fee10c2-6a8a-4ea4-b5f4-ef41518cc2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114863133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.114863133
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1947457083
Short name T906
Test name
Test status
Simulation time 323187510 ps
CPU time 0.8 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:32:21 PM PDT 24
Peak memory 201328 kb
Host smart-d7cd0384-bca8-4036-ace0-cd249bdb1ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947457083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1947457083
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4094276441
Short name T911
Test name
Test status
Simulation time 399706522 ps
CPU time 0.71 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:12 PM PDT 24
Peak memory 201312 kb
Host smart-cccc2d42-9c4b-4d06-b8f4-1ef7fe6c0b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094276441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4094276441
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.179781058
Short name T828
Test name
Test status
Simulation time 380440678 ps
CPU time 1.4 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:32:16 PM PDT 24
Peak memory 201348 kb
Host smart-6abec86f-308c-4e9c-8809-fdabb46c64a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179781058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.179781058
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.813922000
Short name T865
Test name
Test status
Simulation time 329399300 ps
CPU time 1.36 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:32:17 PM PDT 24
Peak memory 201380 kb
Host smart-2d9ac30f-39bc-43f7-a53c-eb6d5c232641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813922000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.813922000
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.959766960
Short name T875
Test name
Test status
Simulation time 473750232 ps
CPU time 1.19 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201368 kb
Host smart-d4302e06-c80d-4bbd-9a68-459d1b0a8bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959766960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.959766960
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3055989221
Short name T902
Test name
Test status
Simulation time 498014193 ps
CPU time 1.04 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201328 kb
Host smart-87a99ea5-ea19-4cac-b091-9d851ab6f2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055989221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3055989221
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.176900118
Short name T806
Test name
Test status
Simulation time 435073895 ps
CPU time 0.86 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:32:21 PM PDT 24
Peak memory 201336 kb
Host smart-cd589a6e-0741-4635-a008-d5eea68aa02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176900118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.176900118
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2472901904
Short name T898
Test name
Test status
Simulation time 565660816 ps
CPU time 2.1 seconds
Started Aug 06 07:31:32 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 201508 kb
Host smart-aa7f70b8-9a2c-477f-9667-448e87d7e6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472901904 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2472901904
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.891756251
Short name T913
Test name
Test status
Simulation time 513249318 ps
CPU time 0.92 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:35 PM PDT 24
Peak memory 201336 kb
Host smart-591ae2e6-f83a-4210-bbba-25f5fabf4bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891756251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.891756251
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.739457222
Short name T860
Test name
Test status
Simulation time 453410439 ps
CPU time 1.69 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201352 kb
Host smart-3a3fe888-2b8b-46c0-9a51-472b78636e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739457222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.739457222
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.23099286
Short name T818
Test name
Test status
Simulation time 4673022900 ps
CPU time 4.78 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:40 PM PDT 24
Peak memory 201560 kb
Host smart-27c18492-8437-4082-9da6-6c7b315b5df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctr
l_same_csr_outstanding.23099286
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1116158488
Short name T816
Test name
Test status
Simulation time 505671040 ps
CPU time 1.35 seconds
Started Aug 06 07:31:37 PM PDT 24
Finished Aug 06 07:31:38 PM PDT 24
Peak memory 201416 kb
Host smart-a37e47b1-e162-4763-920d-a0fb95d8c3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116158488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1116158488
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3940314138
Short name T32
Test name
Test status
Simulation time 4279407041 ps
CPU time 11.46 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:47 PM PDT 24
Peak memory 201644 kb
Host smart-edd46afa-51f5-4c5e-9f8e-3cc7daca721a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940314138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3940314138
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3381292534
Short name T838
Test name
Test status
Simulation time 510846235 ps
CPU time 2.07 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201504 kb
Host smart-bdefc589-de67-4cfb-8a21-e61c2261ea00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381292534 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3381292534
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.905005917
Short name T111
Test name
Test status
Simulation time 415009368 ps
CPU time 0.92 seconds
Started Aug 06 07:31:36 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201340 kb
Host smart-9c758a5d-b199-44af-8951-3916155b66b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905005917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.905005917
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2836868558
Short name T878
Test name
Test status
Simulation time 502254930 ps
CPU time 0.96 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:35 PM PDT 24
Peak memory 201400 kb
Host smart-f1f39f0f-a2c0-476d-8e2f-0beb89900189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836868558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2836868558
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3521694816
Short name T120
Test name
Test status
Simulation time 2045076166 ps
CPU time 4.75 seconds
Started Aug 06 07:31:34 PM PDT 24
Finished Aug 06 07:31:39 PM PDT 24
Peak memory 201336 kb
Host smart-a27f932d-c2af-44ad-b44e-d019a1fdc82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521694816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3521694816
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.913937790
Short name T897
Test name
Test status
Simulation time 520931004 ps
CPU time 3.38 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:39 PM PDT 24
Peak memory 201684 kb
Host smart-47570454-52b9-4f8b-9db3-cef2720d19dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913937790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.913937790
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2177402722
Short name T866
Test name
Test status
Simulation time 7703751303 ps
CPU time 9.62 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:45 PM PDT 24
Peak memory 201648 kb
Host smart-57845f6b-8cd9-466c-9222-574c0d8ff20f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177402722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2177402722
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2596997997
Short name T64
Test name
Test status
Simulation time 540513320 ps
CPU time 1.34 seconds
Started Aug 06 07:31:52 PM PDT 24
Finished Aug 06 07:31:53 PM PDT 24
Peak memory 209816 kb
Host smart-d4f2e24a-6c3d-47cf-b3d6-9aefda32288c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596997997 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2596997997
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1079557931
Short name T888
Test name
Test status
Simulation time 340547057 ps
CPU time 1.21 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201348 kb
Host smart-afdf9711-9338-4bd7-aab3-5132fb364fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079557931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1079557931
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.438974055
Short name T811
Test name
Test status
Simulation time 379834271 ps
CPU time 0.76 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:34 PM PDT 24
Peak memory 201320 kb
Host smart-60290b9d-7cd8-437d-9368-3f015c4fc1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438974055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.438974055
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2668802865
Short name T57
Test name
Test status
Simulation time 4428338792 ps
CPU time 11.02 seconds
Started Aug 06 07:31:36 PM PDT 24
Finished Aug 06 07:31:47 PM PDT 24
Peak memory 201604 kb
Host smart-a72d901f-5606-49fc-b4c2-c6563337ad0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668802865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2668802865
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3739341999
Short name T819
Test name
Test status
Simulation time 334961321 ps
CPU time 2.29 seconds
Started Aug 06 07:31:35 PM PDT 24
Finished Aug 06 07:31:37 PM PDT 24
Peak memory 201604 kb
Host smart-ca2980ab-d5ac-4ee1-91db-e884a9e83ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739341999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3739341999
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.633302168
Short name T900
Test name
Test status
Simulation time 8264750735 ps
CPU time 11.85 seconds
Started Aug 06 07:31:33 PM PDT 24
Finished Aug 06 07:31:45 PM PDT 24
Peak memory 201528 kb
Host smart-54e2a4c3-2a12-44c1-be96-93896f2d7647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633302168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.633302168
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2267482805
Short name T850
Test name
Test status
Simulation time 624096844 ps
CPU time 1.25 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:00 PM PDT 24
Peak memory 201336 kb
Host smart-81781932-caad-4555-b518-ebb52f29c87d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267482805 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2267482805
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3333616407
Short name T115
Test name
Test status
Simulation time 513894260 ps
CPU time 0.98 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201320 kb
Host smart-ea9286dc-91a4-4087-8c0e-75235afdda2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333616407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3333616407
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2219494789
Short name T882
Test name
Test status
Simulation time 297941149 ps
CPU time 1.27 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201360 kb
Host smart-e4642570-6965-4643-b0a9-84afaf79fc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219494789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2219494789
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2310649814
Short name T59
Test name
Test status
Simulation time 2233826120 ps
CPU time 5.29 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:59 PM PDT 24
Peak memory 201412 kb
Host smart-6a787d55-8427-4401-82b5-72c1300644f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310649814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2310649814
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1272471578
Short name T839
Test name
Test status
Simulation time 489548634 ps
CPU time 2.26 seconds
Started Aug 06 07:31:53 PM PDT 24
Finished Aug 06 07:31:55 PM PDT 24
Peak memory 201640 kb
Host smart-389550ee-4a55-4127-ba14-a6de7434dc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272471578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1272471578
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1821760583
Short name T76
Test name
Test status
Simulation time 4322294234 ps
CPU time 6.7 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:32:01 PM PDT 24
Peak memory 201664 kb
Host smart-af9bca2e-fe04-43f1-888f-4bd58fe83a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821760583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1821760583
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3258888238
Short name T75
Test name
Test status
Simulation time 476706114 ps
CPU time 1.91 seconds
Started Aug 06 07:31:54 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201404 kb
Host smart-abfaaf7e-0719-4939-a286-1f2c9ac4ecce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258888238 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3258888238
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.384624200
Short name T910
Test name
Test status
Simulation time 570595453 ps
CPU time 2.12 seconds
Started Aug 06 07:31:52 PM PDT 24
Finished Aug 06 07:31:54 PM PDT 24
Peak memory 201316 kb
Host smart-33893ba4-7c88-487d-a84e-d1e99e4de266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384624200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.384624200
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1125759381
Short name T891
Test name
Test status
Simulation time 502428492 ps
CPU time 1.76 seconds
Started Aug 06 07:31:56 PM PDT 24
Finished Aug 06 07:31:58 PM PDT 24
Peak memory 201356 kb
Host smart-e59cd149-7274-455e-9d82-cfdb872ecb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125759381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1125759381
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1051754191
Short name T852
Test name
Test status
Simulation time 5400549956 ps
CPU time 8.46 seconds
Started Aug 06 07:32:00 PM PDT 24
Finished Aug 06 07:32:09 PM PDT 24
Peak memory 201648 kb
Host smart-048c605a-8452-43be-994e-5befbd8147b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051754191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1051754191
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1674407780
Short name T858
Test name
Test status
Simulation time 338066034 ps
CPU time 2.02 seconds
Started Aug 06 07:31:55 PM PDT 24
Finished Aug 06 07:31:57 PM PDT 24
Peak memory 201536 kb
Host smart-de2f3157-2c8e-4428-ba53-cbd54be2cf99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674407780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1674407780
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1395053965
Short name T914
Test name
Test status
Simulation time 4844008505 ps
CPU time 6.71 seconds
Started Aug 06 07:31:59 PM PDT 24
Finished Aug 06 07:32:06 PM PDT 24
Peak memory 201704 kb
Host smart-3044f83e-750b-4f67-9091-a4a0ffcc3d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395053965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1395053965
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1259088488
Short name T235
Test name
Test status
Simulation time 352836473235 ps
CPU time 419.53 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:39:18 PM PDT 24
Peak memory 201540 kb
Host smart-354a1a65-e57f-4001-86f3-deff7d8d565f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259088488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1259088488
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.262306529
Short name T4
Test name
Test status
Simulation time 194612263673 ps
CPU time 295.16 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:37:13 PM PDT 24
Peak memory 201524 kb
Host smart-888cfb6c-3789-4a1f-9e48-4be8e7e605ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262306529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.262306529
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2318104979
Short name T169
Test name
Test status
Simulation time 492942502684 ps
CPU time 76.27 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:33:29 PM PDT 24
Peak memory 201480 kb
Host smart-a70ea1d9-84d0-4b55-96f6-fb7b2818fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318104979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2318104979
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2863019250
Short name T570
Test name
Test status
Simulation time 162778578929 ps
CPU time 364.14 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:38:19 PM PDT 24
Peak memory 201448 kb
Host smart-a8352b4f-d482-41ee-8104-a4d251145442
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863019250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2863019250
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4237290640
Short name T387
Test name
Test status
Simulation time 491131677992 ps
CPU time 567.07 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:41:46 PM PDT 24
Peak memory 201432 kb
Host smart-104a5d1a-8043-4600-aa62-75e16cec5b92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237290640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4237290640
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1086973742
Short name T446
Test name
Test status
Simulation time 202519935942 ps
CPU time 140.32 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:34:33 PM PDT 24
Peak memory 201348 kb
Host smart-2dc5bac4-1929-46cc-b0aa-06beae790925
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086973742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1086973742
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1407587480
Short name T389
Test name
Test status
Simulation time 212399685640 ps
CPU time 202.33 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:35:43 PM PDT 24
Peak memory 201444 kb
Host smart-63dabbd5-53c0-49e5-86f0-70d706830ed5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407587480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1407587480
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.969207205
Short name T719
Test name
Test status
Simulation time 118317531714 ps
CPU time 620.88 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:42:38 PM PDT 24
Peak memory 201816 kb
Host smart-3baceae7-9b90-4bae-a4a8-d82c32433763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969207205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.969207205
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4138712022
Short name T386
Test name
Test status
Simulation time 24115179774 ps
CPU time 58.91 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:33:16 PM PDT 24
Peak memory 201328 kb
Host smart-79b94c22-18ca-4278-b7c9-310a3d47acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138712022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4138712022
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2492120467
Short name T484
Test name
Test status
Simulation time 3819170330 ps
CPU time 5.31 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 201308 kb
Host smart-1a0677df-c870-448c-92a1-686d0ecd1252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492120467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2492120467
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.429657097
Short name T77
Test name
Test status
Simulation time 8159373727 ps
CPU time 18.8 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:37 PM PDT 24
Peak memory 218224 kb
Host smart-432f06ea-5faf-48c2-bc1a-ffe03a05ca0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429657097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.429657097
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1363692576
Short name T28
Test name
Test status
Simulation time 5742203615 ps
CPU time 7.11 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:32:26 PM PDT 24
Peak memory 201376 kb
Host smart-8618671d-ee8a-47b5-a0ad-d1686a45b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363692576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1363692576
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1248642489
Short name T346
Test name
Test status
Simulation time 351882752099 ps
CPU time 455.69 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:39:54 PM PDT 24
Peak memory 201480 kb
Host smart-54ab2b6d-dd9a-4ec2-9d7d-28ed6112d350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248642489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1248642489
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4279034069
Short name T303
Test name
Test status
Simulation time 90486204580 ps
CPU time 206.97 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:35:46 PM PDT 24
Peak memory 218316 kb
Host smart-611b574d-6e2b-4c68-8c7b-b470e106f25a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279034069 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4279034069
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1532987381
Short name T496
Test name
Test status
Simulation time 443137188 ps
CPU time 1.29 seconds
Started Aug 06 07:32:11 PM PDT 24
Finished Aug 06 07:32:13 PM PDT 24
Peak memory 201220 kb
Host smart-9ee3cc7a-766e-4774-b58d-49aeb295b3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532987381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1532987381
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1528703912
Short name T265
Test name
Test status
Simulation time 210261057561 ps
CPU time 449.06 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:39:46 PM PDT 24
Peak memory 201492 kb
Host smart-53d5dd80-82f8-461b-ad20-16549a178e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528703912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1528703912
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1562016345
Short name T659
Test name
Test status
Simulation time 329316428630 ps
CPU time 71.14 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:33:31 PM PDT 24
Peak memory 201456 kb
Host smart-5ed3ede2-14f6-41ea-9116-43c1950cecc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562016345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1562016345
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1764988782
Short name T135
Test name
Test status
Simulation time 499651577159 ps
CPU time 1148.01 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 201384 kb
Host smart-4d2cebae-435d-4447-b27e-b2452d616d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764988782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1764988782
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3773406561
Short name T673
Test name
Test status
Simulation time 165999428088 ps
CPU time 69.56 seconds
Started Aug 06 07:32:14 PM PDT 24
Finished Aug 06 07:33:24 PM PDT 24
Peak memory 201364 kb
Host smart-4d93a12a-34b4-451c-9603-bcc9b1f22ab2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773406561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3773406561
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2586016546
Short name T92
Test name
Test status
Simulation time 169289508288 ps
CPU time 26.24 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:44 PM PDT 24
Peak memory 201420 kb
Host smart-08804853-30f0-4dc8-ae98-c7f90be27896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586016546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2586016546
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4242338175
Short name T638
Test name
Test status
Simulation time 614489001045 ps
CPU time 386.91 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:38:39 PM PDT 24
Peak memory 201476 kb
Host smart-62123de5-220d-4ae7-84f8-752f59a3cf00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242338175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4242338175
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1366693709
Short name T675
Test name
Test status
Simulation time 38069972854 ps
CPU time 23.78 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:32:36 PM PDT 24
Peak memory 201328 kb
Host smart-003b6951-5b6b-477c-be31-18886828b0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366693709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1366693709
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.654629976
Short name T123
Test name
Test status
Simulation time 3159084961 ps
CPU time 7.97 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 201324 kb
Host smart-eccf4550-c2c3-410f-a69f-dd6af60cdb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654629976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.654629976
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.240759940
Short name T440
Test name
Test status
Simulation time 5968395933 ps
CPU time 2.89 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:21 PM PDT 24
Peak memory 201328 kb
Host smart-0a4e56fa-27f0-4a6f-b1e1-164b1a484259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240759940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.240759940
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3172607397
Short name T23
Test name
Test status
Simulation time 132792121037 ps
CPU time 157.27 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:34:55 PM PDT 24
Peak memory 210864 kb
Host smart-f778a27e-d42c-4a23-826b-f32276e27d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172607397 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3172607397
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.915061589
Short name T502
Test name
Test status
Simulation time 479528124 ps
CPU time 0.96 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:33:03 PM PDT 24
Peak memory 201372 kb
Host smart-481f93cc-6d69-4866-94c8-f11e16411c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915061589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.915061589
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3896079845
Short name T692
Test name
Test status
Simulation time 161268804046 ps
CPU time 102.95 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:34:42 PM PDT 24
Peak memory 201528 kb
Host smart-d1f1d381-fa9e-4336-a276-4b2579b6e457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896079845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3896079845
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.698705045
Short name T644
Test name
Test status
Simulation time 327270280619 ps
CPU time 426.76 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:40:04 PM PDT 24
Peak memory 201384 kb
Host smart-8050abcb-4d50-4646-b796-088ed4912870
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=698705045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.698705045
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.766433126
Short name T13
Test name
Test status
Simulation time 331391565457 ps
CPU time 709.17 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:44:48 PM PDT 24
Peak memory 201472 kb
Host smart-a91aa7ae-5f9f-4489-b3b9-e3659aca830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766433126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.766433126
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3356681569
Short name T543
Test name
Test status
Simulation time 160833215238 ps
CPU time 344.69 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:38:42 PM PDT 24
Peak memory 201468 kb
Host smart-b9ca8870-84da-428d-ab29-08797d54d0bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356681569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3356681569
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2311071789
Short name T338
Test name
Test status
Simulation time 178778313729 ps
CPU time 282.05 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:37:45 PM PDT 24
Peak memory 201412 kb
Host smart-10a1dd14-1539-4ff7-8975-7e67a9adc63a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311071789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2311071789
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2574032163
Short name T88
Test name
Test status
Simulation time 199442355276 ps
CPU time 451.76 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:40:30 PM PDT 24
Peak memory 201384 kb
Host smart-aa48e390-2ad1-428d-a1a3-dde5a9b3d17e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574032163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2574032163
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1824160302
Short name T409
Test name
Test status
Simulation time 121748231244 ps
CPU time 423.02 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:40:03 PM PDT 24
Peak memory 201868 kb
Host smart-74b42081-1737-4e8f-b464-d7cfbf8e11e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824160302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1824160302
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2043653116
Short name T95
Test name
Test status
Simulation time 35912279276 ps
CPU time 40.8 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:33:39 PM PDT 24
Peak memory 201364 kb
Host smart-30fe581b-11d8-414d-b5d2-58326d0fc85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043653116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2043653116
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3714881472
Short name T632
Test name
Test status
Simulation time 5124312540 ps
CPU time 2.38 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:33:01 PM PDT 24
Peak memory 201356 kb
Host smart-68b51db6-e41f-44e7-ab25-f4225de17acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714881472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3714881472
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1701843634
Short name T81
Test name
Test status
Simulation time 5648039669 ps
CPU time 12.14 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:33:10 PM PDT 24
Peak memory 201344 kb
Host smart-956aa873-d17e-457a-bed5-feace406617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701843634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1701843634
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.139709814
Short name T615
Test name
Test status
Simulation time 413690754804 ps
CPU time 753.07 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:45:33 PM PDT 24
Peak memory 201472 kb
Host smart-21fb21a7-98dd-46a4-a2d1-f2eb58e0e793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139709814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
139709814
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1224879629
Short name T21
Test name
Test status
Simulation time 35430106457 ps
CPU time 67.75 seconds
Started Aug 06 07:33:03 PM PDT 24
Finished Aug 06 07:34:11 PM PDT 24
Peak memory 209780 kb
Host smart-4c3ddd0d-d6fd-4492-b76d-8b09e198bc5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224879629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1224879629
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1099460836
Short name T668
Test name
Test status
Simulation time 493554524 ps
CPU time 1.16 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:32:59 PM PDT 24
Peak memory 201244 kb
Host smart-045984d3-25cc-405a-863c-35f9f73d22ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099460836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1099460836
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4174622595
Short name T294
Test name
Test status
Simulation time 334598223791 ps
CPU time 339.34 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:38:39 PM PDT 24
Peak memory 201344 kb
Host smart-260edcff-c472-4b4f-8220-2fc60f5d61c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174622595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4174622595
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3246929428
Short name T205
Test name
Test status
Simulation time 328177001447 ps
CPU time 211.9 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:36:32 PM PDT 24
Peak memory 201540 kb
Host smart-acf4fd5b-d81f-44b1-ac21-accbbb20e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246929428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3246929428
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2265128131
Short name T407
Test name
Test status
Simulation time 493738108780 ps
CPU time 1140.99 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 201408 kb
Host smart-9bdc421e-e01c-4b0c-9d93-da4bcc4bd870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265128131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2265128131
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3795704256
Short name T539
Test name
Test status
Simulation time 165930180383 ps
CPU time 181.11 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:35:59 PM PDT 24
Peak memory 201420 kb
Host smart-efa9983e-fa63-4a9d-8607-0275b5f2afc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795704256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3795704256
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2604026743
Short name T337
Test name
Test status
Simulation time 176232805018 ps
CPU time 81.72 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:34:24 PM PDT 24
Peak memory 201412 kb
Host smart-3206fb16-aaf1-41f3-bdc3-a84cd7f4e626
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604026743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2604026743
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1176742117
Short name T455
Test name
Test status
Simulation time 598265925425 ps
CPU time 746.6 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:45:30 PM PDT 24
Peak memory 201428 kb
Host smart-d2056b4f-791f-41d8-bbe1-13075da28648
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176742117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1176742117
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2469729765
Short name T514
Test name
Test status
Simulation time 88695074606 ps
CPU time 287.63 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:37:51 PM PDT 24
Peak memory 201744 kb
Host smart-2d8d8247-f67e-441c-bc6b-dc13f61c14b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469729765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2469729765
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1190343151
Short name T506
Test name
Test status
Simulation time 25607001081 ps
CPU time 14.3 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:33:16 PM PDT 24
Peak memory 201344 kb
Host smart-c2b0db5f-79db-4dd3-bc8d-194c44523a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190343151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1190343151
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.343475434
Short name T640
Test name
Test status
Simulation time 5178146534 ps
CPU time 13.61 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:33:14 PM PDT 24
Peak memory 201320 kb
Host smart-51bbc21b-d597-44a9-8c29-12380bc1eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343475434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.343475434
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3165377824
Short name T418
Test name
Test status
Simulation time 5842120594 ps
CPU time 12.57 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:33:12 PM PDT 24
Peak memory 201284 kb
Host smart-cece22cd-c9f1-4252-bddb-ee06fe0e35de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165377824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3165377824
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.743572545
Short name T532
Test name
Test status
Simulation time 56481187711 ps
CPU time 30.94 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:33:30 PM PDT 24
Peak memory 201372 kb
Host smart-3ca25133-6990-4f32-abaa-5b27130afa2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743572545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
743572545
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4260461836
Short name T190
Test name
Test status
Simulation time 398492079 ps
CPU time 1.45 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:33:03 PM PDT 24
Peak memory 201208 kb
Host smart-f63835bb-a0a1-415b-adf1-381316eafba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260461836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4260461836
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2516633252
Short name T144
Test name
Test status
Simulation time 564027460362 ps
CPU time 463.18 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:40:45 PM PDT 24
Peak memory 201432 kb
Host smart-23a9e74f-8837-4eb4-9819-84e3647bd458
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516633252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2516633252
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3770227320
Short name T622
Test name
Test status
Simulation time 157249684432 ps
CPU time 359.98 seconds
Started Aug 06 07:33:04 PM PDT 24
Finished Aug 06 07:39:04 PM PDT 24
Peak memory 201324 kb
Host smart-493a4b93-3d57-4514-9ad1-0baa5b81c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770227320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3770227320
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1486761984
Short name T678
Test name
Test status
Simulation time 329896615802 ps
CPU time 127.73 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:35:10 PM PDT 24
Peak memory 201428 kb
Host smart-4f36c058-51de-48f7-a2ed-97b82cbddf38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486761984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1486761984
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1624964063
Short name T665
Test name
Test status
Simulation time 163761333501 ps
CPU time 362.18 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:39:03 PM PDT 24
Peak memory 201404 kb
Host smart-f6986625-5b66-41a1-905e-79e35e5805b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624964063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1624964063
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.513681402
Short name T430
Test name
Test status
Simulation time 500444781058 ps
CPU time 1176.15 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:52:38 PM PDT 24
Peak memory 201456 kb
Host smart-0b018c06-08e1-4177-8b97-f502a60624e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=513681402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.513681402
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4144369107
Short name T401
Test name
Test status
Simulation time 596902585859 ps
CPU time 1244.67 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:53:44 PM PDT 24
Peak memory 201432 kb
Host smart-a4d41edc-d8db-4c20-b347-00a5b9da167d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144369107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4144369107
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1138445968
Short name T712
Test name
Test status
Simulation time 98083909094 ps
CPU time 421.65 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:40:03 PM PDT 24
Peak memory 201824 kb
Host smart-a63874d3-982d-4688-8aaf-afcad31ad4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138445968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1138445968
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2797295733
Short name T627
Test name
Test status
Simulation time 31646758126 ps
CPU time 74.54 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:34:17 PM PDT 24
Peak memory 201340 kb
Host smart-c29c0ffe-0604-440c-a674-2aaf9b71076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797295733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2797295733
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3559035091
Short name T766
Test name
Test status
Simulation time 3066115041 ps
CPU time 4.4 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:33:07 PM PDT 24
Peak memory 201312 kb
Host smart-1243b477-f91d-434c-86a9-911f313d899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559035091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3559035091
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1117303034
Short name T367
Test name
Test status
Simulation time 5979937317 ps
CPU time 9.43 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:33:07 PM PDT 24
Peak memory 201360 kb
Host smart-671df7c0-85ad-4c62-9c9d-9529456477ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117303034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1117303034
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2227990034
Short name T519
Test name
Test status
Simulation time 477590806 ps
CPU time 0.71 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:33:03 PM PDT 24
Peak memory 201244 kb
Host smart-9d36a139-dd6c-410a-b393-eeb8d45685e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227990034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2227990034
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1630260402
Short name T283
Test name
Test status
Simulation time 502270867736 ps
CPU time 691.91 seconds
Started Aug 06 07:33:03 PM PDT 24
Finished Aug 06 07:44:36 PM PDT 24
Peak memory 201496 kb
Host smart-92a95da9-7245-49cd-8095-c098ffeb537b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630260402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1630260402
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1628244977
Short name T793
Test name
Test status
Simulation time 536581487756 ps
CPU time 352.57 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:38:51 PM PDT 24
Peak memory 201436 kb
Host smart-041da1d9-a696-4a95-b037-9b682862f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628244977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1628244977
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2637771664
Short name T649
Test name
Test status
Simulation time 492823852463 ps
CPU time 289.42 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:37:51 PM PDT 24
Peak memory 201488 kb
Host smart-a72bac62-8b36-4adb-980e-fab14a5ebd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637771664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2637771664
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.11701412
Short name T746
Test name
Test status
Simulation time 169548575288 ps
CPU time 388.38 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:39:31 PM PDT 24
Peak memory 201400 kb
Host smart-9a36cd83-efa5-426d-8424-d4b0a0d8f6d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt
_fixed.11701412
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1519289468
Short name T454
Test name
Test status
Simulation time 162182095178 ps
CPU time 194.16 seconds
Started Aug 06 07:32:59 PM PDT 24
Finished Aug 06 07:36:14 PM PDT 24
Peak memory 201484 kb
Host smart-a382673a-f17a-442d-8814-958b361490d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519289468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1519289468
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2932312793
Short name T741
Test name
Test status
Simulation time 204095571489 ps
CPU time 431.39 seconds
Started Aug 06 07:33:04 PM PDT 24
Finished Aug 06 07:40:15 PM PDT 24
Peak memory 201324 kb
Host smart-cd51f2c9-b7bd-4796-a60e-c726d6f0223f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932312793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2932312793
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3995696980
Short name T670
Test name
Test status
Simulation time 111555402436 ps
CPU time 394.13 seconds
Started Aug 06 07:33:05 PM PDT 24
Finished Aug 06 07:39:40 PM PDT 24
Peak memory 201844 kb
Host smart-8b865739-edea-4201-8dd6-7e8ff9a455db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995696980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3995696980
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4149891204
Short name T414
Test name
Test status
Simulation time 40925796552 ps
CPU time 94.69 seconds
Started Aug 06 07:33:06 PM PDT 24
Finished Aug 06 07:34:41 PM PDT 24
Peak memory 201372 kb
Host smart-d9cd6b47-2937-4230-a030-75f37cd4ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149891204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4149891204
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3796426834
Short name T676
Test name
Test status
Simulation time 4590997807 ps
CPU time 5.62 seconds
Started Aug 06 07:33:03 PM PDT 24
Finished Aug 06 07:33:09 PM PDT 24
Peak memory 201212 kb
Host smart-c6bb0181-1ff1-4de6-b13c-590889703b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796426834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3796426834
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.355968423
Short name T459
Test name
Test status
Simulation time 5809054751 ps
CPU time 15.22 seconds
Started Aug 06 07:33:04 PM PDT 24
Finished Aug 06 07:33:19 PM PDT 24
Peak memory 201360 kb
Host smart-c99b204a-15e6-4f03-ada2-15e454866ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355968423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.355968423
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3446365213
Short name T33
Test name
Test status
Simulation time 167277753085 ps
CPU time 202.87 seconds
Started Aug 06 07:33:06 PM PDT 24
Finished Aug 06 07:36:29 PM PDT 24
Peak memory 201460 kb
Host smart-df54ad7b-4546-4a76-8f77-8e73f9ca7fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446365213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3446365213
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2722901753
Short name T589
Test name
Test status
Simulation time 562739358508 ps
CPU time 154.31 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:35:37 PM PDT 24
Peak memory 209728 kb
Host smart-f10bec91-03a7-4d43-b628-f772b293d7f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722901753 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2722901753
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2690620486
Short name T635
Test name
Test status
Simulation time 300473171 ps
CPU time 0.92 seconds
Started Aug 06 07:33:17 PM PDT 24
Finished Aug 06 07:33:18 PM PDT 24
Peak memory 201236 kb
Host smart-71b20afd-9d84-4a68-b6d8-d492ae9711ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690620486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2690620486
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3144859818
Short name T557
Test name
Test status
Simulation time 489320873443 ps
CPU time 1057.66 seconds
Started Aug 06 07:33:18 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 201460 kb
Host smart-4a01ce2c-84dc-4a12-8599-ffd2a43728b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144859818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3144859818
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2194915686
Short name T90
Test name
Test status
Simulation time 483785388489 ps
CPU time 207.56 seconds
Started Aug 06 07:33:15 PM PDT 24
Finished Aug 06 07:36:43 PM PDT 24
Peak memory 201440 kb
Host smart-14957fd4-61bf-409c-b97b-ba230488b6eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194915686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2194915686
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3320860757
Short name T441
Test name
Test status
Simulation time 329827714284 ps
CPU time 79.65 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:34:22 PM PDT 24
Peak memory 201464 kb
Host smart-5c52a1ec-2322-4fce-aae3-fe14af4930b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320860757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3320860757
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2750543898
Short name T179
Test name
Test status
Simulation time 492777166612 ps
CPU time 1034.25 seconds
Started Aug 06 07:33:20 PM PDT 24
Finished Aug 06 07:50:35 PM PDT 24
Peak memory 201460 kb
Host smart-c33fb9f0-933b-48a2-8a95-692c8d98f67e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750543898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2750543898
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1470945665
Short name T154
Test name
Test status
Simulation time 207091578389 ps
CPU time 130.79 seconds
Started Aug 06 07:33:16 PM PDT 24
Finished Aug 06 07:35:27 PM PDT 24
Peak memory 201444 kb
Host smart-d312f953-d45b-43d8-b77f-4e4c58012c07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470945665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1470945665
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2246314046
Short name T576
Test name
Test status
Simulation time 200984147310 ps
CPU time 451.25 seconds
Started Aug 06 07:33:17 PM PDT 24
Finished Aug 06 07:40:49 PM PDT 24
Peak memory 201456 kb
Host smart-f57be3dd-207b-4863-8200-29373be2625d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246314046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2246314046
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.311251319
Short name T569
Test name
Test status
Simulation time 118660868927 ps
CPU time 600.1 seconds
Started Aug 06 07:33:22 PM PDT 24
Finished Aug 06 07:43:22 PM PDT 24
Peak memory 201856 kb
Host smart-00cd40dd-b584-4450-b875-3930de67da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311251319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.311251319
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1763032390
Short name T396
Test name
Test status
Simulation time 26203146388 ps
CPU time 15.88 seconds
Started Aug 06 07:33:18 PM PDT 24
Finished Aug 06 07:33:34 PM PDT 24
Peak memory 201348 kb
Host smart-72634a64-26fb-49be-8cae-fda3d860ddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763032390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1763032390
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2532906871
Short name T735
Test name
Test status
Simulation time 5175003846 ps
CPU time 6.88 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:33:26 PM PDT 24
Peak memory 201328 kb
Host smart-51eea717-674f-486a-a46b-d8e10a3bd73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532906871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2532906871
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1978530895
Short name T416
Test name
Test status
Simulation time 6000101902 ps
CPU time 2.47 seconds
Started Aug 06 07:33:02 PM PDT 24
Finished Aug 06 07:33:05 PM PDT 24
Peak memory 201172 kb
Host smart-7a2da290-3de5-4edb-8de4-9650f224cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978530895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1978530895
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.777853715
Short name T18
Test name
Test status
Simulation time 12656284050 ps
CPU time 31.98 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:33:53 PM PDT 24
Peak memory 209748 kb
Host smart-c1c152a3-d4b0-49d2-b556-94e4c8bfb605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777853715 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.777853715
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.7886913
Short name T583
Test name
Test status
Simulation time 351972018 ps
CPU time 0.83 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:33:32 PM PDT 24
Peak memory 201216 kb
Host smart-8ab0df43-0828-4423-b846-f01cae4c126b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7886913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.7886913
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1993057277
Short name T336
Test name
Test status
Simulation time 348349029252 ps
CPU time 132.05 seconds
Started Aug 06 07:33:20 PM PDT 24
Finished Aug 06 07:35:32 PM PDT 24
Peak memory 201452 kb
Host smart-707cf688-7f9e-4edd-a4c3-457d133b096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993057277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1993057277
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2032195861
Short name T100
Test name
Test status
Simulation time 321947944114 ps
CPU time 77.89 seconds
Started Aug 06 07:33:20 PM PDT 24
Finished Aug 06 07:34:38 PM PDT 24
Peak memory 201400 kb
Host smart-42dd2c9a-04fe-4cd4-8ce2-236e4a88bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032195861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2032195861
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1537567907
Short name T755
Test name
Test status
Simulation time 167098724703 ps
CPU time 108.34 seconds
Started Aug 06 07:33:38 PM PDT 24
Finished Aug 06 07:35:26 PM PDT 24
Peak memory 201436 kb
Host smart-dacf7ac7-9390-42e4-86cf-49afa5bc1ca1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537567907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1537567907
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3649653098
Short name T249
Test name
Test status
Simulation time 492141074596 ps
CPU time 1155.61 seconds
Started Aug 06 07:33:17 PM PDT 24
Finished Aug 06 07:52:33 PM PDT 24
Peak memory 201452 kb
Host smart-34c6d6cd-5d77-4192-81b5-399a27188e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649653098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3649653098
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.930942465
Short name T384
Test name
Test status
Simulation time 324437603219 ps
CPU time 766.37 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:46:07 PM PDT 24
Peak memory 201424 kb
Host smart-5784dfeb-7705-47e3-a987-b0246ca5d152
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930942465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.930942465
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2706504202
Short name T245
Test name
Test status
Simulation time 664733379344 ps
CPU time 339.83 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:38:59 PM PDT 24
Peak memory 201444 kb
Host smart-e3b71282-b2bd-4fb0-90ee-e73d20cdccac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706504202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2706504202
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2864440759
Short name T729
Test name
Test status
Simulation time 205702281997 ps
CPU time 479.94 seconds
Started Aug 06 07:33:22 PM PDT 24
Finished Aug 06 07:41:22 PM PDT 24
Peak memory 201468 kb
Host smart-5f78bb0b-62f3-449c-ade6-a47477fc19cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864440759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2864440759
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.854431932
Short name T101
Test name
Test status
Simulation time 133061901696 ps
CPU time 380.71 seconds
Started Aug 06 07:33:18 PM PDT 24
Finished Aug 06 07:39:39 PM PDT 24
Peak memory 201800 kb
Host smart-78d2a051-65f1-4c40-af3d-b8b3e11d9137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854431932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.854431932
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2176673059
Short name T597
Test name
Test status
Simulation time 25663250174 ps
CPU time 55.58 seconds
Started Aug 06 07:33:22 PM PDT 24
Finished Aug 06 07:34:17 PM PDT 24
Peak memory 201372 kb
Host smart-03856233-7193-44c9-9f1f-dbf0b3f0b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176673059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2176673059
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1116743924
Short name T593
Test name
Test status
Simulation time 2913234073 ps
CPU time 1.56 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:33:31 PM PDT 24
Peak memory 201324 kb
Host smart-ce0acddd-012b-46e2-83c1-d935a13738a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116743924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1116743924
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2175587790
Short name T763
Test name
Test status
Simulation time 5700412614 ps
CPU time 4.03 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:33:23 PM PDT 24
Peak memory 201332 kb
Host smart-014e3da3-4a3b-4d15-a320-15ef83e39bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175587790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2175587790
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.4246278844
Short name T691
Test name
Test status
Simulation time 114373316345 ps
CPU time 336.48 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:38:56 PM PDT 24
Peak memory 217808 kb
Host smart-cc901489-ca5e-426b-97c3-86c69405f189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246278844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.4246278844
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3985121010
Short name T89
Test name
Test status
Simulation time 522507813 ps
CPU time 1.73 seconds
Started Aug 06 07:33:21 PM PDT 24
Finished Aug 06 07:33:23 PM PDT 24
Peak memory 201248 kb
Host smart-ea69b5d5-0f9a-4ad0-a9d4-925c087327bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985121010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3985121010
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.978925766
Short name T580
Test name
Test status
Simulation time 344585004824 ps
CPU time 792.63 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:46:32 PM PDT 24
Peak memory 201400 kb
Host smart-a9cd370f-0234-484b-a89f-a8fce71737f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978925766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.978925766
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3203642808
Short name T467
Test name
Test status
Simulation time 323471210970 ps
CPU time 709.62 seconds
Started Aug 06 07:33:18 PM PDT 24
Finished Aug 06 07:45:07 PM PDT 24
Peak memory 201640 kb
Host smart-c45ad99b-11f8-42bb-b97c-4f46f1221a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203642808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3203642808
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1301086027
Short name T556
Test name
Test status
Simulation time 497291045686 ps
CPU time 1091.89 seconds
Started Aug 06 07:33:17 PM PDT 24
Finished Aug 06 07:51:29 PM PDT 24
Peak memory 201412 kb
Host smart-e17c646d-b3de-487a-9ee6-e3957caed038
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301086027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1301086027
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4224287776
Short name T164
Test name
Test status
Simulation time 331543944836 ps
CPU time 381.19 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:39:52 PM PDT 24
Peak memory 201428 kb
Host smart-cb68bdbc-167f-4d12-a0df-c18da15b4e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224287776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4224287776
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1361367558
Short name T488
Test name
Test status
Simulation time 330232172957 ps
CPU time 699.1 seconds
Started Aug 06 07:33:16 PM PDT 24
Finished Aug 06 07:44:56 PM PDT 24
Peak memory 201440 kb
Host smart-43de1ad9-edac-4c3f-be9b-e62900ae7294
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361367558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1361367558
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2753666746
Short name T592
Test name
Test status
Simulation time 396534527461 ps
CPU time 828.84 seconds
Started Aug 06 07:33:19 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 201436 kb
Host smart-67e8b460-9268-4059-b714-0fdb50f257e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753666746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2753666746
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2380912730
Short name T54
Test name
Test status
Simulation time 122045293183 ps
CPU time 632.52 seconds
Started Aug 06 07:33:20 PM PDT 24
Finished Aug 06 07:43:53 PM PDT 24
Peak memory 201800 kb
Host smart-78c422f7-8fb6-484a-bd3d-18311c0b2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380912730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2380912730
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1294997058
Short name T9
Test name
Test status
Simulation time 44387286038 ps
CPU time 47.32 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:34:18 PM PDT 24
Peak memory 201336 kb
Host smart-fb607e75-ecec-484b-8d0b-534e759bcfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294997058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1294997058
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1397277612
Short name T94
Test name
Test status
Simulation time 2817056891 ps
CPU time 7.62 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:33:38 PM PDT 24
Peak memory 201324 kb
Host smart-164207b9-3c87-4021-ba94-7600163e18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397277612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1397277612
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2924798792
Short name T529
Test name
Test status
Simulation time 6030132975 ps
CPU time 4.42 seconds
Started Aug 06 07:33:16 PM PDT 24
Finished Aug 06 07:33:20 PM PDT 24
Peak memory 201328 kb
Host smart-1075fd63-3521-4239-9813-c16f78dc7930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924798792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2924798792
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2310535441
Short name T465
Test name
Test status
Simulation time 177741502503 ps
CPU time 94.44 seconds
Started Aug 06 07:33:22 PM PDT 24
Finished Aug 06 07:34:57 PM PDT 24
Peak memory 201460 kb
Host smart-c71524f5-ebf7-4011-b3be-7b7d0f061f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310535441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2310535441
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3466816704
Short name T540
Test name
Test status
Simulation time 291927775 ps
CPU time 1.25 seconds
Started Aug 06 07:33:34 PM PDT 24
Finished Aug 06 07:33:35 PM PDT 24
Peak memory 201228 kb
Host smart-694c5952-5d22-4264-8007-87089fc8a920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466816704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3466816704
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.769678447
Short name T620
Test name
Test status
Simulation time 193416688560 ps
CPU time 236.17 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:37:26 PM PDT 24
Peak memory 201444 kb
Host smart-1cf7ac77-ff06-4293-84a2-1b2af741cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769678447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.769678447
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.372218463
Short name T264
Test name
Test status
Simulation time 324101439180 ps
CPU time 244.46 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:37:35 PM PDT 24
Peak memory 201408 kb
Host smart-e1833e92-a31d-419d-a4e3-acc5b40595a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372218463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.372218463
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.768709702
Short name T690
Test name
Test status
Simulation time 324145211300 ps
CPU time 206.78 seconds
Started Aug 06 07:33:32 PM PDT 24
Finished Aug 06 07:36:59 PM PDT 24
Peak memory 201340 kb
Host smart-6d85c60b-0205-4a03-8915-3c3a42d84025
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=768709702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.768709702
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1018716787
Short name T298
Test name
Test status
Simulation time 328364643552 ps
CPU time 339.74 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:39:10 PM PDT 24
Peak memory 201436 kb
Host smart-598e4bf6-9bd1-4cb1-81b8-0b781f7526ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018716787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1018716787
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3254646336
Short name T12
Test name
Test status
Simulation time 491709385973 ps
CPU time 1152.24 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:52:43 PM PDT 24
Peak memory 201420 kb
Host smart-b384f293-87b8-4517-926f-8c0f30f580cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254646336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3254646336
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3399117997
Short name T297
Test name
Test status
Simulation time 352359538237 ps
CPU time 732.68 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 201460 kb
Host smart-e0006e7c-ffa1-475f-ab2a-3c872cbecf10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399117997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3399117997
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.468943758
Short name T381
Test name
Test status
Simulation time 193935694443 ps
CPU time 108.38 seconds
Started Aug 06 07:33:29 PM PDT 24
Finished Aug 06 07:35:17 PM PDT 24
Peak memory 201416 kb
Host smart-c805a6e2-7829-4a40-b12b-ce591e13fba9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468943758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.468943758
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4268652930
Short name T753
Test name
Test status
Simulation time 106316395741 ps
CPU time 530.12 seconds
Started Aug 06 07:33:29 PM PDT 24
Finished Aug 06 07:42:20 PM PDT 24
Peak memory 201844 kb
Host smart-e58d068e-7414-426b-84db-fa9fcaee2599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268652930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4268652930
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1326256091
Short name T774
Test name
Test status
Simulation time 25498937926 ps
CPU time 17.62 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:33:49 PM PDT 24
Peak memory 201348 kb
Host smart-3abd8256-6ebc-4780-9d39-3d56467ddb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326256091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1326256091
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4083972872
Short name T624
Test name
Test status
Simulation time 2709956334 ps
CPU time 2.41 seconds
Started Aug 06 07:33:28 PM PDT 24
Finished Aug 06 07:33:30 PM PDT 24
Peak memory 201288 kb
Host smart-4def9aa2-2eab-4038-89ce-34a3767d0e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083972872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4083972872
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.922973537
Short name T636
Test name
Test status
Simulation time 5723778783 ps
CPU time 14.24 seconds
Started Aug 06 07:33:16 PM PDT 24
Finished Aug 06 07:33:30 PM PDT 24
Peak memory 201388 kb
Host smart-f9e5c25f-a18a-4b51-8aba-2f5708317486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922973537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.922973537
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.120245423
Short name T723
Test name
Test status
Simulation time 172412166149 ps
CPU time 415.44 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:40:27 PM PDT 24
Peak memory 201444 kb
Host smart-5d7bd1f7-788f-4c23-ac40-93ffc890926a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120245423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
120245423
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1805883373
Short name T42
Test name
Test status
Simulation time 334971699623 ps
CPU time 131.38 seconds
Started Aug 06 07:33:33 PM PDT 24
Finished Aug 06 07:35:45 PM PDT 24
Peak memory 209804 kb
Host smart-3afbeb35-01c6-4c36-a2c6-06e933b2a3ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805883373 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1805883373
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3936474372
Short name T559
Test name
Test status
Simulation time 492034092 ps
CPU time 1.18 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:33:45 PM PDT 24
Peak memory 201184 kb
Host smart-302c4c5c-efb6-4461-8925-14116a8539ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936474372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3936474372
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2396247398
Short name T510
Test name
Test status
Simulation time 166355850669 ps
CPU time 89.96 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:35:00 PM PDT 24
Peak memory 201484 kb
Host smart-b9cf4977-8e07-4e64-b430-1bfc9b3cbadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396247398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2396247398
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1904482147
Short name T479
Test name
Test status
Simulation time 332471418633 ps
CPU time 211.43 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:37:01 PM PDT 24
Peak memory 201460 kb
Host smart-138cb9dd-7ded-4772-a87e-a181542de345
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904482147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1904482147
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2986287484
Short name T568
Test name
Test status
Simulation time 493298388160 ps
CPU time 1173.64 seconds
Started Aug 06 07:33:38 PM PDT 24
Finished Aug 06 07:53:12 PM PDT 24
Peak memory 201436 kb
Host smart-cf07c323-0633-4dc5-8f6c-b68d8a899ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986287484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2986287484
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2210083023
Short name T187
Test name
Test status
Simulation time 167039391943 ps
CPU time 100.77 seconds
Started Aug 06 07:33:30 PM PDT 24
Finished Aug 06 07:35:11 PM PDT 24
Peak memory 201372 kb
Host smart-61f1c71c-354b-43d3-a37d-967987993604
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210083023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2210083023
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3180777623
Short name T586
Test name
Test status
Simulation time 193656737313 ps
CPU time 98.71 seconds
Started Aug 06 07:33:31 PM PDT 24
Finished Aug 06 07:35:10 PM PDT 24
Peak memory 201500 kb
Host smart-eaca9942-4692-4ef2-b741-26b16e6c088f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180777623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3180777623
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1032771796
Short name T705
Test name
Test status
Simulation time 592229456009 ps
CPU time 371.05 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:39:56 PM PDT 24
Peak memory 201508 kb
Host smart-e710f041-edae-4601-b5ac-c77ffce19714
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032771796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1032771796
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.121579820
Short name T49
Test name
Test status
Simulation time 89205179087 ps
CPU time 481.07 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:41:45 PM PDT 24
Peak memory 201844 kb
Host smart-7cd36ca7-aeb1-4b8f-ac24-c54632ca5bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121579820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.121579820
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4141582133
Short name T451
Test name
Test status
Simulation time 37337615301 ps
CPU time 85.97 seconds
Started Aug 06 07:33:43 PM PDT 24
Finished Aug 06 07:35:09 PM PDT 24
Peak memory 201336 kb
Host smart-fd1edf19-69ed-40ec-96ff-ca3e21d8fbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141582133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4141582133
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2270493558
Short name T703
Test name
Test status
Simulation time 4312012049 ps
CPU time 3.01 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:33:47 PM PDT 24
Peak memory 201292 kb
Host smart-9bce6954-9a4a-45d5-b7ac-112eb5ff2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270493558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2270493558
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2872486614
Short name T582
Test name
Test status
Simulation time 5823411190 ps
CPU time 14.69 seconds
Started Aug 06 07:33:34 PM PDT 24
Finished Aug 06 07:33:49 PM PDT 24
Peak memory 201364 kb
Host smart-bfa54d8a-e266-45ab-857a-2dfdcef6429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872486614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2872486614
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1214844567
Short name T221
Test name
Test status
Simulation time 280492981871 ps
CPU time 526.74 seconds
Started Aug 06 07:33:45 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 210020 kb
Host smart-a02e7c6b-d9a1-41ce-8bc3-46abf37357da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214844567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1214844567
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.392252871
Short name T397
Test name
Test status
Simulation time 480791482 ps
CPU time 0.89 seconds
Started Aug 06 07:34:04 PM PDT 24
Finished Aug 06 07:34:05 PM PDT 24
Peak memory 201188 kb
Host smart-9a21becd-2620-4254-bdca-b282ab9527be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392252871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.392252871
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2393767264
Short name T272
Test name
Test status
Simulation time 167028080128 ps
CPU time 100.23 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:35:46 PM PDT 24
Peak memory 201376 kb
Host smart-ebc34249-46fc-48f8-b605-f5986969e261
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393767264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2393767264
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3155248793
Short name T158
Test name
Test status
Simulation time 545337235337 ps
CPU time 109.22 seconds
Started Aug 06 07:34:04 PM PDT 24
Finished Aug 06 07:35:53 PM PDT 24
Peak memory 201412 kb
Host smart-d496f6e4-0952-4b10-9e14-575fe5fd4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155248793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3155248793
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.176176447
Short name T571
Test name
Test status
Simulation time 326241724711 ps
CPU time 395.21 seconds
Started Aug 06 07:33:45 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 201432 kb
Host smart-f117d2ee-026c-43f4-9f5b-cd01c25bad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176176447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.176176447
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3492279729
Short name T522
Test name
Test status
Simulation time 334450505829 ps
CPU time 801.34 seconds
Started Aug 06 07:33:46 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 201492 kb
Host smart-0a2fe374-53f5-41d4-acc1-bfd4221ef883
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492279729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3492279729
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1901796601
Short name T137
Test name
Test status
Simulation time 320647272762 ps
CPU time 128.95 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:35:53 PM PDT 24
Peak memory 201408 kb
Host smart-b9fea73a-e58c-451c-8e16-c4675ac340d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901796601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1901796601
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1807163957
Short name T725
Test name
Test status
Simulation time 164389436232 ps
CPU time 353.3 seconds
Started Aug 06 07:33:46 PM PDT 24
Finished Aug 06 07:39:40 PM PDT 24
Peak memory 201424 kb
Host smart-f686615a-80ad-4ac7-9989-59bfc5a898c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807163957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1807163957
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2125246832
Short name T754
Test name
Test status
Simulation time 581455293646 ps
CPU time 1270.97 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:55:16 PM PDT 24
Peak memory 201424 kb
Host smart-bf88df15-0cea-4df6-82ae-6b515bbd6aff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125246832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2125246832
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1105709498
Short name T628
Test name
Test status
Simulation time 201546814817 ps
CPU time 75.17 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:35:20 PM PDT 24
Peak memory 201420 kb
Host smart-628d59f8-ce7a-4f64-bcc8-6600e96e15c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105709498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1105709498
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2404674706
Short name T445
Test name
Test status
Simulation time 73169012299 ps
CPU time 353.47 seconds
Started Aug 06 07:34:04 PM PDT 24
Finished Aug 06 07:39:58 PM PDT 24
Peak memory 201856 kb
Host smart-89c28e33-5043-4d31-a297-a8a1ed68dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404674706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2404674706
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2903841666
Short name T84
Test name
Test status
Simulation time 23751750174 ps
CPU time 14.23 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:34:19 PM PDT 24
Peak memory 201340 kb
Host smart-0bb41bc8-cf4e-4f2a-841a-08442e4f1109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903841666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2903841666
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1287653767
Short name T667
Test name
Test status
Simulation time 4287047286 ps
CPU time 10.04 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:34:15 PM PDT 24
Peak memory 201332 kb
Host smart-2732c942-5912-41af-a02c-166010d15191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287653767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1287653767
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3838792634
Short name T639
Test name
Test status
Simulation time 5940688560 ps
CPU time 14.84 seconds
Started Aug 06 07:33:44 PM PDT 24
Finished Aug 06 07:33:59 PM PDT 24
Peak memory 201404 kb
Host smart-3949cc64-9e3c-4e30-b3f6-e43717f6cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838792634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3838792634
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2355326278
Short name T34
Test name
Test status
Simulation time 6811021717 ps
CPU time 8.07 seconds
Started Aug 06 07:34:04 PM PDT 24
Finished Aug 06 07:34:12 PM PDT 24
Peak memory 201380 kb
Host smart-8140b08f-e65f-43cf-9076-df6d4381ef9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355326278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2355326278
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.988232314
Short name T301
Test name
Test status
Simulation time 40773943488 ps
CPU time 89.23 seconds
Started Aug 06 07:34:04 PM PDT 24
Finished Aug 06 07:35:33 PM PDT 24
Peak memory 211448 kb
Host smart-30072ce0-25bf-4ae4-a670-57db95eac66f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988232314 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.988232314
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2087911523
Short name T564
Test name
Test status
Simulation time 419288645 ps
CPU time 1.54 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:20 PM PDT 24
Peak memory 201268 kb
Host smart-f4322836-4b39-4d72-b771-a20d8719f916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087911523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2087911523
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2232153940
Short name T771
Test name
Test status
Simulation time 605165453362 ps
CPU time 591.58 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:42:11 PM PDT 24
Peak memory 201432 kb
Host smart-f1ab4f59-6a79-48cd-8fd6-e3cc8fa22b84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232153940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2232153940
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2548417274
Short name T2
Test name
Test status
Simulation time 325726161981 ps
CPU time 96.6 seconds
Started Aug 06 07:32:16 PM PDT 24
Finished Aug 06 07:33:53 PM PDT 24
Peak memory 201420 kb
Host smart-e5103ea6-c899-42d0-8854-f274238a23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548417274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2548417274
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.362329840
Short name T748
Test name
Test status
Simulation time 324350583056 ps
CPU time 677.37 seconds
Started Aug 06 07:32:16 PM PDT 24
Finished Aug 06 07:43:34 PM PDT 24
Peak memory 201424 kb
Host smart-11ca1414-72f9-4642-8635-6bb72d1e61a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=362329840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.362329840
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.378942782
Short name T460
Test name
Test status
Simulation time 331554830898 ps
CPU time 108.05 seconds
Started Aug 06 07:32:12 PM PDT 24
Finished Aug 06 07:34:00 PM PDT 24
Peak memory 201404 kb
Host smart-3009f2d6-8eff-48ad-9b24-0d35330f196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378942782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.378942782
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1425234458
Short name T595
Test name
Test status
Simulation time 508015977716 ps
CPU time 1182.35 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:52:02 PM PDT 24
Peak memory 201392 kb
Host smart-b155e764-ffd0-4587-bfb4-46a8f411f35e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425234458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1425234458
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4062206475
Short name T304
Test name
Test status
Simulation time 528499927824 ps
CPU time 316.72 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:37:36 PM PDT 24
Peak memory 201400 kb
Host smart-8e5bbfd6-5e87-4ba4-a82f-1a3875fd3da4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062206475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4062206475
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3579023713
Short name T700
Test name
Test status
Simulation time 198171931981 ps
CPU time 50.18 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:33:03 PM PDT 24
Peak memory 201464 kb
Host smart-aad3a498-c8c2-4eb3-9190-56a8778a0b6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579023713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3579023713
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2549246701
Short name T480
Test name
Test status
Simulation time 91187675724 ps
CPU time 302.75 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:37:22 PM PDT 24
Peak memory 201844 kb
Host smart-2868ff36-9ccf-475b-9b57-180c59b16948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549246701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2549246701
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2538375972
Short name T422
Test name
Test status
Simulation time 38720173085 ps
CPU time 96.18 seconds
Started Aug 06 07:32:14 PM PDT 24
Finished Aug 06 07:33:50 PM PDT 24
Peak memory 201296 kb
Host smart-00665034-55c0-42ea-8b20-d0ec1fe50dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538375972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2538375972
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1996044907
Short name T375
Test name
Test status
Simulation time 3444224759 ps
CPU time 4.55 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 201332 kb
Host smart-764717fa-09a5-430d-b6f2-d3e754346031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996044907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1996044907
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3923191842
Short name T78
Test name
Test status
Simulation time 3951350728 ps
CPU time 2.93 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:32:20 PM PDT 24
Peak memory 217072 kb
Host smart-6e366ec1-ecef-4ff5-a060-3ae7f25ff489
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923191842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3923191842
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2541396810
Short name T450
Test name
Test status
Simulation time 6096768426 ps
CPU time 14.53 seconds
Started Aug 06 07:32:17 PM PDT 24
Finished Aug 06 07:32:32 PM PDT 24
Peak memory 201336 kb
Host smart-d4a69f47-a7f2-4a2d-8310-ea20910c5afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541396810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2541396810
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3658829251
Short name T507
Test name
Test status
Simulation time 243951434799 ps
CPU time 116.73 seconds
Started Aug 06 07:32:14 PM PDT 24
Finished Aug 06 07:34:10 PM PDT 24
Peak memory 201412 kb
Host smart-025307dd-c2e6-4239-adaf-f84b8b8fa6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658829251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3658829251
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2646735083
Short name T170
Test name
Test status
Simulation time 139706071797 ps
CPU time 169.04 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:35:02 PM PDT 24
Peak memory 217624 kb
Host smart-53f4cc49-1535-4537-b95e-75fa311857b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646735083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2646735083
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.975718360
Short name T434
Test name
Test status
Simulation time 434226804 ps
CPU time 1.08 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:34:32 PM PDT 24
Peak memory 201252 kb
Host smart-a5759892-f62c-46d4-8914-aa6805f01443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975718360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.975718360
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3549536019
Short name T544
Test name
Test status
Simulation time 203614043700 ps
CPU time 242.85 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:38:09 PM PDT 24
Peak memory 201440 kb
Host smart-3ead52d1-c5a5-44bc-82ad-4c4d2a796b9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549536019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3549536019
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.344399018
Short name T536
Test name
Test status
Simulation time 491591067303 ps
CPU time 205.19 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:37:30 PM PDT 24
Peak memory 201388 kb
Host smart-762308ee-8cb5-44e9-ada0-9e7b74310f48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=344399018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.344399018
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1781002311
Short name T331
Test name
Test status
Simulation time 482352413240 ps
CPU time 1082.62 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:52:08 PM PDT 24
Peak memory 201444 kb
Host smart-6473097b-c049-4ade-9624-bc51da6c1388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781002311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1781002311
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1012876674
Short name T186
Test name
Test status
Simulation time 326696328946 ps
CPU time 362.11 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:40:07 PM PDT 24
Peak memory 201448 kb
Host smart-84ff16ac-a1ec-4257-a1d4-d820ccd10ce0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012876674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1012876674
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3798695641
Short name T288
Test name
Test status
Simulation time 575324448053 ps
CPU time 660.43 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:45:06 PM PDT 24
Peak memory 201420 kb
Host smart-cf41bcad-a60f-4ce5-b3a9-d044fff73150
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798695641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3798695641
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3293315147
Short name T549
Test name
Test status
Simulation time 186173247422 ps
CPU time 217.98 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:37:44 PM PDT 24
Peak memory 201428 kb
Host smart-082851ac-fc77-4d92-b205-117bd7360763
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293315147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3293315147
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1703379220
Short name T358
Test name
Test status
Simulation time 107014904416 ps
CPU time 383.86 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:40:30 PM PDT 24
Peak memory 201796 kb
Host smart-2e8d4847-b698-4f99-8aa9-8bea6edeb375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703379220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1703379220
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.974343814
Short name T656
Test name
Test status
Simulation time 31331343091 ps
CPU time 4.35 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:34:10 PM PDT 24
Peak memory 201312 kb
Host smart-8008fcfd-5768-4e22-a9ae-f5e3666ba641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974343814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.974343814
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2080067827
Short name T631
Test name
Test status
Simulation time 5677252882 ps
CPU time 4.04 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:34:09 PM PDT 24
Peak memory 201376 kb
Host smart-bc0ebd38-6497-45b1-98fa-9618e7cd0b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080067827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2080067827
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4220670586
Short name T393
Test name
Test status
Simulation time 5638664677 ps
CPU time 1.62 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:34:08 PM PDT 24
Peak memory 201336 kb
Host smart-dd859077-45fc-4ad3-ba1e-2c018bc72ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220670586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4220670586
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1727037708
Short name T694
Test name
Test status
Simulation time 6719054026 ps
CPU time 15.35 seconds
Started Aug 06 07:34:05 PM PDT 24
Finished Aug 06 07:34:21 PM PDT 24
Peak memory 201304 kb
Host smart-662fc006-8a4f-4e70-8441-5d962c5feb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727037708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1727037708
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4037184023
Short name T724
Test name
Test status
Simulation time 87232488195 ps
CPU time 40.62 seconds
Started Aug 06 07:34:06 PM PDT 24
Finished Aug 06 07:34:47 PM PDT 24
Peak memory 217848 kb
Host smart-b4b8d0b1-5417-49e1-9321-757d39e428e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037184023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4037184023
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.673240793
Short name T436
Test name
Test status
Simulation time 366282794 ps
CPU time 1.46 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 07:34:38 PM PDT 24
Peak memory 201188 kb
Host smart-89ceb1b1-007a-4c31-b004-d956e65cbc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673240793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.673240793
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2185423984
Short name T153
Test name
Test status
Simulation time 184819492184 ps
CPU time 222.26 seconds
Started Aug 06 07:34:33 PM PDT 24
Finished Aug 06 07:38:16 PM PDT 24
Peak memory 201412 kb
Host smart-1785eba5-7631-4832-8e44-e57d73278905
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185423984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2185423984
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3160480002
Short name T671
Test name
Test status
Simulation time 291725900760 ps
CPU time 336.16 seconds
Started Aug 06 07:34:32 PM PDT 24
Finished Aug 06 07:40:08 PM PDT 24
Peak memory 201508 kb
Host smart-6e9f2825-62bf-410e-b45c-d725036d932b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160480002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3160480002
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.179644325
Short name T96
Test name
Test status
Simulation time 164594319733 ps
CPU time 101.82 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 07:36:17 PM PDT 24
Peak memory 201680 kb
Host smart-7396dead-f57a-43e5-8e15-0ffb97810c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179644325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.179644325
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2135419525
Short name T602
Test name
Test status
Simulation time 495158241275 ps
CPU time 782.54 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:47:32 PM PDT 24
Peak memory 201472 kb
Host smart-ebb85c97-c6aa-44c9-a2fe-5448d1793400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135419525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2135419525
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3615646531
Short name T512
Test name
Test status
Simulation time 165453841722 ps
CPU time 94.96 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 07:36:11 PM PDT 24
Peak memory 201444 kb
Host smart-e229bf98-640d-4a5f-ad85-13e5d963d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615646531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3615646531
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2608456124
Short name T661
Test name
Test status
Simulation time 160239075148 ps
CPU time 110.9 seconds
Started Aug 06 07:34:37 PM PDT 24
Finished Aug 06 07:36:28 PM PDT 24
Peak memory 201440 kb
Host smart-c57b1346-e636-4dde-81df-f529b17a8093
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608456124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2608456124
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.983816203
Short name T319
Test name
Test status
Simulation time 172549389661 ps
CPU time 32.52 seconds
Started Aug 06 07:34:29 PM PDT 24
Finished Aug 06 07:35:02 PM PDT 24
Peak memory 201440 kb
Host smart-2209af9a-f0eb-41fc-be95-a67701dbda1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983816203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.983816203
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2553149673
Short name T400
Test name
Test status
Simulation time 608856352264 ps
CPU time 1288.26 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 07:56:05 PM PDT 24
Peak memory 201388 kb
Host smart-49ae066e-caf2-4900-b94f-ece84de3354a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553149673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2553149673
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.856176744
Short name T211
Test name
Test status
Simulation time 107183421090 ps
CPU time 425.23 seconds
Started Aug 06 07:34:32 PM PDT 24
Finished Aug 06 07:41:37 PM PDT 24
Peak memory 201844 kb
Host smart-390b380f-018b-4f56-90ae-3254ac5b1db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856176744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.856176744
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.435611807
Short name T444
Test name
Test status
Simulation time 22641410656 ps
CPU time 28.77 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:34:59 PM PDT 24
Peak memory 201276 kb
Host smart-f67a1914-9229-45a7-b1e2-7ff6ce865741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435611807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.435611807
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2208303920
Short name T463
Test name
Test status
Simulation time 3786359716 ps
CPU time 9.95 seconds
Started Aug 06 07:34:31 PM PDT 24
Finished Aug 06 07:34:41 PM PDT 24
Peak memory 201312 kb
Host smart-1af4c02b-7e27-4d08-8032-7d5f84be2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208303920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2208303920
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.157125680
Short name T428
Test name
Test status
Simulation time 5621929680 ps
CPU time 7.51 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 07:34:43 PM PDT 24
Peak memory 201536 kb
Host smart-14bc8354-ec88-4eec-ac92-7589c72d8b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157125680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.157125680
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1904559410
Short name T329
Test name
Test status
Simulation time 969273928549 ps
CPU time 2424.41 seconds
Started Aug 06 07:34:36 PM PDT 24
Finished Aug 06 08:15:01 PM PDT 24
Peak memory 210248 kb
Host smart-7968cb36-acb6-4445-9705-544256df42e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904559410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1904559410
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2984261393
Short name T93
Test name
Test status
Simulation time 46913679319 ps
CPU time 90.63 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:36:01 PM PDT 24
Peak memory 209796 kb
Host smart-b2f1ea0e-8977-45a8-9ef4-3be84b3ce0be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984261393 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2984261393
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4145539085
Short name T73
Test name
Test status
Simulation time 472253887 ps
CPU time 0.82 seconds
Started Aug 06 07:34:31 PM PDT 24
Finished Aug 06 07:34:32 PM PDT 24
Peak memory 201232 kb
Host smart-29b91379-95a9-4861-b2b0-6abcdb4ef3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145539085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4145539085
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.70252508
Short name T734
Test name
Test status
Simulation time 162010137798 ps
CPU time 191.37 seconds
Started Aug 06 07:34:31 PM PDT 24
Finished Aug 06 07:37:42 PM PDT 24
Peak memory 201452 kb
Host smart-660f22f3-61e8-491e-9ece-5878c86963c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70252508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gatin
g.70252508
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3047245380
Short name T197
Test name
Test status
Simulation time 336628721035 ps
CPU time 216.78 seconds
Started Aug 06 07:34:32 PM PDT 24
Finished Aug 06 07:38:09 PM PDT 24
Peak memory 201464 kb
Host smart-4b59d45c-4554-4252-8177-2a7fff25b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047245380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3047245380
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3198650486
Short name T475
Test name
Test status
Simulation time 162418364238 ps
CPU time 357.66 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:40:27 PM PDT 24
Peak memory 201480 kb
Host smart-d705026f-809d-449b-a0b7-049be6db317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198650486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3198650486
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2725211020
Short name T474
Test name
Test status
Simulation time 331047164631 ps
CPU time 190.47 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:37:41 PM PDT 24
Peak memory 201456 kb
Host smart-8cc55cde-3da4-448d-aa3c-df0d9bbe80cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725211020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2725211020
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.613971784
Short name T516
Test name
Test status
Simulation time 491533192422 ps
CPU time 199.18 seconds
Started Aug 06 07:34:37 PM PDT 24
Finished Aug 06 07:37:57 PM PDT 24
Peak memory 201424 kb
Host smart-330dc8fd-7b7a-4285-846a-a3c5120e7066
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=613971784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.613971784
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4241687462
Short name T750
Test name
Test status
Simulation time 370315409220 ps
CPU time 448.96 seconds
Started Aug 06 07:34:35 PM PDT 24
Finished Aug 06 07:42:04 PM PDT 24
Peak memory 201448 kb
Host smart-c16231dd-ff42-4c4d-b113-f0eb0f7e9027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241687462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4241687462
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3973705282
Short name T503
Test name
Test status
Simulation time 600022385333 ps
CPU time 291.89 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:39:22 PM PDT 24
Peak memory 201404 kb
Host smart-2a6c7cec-e1e8-4ff9-b3b3-28cc9d3a3099
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973705282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3973705282
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3474395970
Short name T218
Test name
Test status
Simulation time 104509885117 ps
CPU time 472.73 seconds
Started Aug 06 07:34:34 PM PDT 24
Finished Aug 06 07:42:27 PM PDT 24
Peak memory 201844 kb
Host smart-5563510b-0e66-45c0-8074-d0b2714c57a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474395970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3474395970
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2764219599
Short name T382
Test name
Test status
Simulation time 24038544929 ps
CPU time 53.98 seconds
Started Aug 06 07:34:29 PM PDT 24
Finished Aug 06 07:35:23 PM PDT 24
Peak memory 201340 kb
Host smart-5b4e153e-2410-4a7a-aef6-885a7176c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764219599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2764219599
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.4187882610
Short name T652
Test name
Test status
Simulation time 4932529803 ps
CPU time 12.13 seconds
Started Aug 06 07:34:29 PM PDT 24
Finished Aug 06 07:34:41 PM PDT 24
Peak memory 201348 kb
Host smart-8f35ff4a-ee33-4401-9694-a40edc86eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187882610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4187882610
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.660327489
Short name T567
Test name
Test status
Simulation time 5703037052 ps
CPU time 13.85 seconds
Started Aug 06 07:34:32 PM PDT 24
Finished Aug 06 07:34:46 PM PDT 24
Peak memory 201364 kb
Host smart-f4e62613-b5d6-4680-ae45-e55541e66f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660327489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.660327489
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3677214725
Short name T347
Test name
Test status
Simulation time 727653624763 ps
CPU time 1946.31 seconds
Started Aug 06 07:34:33 PM PDT 24
Finished Aug 06 08:07:00 PM PDT 24
Peak memory 209932 kb
Host smart-f6c97365-d718-4205-b1a9-8b45545f3a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677214725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3677214725
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4248804609
Short name T344
Test name
Test status
Simulation time 802438615892 ps
CPU time 141.13 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:36:51 PM PDT 24
Peak memory 209828 kb
Host smart-f35815bb-fe22-4fcb-9116-62647db8e37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248804609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4248804609
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2450758570
Short name T598
Test name
Test status
Simulation time 443201456 ps
CPU time 0.88 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:34:48 PM PDT 24
Peak memory 201200 kb
Host smart-297f55a6-b809-48b3-8b17-0702214bfeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450758570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2450758570
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.24926648
Short name T256
Test name
Test status
Simulation time 181926658266 ps
CPU time 425.25 seconds
Started Aug 06 07:34:46 PM PDT 24
Finished Aug 06 07:41:51 PM PDT 24
Peak memory 201408 kb
Host smart-a54d1a2a-ab48-4f9a-a547-ae912afdf1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24926648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.24926648
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.4013059913
Short name T277
Test name
Test status
Simulation time 495311075239 ps
CPU time 1094.74 seconds
Started Aug 06 07:34:29 PM PDT 24
Finished Aug 06 07:52:44 PM PDT 24
Peak memory 201404 kb
Host smart-7e24b5f7-24a5-4da0-956b-74cdcd20585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013059913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4013059913
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2762006007
Short name T260
Test name
Test status
Simulation time 163754974004 ps
CPU time 197.72 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:38:05 PM PDT 24
Peak memory 201444 kb
Host smart-305cedc7-c988-45b6-8ce6-b3c37a03f6ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762006007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2762006007
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.888715391
Short name T156
Test name
Test status
Simulation time 330145277476 ps
CPU time 345.4 seconds
Started Aug 06 07:34:38 PM PDT 24
Finished Aug 06 07:40:23 PM PDT 24
Peak memory 201492 kb
Host smart-331d4303-ff8c-4c74-83ca-f3a44c7d2b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888715391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.888715391
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2291655695
Short name T448
Test name
Test status
Simulation time 324642706142 ps
CPU time 188.36 seconds
Started Aug 06 07:34:30 PM PDT 24
Finished Aug 06 07:37:39 PM PDT 24
Peak memory 201496 kb
Host smart-6c8e493d-1d60-4c9a-bc57-065fccd79960
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291655695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2291655695
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3095355495
Short name T231
Test name
Test status
Simulation time 172498156621 ps
CPU time 168.79 seconds
Started Aug 06 07:34:50 PM PDT 24
Finished Aug 06 07:37:39 PM PDT 24
Peak memory 201348 kb
Host smart-cf60497b-245d-4543-89b5-f0ef683a55bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095355495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3095355495
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.526509858
Short name T696
Test name
Test status
Simulation time 604624361424 ps
CPU time 352.28 seconds
Started Aug 06 07:34:46 PM PDT 24
Finished Aug 06 07:40:38 PM PDT 24
Peak memory 201408 kb
Host smart-eecb9554-33c4-4fd5-857f-ebe786717f95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526509858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.526509858
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.387672206
Short name T195
Test name
Test status
Simulation time 82951484102 ps
CPU time 320 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:40:07 PM PDT 24
Peak memory 201848 kb
Host smart-2e50d483-e54e-4e59-8cbf-464a9fc908ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387672206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.387672206
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1448155085
Short name T8
Test name
Test status
Simulation time 34393858374 ps
CPU time 20.58 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:35:07 PM PDT 24
Peak memory 201376 kb
Host smart-b9cafc14-b295-4310-9b8a-67a868b8c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448155085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1448155085
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2227587655
Short name T91
Test name
Test status
Simulation time 4509558865 ps
CPU time 3.22 seconds
Started Aug 06 07:34:52 PM PDT 24
Finished Aug 06 07:34:56 PM PDT 24
Peak memory 201332 kb
Host smart-930e034e-b877-4c50-b422-7e01dd866540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227587655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2227587655
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4233516142
Short name T83
Test name
Test status
Simulation time 5586194944 ps
CPU time 13.05 seconds
Started Aug 06 07:34:35 PM PDT 24
Finished Aug 06 07:34:48 PM PDT 24
Peak memory 201360 kb
Host smart-536a250f-4686-4a90-9981-c2cadf582fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233516142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4233516142
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3718015395
Short name T258
Test name
Test status
Simulation time 352575677984 ps
CPU time 673.91 seconds
Started Aug 06 07:34:49 PM PDT 24
Finished Aug 06 07:46:03 PM PDT 24
Peak memory 201416 kb
Host smart-12d27721-b721-4898-a5f3-fa1f4620f27e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718015395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3718015395
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1647936705
Short name T325
Test name
Test status
Simulation time 45338105397 ps
CPU time 102.16 seconds
Started Aug 06 07:34:53 PM PDT 24
Finished Aug 06 07:36:35 PM PDT 24
Peak memory 209860 kb
Host smart-76c371f8-ec4a-48a7-a938-57805ec3cfe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647936705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1647936705
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2700945065
Short name T432
Test name
Test status
Simulation time 457611364 ps
CPU time 1.13 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:35:06 PM PDT 24
Peak memory 201220 kb
Host smart-427423e6-edb3-42d2-8584-4942646a1bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700945065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2700945065
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2816878320
Short name T234
Test name
Test status
Simulation time 173467735075 ps
CPU time 191.44 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:37:58 PM PDT 24
Peak memory 201400 kb
Host smart-a525941d-1c92-4db8-84cf-c14f70c1e2bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816878320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2816878320
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2746256003
Short name T738
Test name
Test status
Simulation time 330144268626 ps
CPU time 513.2 seconds
Started Aug 06 07:34:53 PM PDT 24
Finished Aug 06 07:43:26 PM PDT 24
Peak memory 201456 kb
Host smart-a68da5b0-b0b9-4d0a-97d3-32c435a2430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746256003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2746256003
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1410915140
Short name T391
Test name
Test status
Simulation time 487498645864 ps
CPU time 1050.35 seconds
Started Aug 06 07:34:46 PM PDT 24
Finished Aug 06 07:52:17 PM PDT 24
Peak memory 201404 kb
Host smart-0c7b880d-7795-4de1-bf4b-47fc5c8b1306
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410915140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1410915140
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3413612857
Short name T299
Test name
Test status
Simulation time 490805315453 ps
CPU time 553.55 seconds
Started Aug 06 07:34:52 PM PDT 24
Finished Aug 06 07:44:05 PM PDT 24
Peak memory 201388 kb
Host smart-a0053117-a6fd-484a-8b14-8742823ba3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413612857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3413612857
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1409955898
Short name T373
Test name
Test status
Simulation time 166645942185 ps
CPU time 181.77 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:37:49 PM PDT 24
Peak memory 201412 kb
Host smart-edb77724-db41-434a-88a6-c3db09f2af39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409955898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1409955898
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3124980252
Short name T353
Test name
Test status
Simulation time 166516360069 ps
CPU time 102.79 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:36:30 PM PDT 24
Peak memory 201452 kb
Host smart-fd014d84-5f40-4002-9a28-b10d6daa369b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124980252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3124980252
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.612467540
Short name T614
Test name
Test status
Simulation time 599738788654 ps
CPU time 73.06 seconds
Started Aug 06 07:34:47 PM PDT 24
Finished Aug 06 07:36:00 PM PDT 24
Peak memory 201464 kb
Host smart-d6ce7910-a2ea-4031-b00d-16c2caed9122
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612467540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.612467540
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2596091364
Short name T777
Test name
Test status
Simulation time 101678000832 ps
CPU time 404.33 seconds
Started Aug 06 07:35:11 PM PDT 24
Finished Aug 06 07:41:55 PM PDT 24
Peak memory 201832 kb
Host smart-007701db-c0f1-4cbe-b01b-39a78ecad6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596091364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2596091364
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2804900588
Short name T427
Test name
Test status
Simulation time 33942968825 ps
CPU time 7.71 seconds
Started Aug 06 07:35:07 PM PDT 24
Finished Aug 06 07:35:14 PM PDT 24
Peak memory 201360 kb
Host smart-cdbf5eb6-81c3-4742-9843-08e0abd8eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804900588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2804900588
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3810547214
Short name T761
Test name
Test status
Simulation time 5734591814 ps
CPU time 13.64 seconds
Started Aug 06 07:34:46 PM PDT 24
Finished Aug 06 07:35:00 PM PDT 24
Peak memory 201396 kb
Host smart-c1ecbdbb-af15-4cf2-ba8e-9588ddfbdd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810547214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3810547214
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1317503635
Short name T658
Test name
Test status
Simulation time 5753934220 ps
CPU time 13.26 seconds
Started Aug 06 07:34:46 PM PDT 24
Finished Aug 06 07:34:59 PM PDT 24
Peak memory 201352 kb
Host smart-4bcfaa4c-4f90-4642-a384-6b563b167e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317503635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1317503635
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.821929605
Short name T701
Test name
Test status
Simulation time 375902718866 ps
CPU time 412.67 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:41:58 PM PDT 24
Peak memory 201412 kb
Host smart-c97aa3d5-7056-45a4-8537-5cbe2ddfb18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821929605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
821929605
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3439827370
Short name T37
Test name
Test status
Simulation time 262415305025 ps
CPU time 177.05 seconds
Started Aug 06 07:35:07 PM PDT 24
Finished Aug 06 07:38:04 PM PDT 24
Peak memory 210056 kb
Host smart-d442de5c-dc91-4996-a0a2-4b760d2c881a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439827370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3439827370
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2567888572
Short name T371
Test name
Test status
Simulation time 388178879 ps
CPU time 1.49 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:35:06 PM PDT 24
Peak memory 201260 kb
Host smart-0b7270d5-2844-4a74-b6ae-150247c73394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567888572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2567888572
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.200401063
Short name T188
Test name
Test status
Simulation time 648681684615 ps
CPU time 50.8 seconds
Started Aug 06 07:35:06 PM PDT 24
Finished Aug 06 07:35:57 PM PDT 24
Peak memory 201392 kb
Host smart-248c49de-309b-41ad-9ee3-c48888db1249
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200401063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.200401063
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1409295243
Short name T558
Test name
Test status
Simulation time 329479227557 ps
CPU time 690.58 seconds
Started Aug 06 07:35:10 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 201444 kb
Host smart-4a7f1129-462f-4564-abd5-df28b7cfb846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409295243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1409295243
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.205657692
Short name T352
Test name
Test status
Simulation time 502445033392 ps
CPU time 1134.8 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:54:00 PM PDT 24
Peak memory 201428 kb
Host smart-7b0726f5-a5bd-45b6-969f-8240f0ef69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205657692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.205657692
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2504109227
Short name T447
Test name
Test status
Simulation time 494720907187 ps
CPU time 210.92 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:38:36 PM PDT 24
Peak memory 201436 kb
Host smart-f6ec4cc4-ec39-4803-8960-dcd6600b8cdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504109227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2504109227
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.211176685
Short name T412
Test name
Test status
Simulation time 478970089734 ps
CPU time 1050.89 seconds
Started Aug 06 07:35:08 PM PDT 24
Finished Aug 06 07:52:39 PM PDT 24
Peak memory 201508 kb
Host smart-ff16be88-fb91-480f-91bc-4cbebafea542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211176685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.211176685
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1233784364
Short name T419
Test name
Test status
Simulation time 327186576519 ps
CPU time 188.11 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:38:13 PM PDT 24
Peak memory 201416 kb
Host smart-359dedf5-98c4-4dce-bb64-a42e2507217a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233784364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1233784364
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3022233854
Short name T739
Test name
Test status
Simulation time 546005192944 ps
CPU time 1217.72 seconds
Started Aug 06 07:35:06 PM PDT 24
Finished Aug 06 07:55:23 PM PDT 24
Peak memory 201392 kb
Host smart-6a85713f-6c49-41f9-8529-14982cdebe38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022233854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3022233854
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1830809652
Short name T630
Test name
Test status
Simulation time 195172852166 ps
CPU time 103.29 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:36:49 PM PDT 24
Peak memory 201424 kb
Host smart-cb5daf60-af89-4b93-ae13-46d4108e726b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830809652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1830809652
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3489386776
Short name T590
Test name
Test status
Simulation time 68491552854 ps
CPU time 211.5 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:38:37 PM PDT 24
Peak memory 201744 kb
Host smart-5e80f230-627d-4dd0-82c5-896177eb0fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489386776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3489386776
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.514104355
Short name T369
Test name
Test status
Simulation time 29241824032 ps
CPU time 33.17 seconds
Started Aug 06 07:35:06 PM PDT 24
Finished Aug 06 07:35:39 PM PDT 24
Peak memory 201352 kb
Host smart-aa9cf396-3919-449d-a144-4aef83a8dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514104355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.514104355
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3228991332
Short name T489
Test name
Test status
Simulation time 3065046971 ps
CPU time 4.05 seconds
Started Aug 06 07:35:08 PM PDT 24
Finished Aug 06 07:35:12 PM PDT 24
Peak memory 201328 kb
Host smart-4c5d3594-3a56-48b5-a9ce-a799c9ca2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228991332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3228991332
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2070488884
Short name T362
Test name
Test status
Simulation time 6093034250 ps
CPU time 8.3 seconds
Started Aug 06 07:35:07 PM PDT 24
Finished Aug 06 07:35:15 PM PDT 24
Peak memory 201356 kb
Host smart-feaf6086-0fc8-4339-9842-2758d1bf5dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070488884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2070488884
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4238686951
Short name T787
Test name
Test status
Simulation time 331719120366 ps
CPU time 137.38 seconds
Started Aug 06 07:35:07 PM PDT 24
Finished Aug 06 07:37:24 PM PDT 24
Peak memory 201404 kb
Host smart-81f98da9-b760-407f-afdf-53c6b9bddc18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238686951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4238686951
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.241789756
Short name T497
Test name
Test status
Simulation time 27238503498 ps
CPU time 55.16 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:36:00 PM PDT 24
Peak memory 209796 kb
Host smart-8687c8fb-d4f5-475d-a799-92df8ea1a7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241789756 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.241789756
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1557696347
Short name T383
Test name
Test status
Simulation time 419664811 ps
CPU time 0.85 seconds
Started Aug 06 07:35:23 PM PDT 24
Finished Aug 06 07:35:24 PM PDT 24
Peak memory 201188 kb
Host smart-9453ea31-04c6-409f-b931-064a928dce6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557696347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1557696347
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3900263832
Short name T270
Test name
Test status
Simulation time 417409633053 ps
CPU time 388.39 seconds
Started Aug 06 07:35:21 PM PDT 24
Finished Aug 06 07:41:50 PM PDT 24
Peak memory 201448 kb
Host smart-fafc7401-f910-4b81-852e-3578db74ffed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900263832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3900263832
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2381373751
Short name T682
Test name
Test status
Simulation time 487066450013 ps
CPU time 1084.07 seconds
Started Aug 06 07:35:22 PM PDT 24
Finished Aug 06 07:53:26 PM PDT 24
Peak memory 201420 kb
Host smart-11107639-d4e7-4727-8e4e-d84ed9deecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381373751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2381373751
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1337311264
Short name T505
Test name
Test status
Simulation time 486018069549 ps
CPU time 519.51 seconds
Started Aug 06 07:35:22 PM PDT 24
Finished Aug 06 07:44:01 PM PDT 24
Peak memory 201476 kb
Host smart-eef6ae23-f539-4b8c-9e88-d79d06bfcb52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337311264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1337311264
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1557731311
Short name T744
Test name
Test status
Simulation time 327779064832 ps
CPU time 738.14 seconds
Started Aug 06 07:35:05 PM PDT 24
Finished Aug 06 07:47:23 PM PDT 24
Peak memory 201404 kb
Host smart-0b2dc667-52cd-4809-9b63-21e3c1786099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557731311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1557731311
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2422543243
Short name T472
Test name
Test status
Simulation time 164651480324 ps
CPU time 94.17 seconds
Started Aug 06 07:35:20 PM PDT 24
Finished Aug 06 07:36:54 PM PDT 24
Peak memory 201356 kb
Host smart-9d0fc61a-ca37-4ca6-92b7-8e0229764669
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422543243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2422543243
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.692635014
Short name T47
Test name
Test status
Simulation time 376537076488 ps
CPU time 874.35 seconds
Started Aug 06 07:35:23 PM PDT 24
Finished Aug 06 07:49:57 PM PDT 24
Peak memory 201460 kb
Host smart-a4ed512a-d483-45fe-ad4c-c5741b188991
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692635014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.692635014
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2583245550
Short name T406
Test name
Test status
Simulation time 195384832723 ps
CPU time 419.43 seconds
Started Aug 06 07:35:24 PM PDT 24
Finished Aug 06 07:42:23 PM PDT 24
Peak memory 201428 kb
Host smart-af0e8ce2-d7c5-484b-bbd7-5c2d5f203b28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583245550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2583245550
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2904772146
Short name T53
Test name
Test status
Simulation time 98960421295 ps
CPU time 343.87 seconds
Started Aug 06 07:35:20 PM PDT 24
Finished Aug 06 07:41:04 PM PDT 24
Peak memory 201856 kb
Host smart-4dddafbb-c3f8-477a-a37b-728c169455d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904772146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2904772146
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2398545229
Short name T643
Test name
Test status
Simulation time 34078588720 ps
CPU time 5.73 seconds
Started Aug 06 07:35:25 PM PDT 24
Finished Aug 06 07:35:31 PM PDT 24
Peak memory 201304 kb
Host smart-80a36d37-7697-44e4-b47f-83badc01cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398545229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2398545229
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3045423123
Short name T525
Test name
Test status
Simulation time 3956488161 ps
CPU time 10.11 seconds
Started Aug 06 07:35:21 PM PDT 24
Finished Aug 06 07:35:31 PM PDT 24
Peak memory 201356 kb
Host smart-ebd2fae8-bada-468d-9a13-64774771376b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045423123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3045423123
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1172786028
Short name T547
Test name
Test status
Simulation time 5686343990 ps
CPU time 5.31 seconds
Started Aug 06 07:35:08 PM PDT 24
Finished Aug 06 07:35:13 PM PDT 24
Peak memory 201380 kb
Host smart-6503b20f-1f5f-4d90-ac4b-e82932c5a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172786028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1172786028
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1047010668
Short name T334
Test name
Test status
Simulation time 196609120041 ps
CPU time 208.86 seconds
Started Aug 06 07:35:22 PM PDT 24
Finished Aug 06 07:38:51 PM PDT 24
Peak memory 210104 kb
Host smart-af16f6fb-56de-460b-973d-6491c367628d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047010668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1047010668
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.499566534
Short name T695
Test name
Test status
Simulation time 451440067 ps
CPU time 0.82 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:35:39 PM PDT 24
Peak memory 201240 kb
Host smart-8b4f6c81-f1fc-4a3a-9b46-72dd5f2303bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499566534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.499566534
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2880524248
Short name T711
Test name
Test status
Simulation time 532329063648 ps
CPU time 1131.58 seconds
Started Aug 06 07:35:39 PM PDT 24
Finished Aug 06 07:54:31 PM PDT 24
Peak memory 201484 kb
Host smart-c9c1600f-532a-4291-9b14-cc44e6411b7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880524248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2880524248
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1797461569
Short name T306
Test name
Test status
Simulation time 184741082892 ps
CPU time 115.02 seconds
Started Aug 06 07:35:37 PM PDT 24
Finished Aug 06 07:37:32 PM PDT 24
Peak memory 201516 kb
Host smart-8c4d998b-32a3-4989-b4f6-2ab5fa34d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797461569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1797461569
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.622644110
Short name T191
Test name
Test status
Simulation time 163681581215 ps
CPU time 335.56 seconds
Started Aug 06 07:35:23 PM PDT 24
Finished Aug 06 07:40:59 PM PDT 24
Peak memory 201464 kb
Host smart-7abacf07-d64a-4cae-9cac-05472dafcefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622644110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.622644110
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.51700932
Short name T783
Test name
Test status
Simulation time 166136872447 ps
CPU time 66.55 seconds
Started Aug 06 07:35:22 PM PDT 24
Finished Aug 06 07:36:28 PM PDT 24
Peak memory 201384 kb
Host smart-0c3fd7fc-45b0-43d8-8b14-ea50528f648d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=51700932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt
_fixed.51700932
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.287070077
Short name T173
Test name
Test status
Simulation time 491666465476 ps
CPU time 537.42 seconds
Started Aug 06 07:35:21 PM PDT 24
Finished Aug 06 07:44:19 PM PDT 24
Peak memory 201464 kb
Host smart-f4c3eba4-a910-4a6a-9f6a-4d278257c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287070077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.287070077
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4186938251
Short name T500
Test name
Test status
Simulation time 168769661746 ps
CPU time 376.47 seconds
Started Aug 06 07:35:22 PM PDT 24
Finished Aug 06 07:41:39 PM PDT 24
Peak memory 201400 kb
Host smart-a7ad4863-37e4-4d5c-be49-c410662ab4b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186938251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4186938251
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3439059797
Short name T402
Test name
Test status
Simulation time 190981215349 ps
CPU time 428.47 seconds
Started Aug 06 07:35:23 PM PDT 24
Finished Aug 06 07:42:32 PM PDT 24
Peak memory 201376 kb
Host smart-8930bb3e-d151-4d0e-809c-bbfbdc99d1a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439059797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3439059797
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3622987055
Short name T7
Test name
Test status
Simulation time 111172276560 ps
CPU time 409.48 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:42:30 PM PDT 24
Peak memory 201736 kb
Host smart-f1897c11-9e52-4052-8000-88edbd8d8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622987055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3622987055
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3411196161
Short name T534
Test name
Test status
Simulation time 26097207062 ps
CPU time 61.73 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:36:40 PM PDT 24
Peak memory 201332 kb
Host smart-02aff977-54ec-4de4-b82b-2ebf2922700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411196161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3411196161
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.78005437
Short name T633
Test name
Test status
Simulation time 4756091305 ps
CPU time 10.92 seconds
Started Aug 06 07:35:39 PM PDT 24
Finished Aug 06 07:35:50 PM PDT 24
Peak memory 201312 kb
Host smart-3856fb29-6c49-4b6f-9f74-9e4cb3626e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78005437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.78005437
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1587564599
Short name T608
Test name
Test status
Simulation time 5998090519 ps
CPU time 4.94 seconds
Started Aug 06 07:35:24 PM PDT 24
Finished Aug 06 07:35:29 PM PDT 24
Peak memory 201408 kb
Host smart-fc4f2072-9dab-45cd-be23-8807906f1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587564599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1587564599
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.778183309
Short name T312
Test name
Test status
Simulation time 647431479519 ps
CPU time 367.23 seconds
Started Aug 06 07:35:37 PM PDT 24
Finished Aug 06 07:41:45 PM PDT 24
Peak memory 201384 kb
Host smart-d92e63f1-883d-479c-9fe8-034c5e7021e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778183309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
778183309
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.683358803
Short name T395
Test name
Test status
Simulation time 504257833 ps
CPU time 1.23 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:35:39 PM PDT 24
Peak memory 201260 kb
Host smart-55571d4a-949a-43e5-b642-f65dfa6b35ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683358803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.683358803
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3893764053
Short name T160
Test name
Test status
Simulation time 325926324607 ps
CPU time 206.26 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:39:07 PM PDT 24
Peak memory 201672 kb
Host smart-2a727574-4e2b-4696-b62d-7b4e519d09b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893764053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3893764053
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2375436767
Short name T742
Test name
Test status
Simulation time 322296757599 ps
CPU time 165.97 seconds
Started Aug 06 07:35:40 PM PDT 24
Finished Aug 06 07:38:26 PM PDT 24
Peak memory 201404 kb
Host smart-6808f532-82c6-4e64-bfbf-ca4abe439b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375436767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2375436767
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3667830612
Short name T180
Test name
Test status
Simulation time 328459544670 ps
CPU time 383.79 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:42:05 PM PDT 24
Peak memory 201360 kb
Host smart-609afb63-001d-4306-8f57-f8153ae5fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667830612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3667830612
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2782361461
Short name T275
Test name
Test status
Simulation time 315889567576 ps
CPU time 716.53 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 201396 kb
Host smart-c5cf8aed-1bdb-4743-ab19-bd4b72cf1f67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782361461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2782361461
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.371224687
Short name T709
Test name
Test status
Simulation time 484858705602 ps
CPU time 292.81 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:40:31 PM PDT 24
Peak memory 201396 kb
Host smart-afb485cc-b62d-4c44-885d-e2a851b79d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371224687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.371224687
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3755816829
Short name T785
Test name
Test status
Simulation time 333776496178 ps
CPU time 344.23 seconds
Started Aug 06 07:35:36 PM PDT 24
Finished Aug 06 07:41:21 PM PDT 24
Peak memory 201420 kb
Host smart-7e83174a-b581-42a0-a3f4-3397b94202fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755816829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3755816829
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4145198072
Short name T296
Test name
Test status
Simulation time 528223863827 ps
CPU time 1168.98 seconds
Started Aug 06 07:35:39 PM PDT 24
Finished Aug 06 07:55:08 PM PDT 24
Peak memory 201464 kb
Host smart-3bc2777f-d0d1-40f7-a583-5eb8ee90e9dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145198072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4145198072
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.880130514
Short name T10
Test name
Test status
Simulation time 194003216347 ps
CPU time 119.92 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:37:38 PM PDT 24
Peak memory 201464 kb
Host smart-7730a27b-7941-4f38-bd5c-baeded277c04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880130514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.880130514
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3754551979
Short name T572
Test name
Test status
Simulation time 35763554873 ps
CPU time 21.14 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:35:59 PM PDT 24
Peak memory 201388 kb
Host smart-bcb63915-4464-4496-ada8-83ba090408d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754551979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3754551979
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2072553285
Short name T476
Test name
Test status
Simulation time 4322134594 ps
CPU time 6.2 seconds
Started Aug 06 07:35:37 PM PDT 24
Finished Aug 06 07:35:44 PM PDT 24
Peak memory 201396 kb
Host smart-1a720b45-02c1-4f40-86ff-c3f290d12efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072553285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2072553285
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2057337529
Short name T379
Test name
Test status
Simulation time 5668687698 ps
CPU time 2.95 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:35:41 PM PDT 24
Peak memory 201296 kb
Host smart-d0a846cb-a88b-450b-873b-d8354a67a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057337529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2057337529
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2529866895
Short name T355
Test name
Test status
Simulation time 149082497682 ps
CPU time 719.89 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 202008 kb
Host smart-9b2fd84a-a9e7-427d-9eea-95f9f7c850ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529866895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2529866895
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1184749946
Short name T650
Test name
Test status
Simulation time 479278063 ps
CPU time 1.46 seconds
Started Aug 06 07:35:54 PM PDT 24
Finished Aug 06 07:35:55 PM PDT 24
Peak memory 201244 kb
Host smart-3fc21b6b-a7c9-487a-aff2-bc805e21d96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184749946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1184749946
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3792086597
Short name T142
Test name
Test status
Simulation time 556314511808 ps
CPU time 896.09 seconds
Started Aug 06 07:36:01 PM PDT 24
Finished Aug 06 07:50:57 PM PDT 24
Peak memory 201420 kb
Host smart-ee5b11f8-7d53-4bc1-b0ab-10515b8a564f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792086597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3792086597
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3346039458
Short name T155
Test name
Test status
Simulation time 523739328074 ps
CPU time 911.24 seconds
Started Aug 06 07:35:52 PM PDT 24
Finished Aug 06 07:51:04 PM PDT 24
Peak memory 201444 kb
Host smart-c35c7744-171e-4768-8be8-80b3f7672214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346039458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3346039458
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2397324526
Short name T611
Test name
Test status
Simulation time 160306720253 ps
CPU time 27.02 seconds
Started Aug 06 07:35:56 PM PDT 24
Finished Aug 06 07:36:23 PM PDT 24
Peak memory 201468 kb
Host smart-24ae9bc4-a1dc-4a57-bf5f-0327b2abedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397324526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2397324526
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1958662072
Short name T392
Test name
Test status
Simulation time 331751379995 ps
CPU time 382.21 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:42:16 PM PDT 24
Peak memory 201528 kb
Host smart-1245e2fc-bc95-4999-9d39-47d418fa9cb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958662072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1958662072
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2471777020
Short name T646
Test name
Test status
Simulation time 328146205666 ps
CPU time 291.68 seconds
Started Aug 06 07:35:41 PM PDT 24
Finished Aug 06 07:40:33 PM PDT 24
Peak memory 201628 kb
Host smart-aa09f06f-f629-4779-ba4b-77fe64b1be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471777020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2471777020
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.697022492
Short name T365
Test name
Test status
Simulation time 325252693321 ps
CPU time 679.79 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 201476 kb
Host smart-31dcac9b-a5f3-4cad-b455-0714f5951da3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=697022492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.697022492
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1280322778
Short name T716
Test name
Test status
Simulation time 180036189541 ps
CPU time 90.27 seconds
Started Aug 06 07:35:54 PM PDT 24
Finished Aug 06 07:37:24 PM PDT 24
Peak memory 201420 kb
Host smart-ece4be2e-35d4-4c5c-a49b-7460109d99f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280322778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1280322778
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.559835374
Short name T683
Test name
Test status
Simulation time 111148391176 ps
CPU time 579.56 seconds
Started Aug 06 07:35:59 PM PDT 24
Finished Aug 06 07:45:39 PM PDT 24
Peak memory 201844 kb
Host smart-d673ec46-3142-4565-9700-2b50d08af518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559835374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.559835374
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3881644227
Short name T411
Test name
Test status
Simulation time 24739818533 ps
CPU time 16.5 seconds
Started Aug 06 07:35:56 PM PDT 24
Finished Aug 06 07:36:12 PM PDT 24
Peak memory 201336 kb
Host smart-d6600344-c4f5-40b9-8e24-2078da60ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881644227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3881644227
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1959009920
Short name T603
Test name
Test status
Simulation time 4454662559 ps
CPU time 11.36 seconds
Started Aug 06 07:35:57 PM PDT 24
Finished Aug 06 07:36:08 PM PDT 24
Peak memory 201260 kb
Host smart-3e24553d-39d1-4632-b39a-810769c734d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959009920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1959009920
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.186853876
Short name T669
Test name
Test status
Simulation time 5896190568 ps
CPU time 7.12 seconds
Started Aug 06 07:35:38 PM PDT 24
Finished Aug 06 07:35:46 PM PDT 24
Peak memory 201380 kb
Host smart-8f4683b8-f880-4bcf-915d-ef85596707a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186853876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.186853876
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3649225728
Short name T594
Test name
Test status
Simulation time 328754828508 ps
CPU time 412.71 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:42:46 PM PDT 24
Peak memory 201424 kb
Host smart-36ea7464-b7b5-46b9-9c68-1fd74ee0fb72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649225728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3649225728
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.356425204
Short name T38
Test name
Test status
Simulation time 57778444481 ps
CPU time 44.12 seconds
Started Aug 06 07:35:52 PM PDT 24
Finished Aug 06 07:36:37 PM PDT 24
Peak memory 210204 kb
Host smart-531aa2fa-3be3-4bc0-b746-52f350247727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356425204 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.356425204
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2779066278
Short name T360
Test name
Test status
Simulation time 398712704 ps
CPU time 0.75 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:32:19 PM PDT 24
Peak memory 201228 kb
Host smart-83d233cc-6c4f-4c1e-85e2-bcc9e6274e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779066278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2779066278
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2128909886
Short name T148
Test name
Test status
Simulation time 220569201151 ps
CPU time 65.5 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:33:26 PM PDT 24
Peak memory 201444 kb
Host smart-5794f668-b057-4b1d-b2f9-80f0f0037e3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128909886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2128909886
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1614523164
Short name T204
Test name
Test status
Simulation time 486251004156 ps
CPU time 118.98 seconds
Started Aug 06 07:32:21 PM PDT 24
Finished Aug 06 07:34:20 PM PDT 24
Peak memory 201444 kb
Host smart-2c48ff90-727a-4e94-8fce-5c970f6bc9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614523164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1614523164
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2347764720
Short name T498
Test name
Test status
Simulation time 317722241834 ps
CPU time 186.3 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:35:27 PM PDT 24
Peak memory 201416 kb
Host smart-143a1617-62a4-4fc4-b6b0-afbb99be1104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347764720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2347764720
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3780919822
Short name T710
Test name
Test status
Simulation time 492198766747 ps
CPU time 120.95 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:34:21 PM PDT 24
Peak memory 201388 kb
Host smart-44576b21-5e9e-4c34-8f4a-3daf2d96ec04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780919822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3780919822
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.760350680
Short name T159
Test name
Test status
Simulation time 495229037233 ps
CPU time 117.44 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:34:17 PM PDT 24
Peak memory 201420 kb
Host smart-dc3ea1f3-490d-497a-9253-071273282c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760350680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.760350680
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.314742329
Short name T530
Test name
Test status
Simulation time 494637644465 ps
CPU time 238.13 seconds
Started Aug 06 07:32:21 PM PDT 24
Finished Aug 06 07:36:19 PM PDT 24
Peak memory 201448 kb
Host smart-bc7d0b35-6af2-4b1c-80fe-b38682a1a727
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=314742329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.314742329
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3222781597
Short name T363
Test name
Test status
Simulation time 618407218619 ps
CPU time 1455.26 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:56:34 PM PDT 24
Peak memory 201396 kb
Host smart-9ac787c1-0da2-4f1e-9039-96c529b2d80d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222781597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3222781597
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.767771581
Short name T437
Test name
Test status
Simulation time 132081957724 ps
CPU time 691.35 seconds
Started Aug 06 07:32:19 PM PDT 24
Finished Aug 06 07:43:50 PM PDT 24
Peak memory 201836 kb
Host smart-c3c330b5-73a3-4e6c-9f55-791469e6fa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767771581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.767771581
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1410789785
Short name T642
Test name
Test status
Simulation time 31718066366 ps
CPU time 18.62 seconds
Started Aug 06 07:32:20 PM PDT 24
Finished Aug 06 07:32:39 PM PDT 24
Peak memory 201336 kb
Host smart-508e0bb5-a2f0-4569-8afd-7d4fd88332af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410789785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1410789785
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3537062549
Short name T378
Test name
Test status
Simulation time 4259122314 ps
CPU time 3.14 seconds
Started Aug 06 07:32:21 PM PDT 24
Finished Aug 06 07:32:24 PM PDT 24
Peak memory 201332 kb
Host smart-88edcfc2-9a7c-46db-bc9b-07334da6b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537062549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3537062549
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.455226568
Short name T68
Test name
Test status
Simulation time 3880594438 ps
CPU time 9.91 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 217072 kb
Host smart-e4880828-ac0b-4340-a32f-5d8ed937a35a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455226568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.455226568
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3083671074
Short name T538
Test name
Test status
Simulation time 5680602987 ps
CPU time 7.4 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:32:21 PM PDT 24
Peak memory 201544 kb
Host smart-3917e643-8aa1-4cec-98fa-20d40d9a44ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083671074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3083671074
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3385789971
Short name T302
Test name
Test status
Simulation time 262125100674 ps
CPU time 64.82 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:33:20 PM PDT 24
Peak memory 210132 kb
Host smart-3a700586-bfd8-4da0-8b9e-7f03f2187137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385789971 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3385789971
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2107584344
Short name T420
Test name
Test status
Simulation time 504530142 ps
CPU time 1.58 seconds
Started Aug 06 07:36:11 PM PDT 24
Finished Aug 06 07:36:13 PM PDT 24
Peak memory 201116 kb
Host smart-1f565855-ea02-4108-a2cb-474cef363f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107584344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2107584344
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2249536359
Short name T727
Test name
Test status
Simulation time 504094911256 ps
CPU time 807.1 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:49:20 PM PDT 24
Peak memory 201396 kb
Host smart-df4e53da-b4bd-42d6-875e-6f181a18e95c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249536359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2249536359
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2862651450
Short name T199
Test name
Test status
Simulation time 487943826835 ps
CPU time 1120.61 seconds
Started Aug 06 07:36:01 PM PDT 24
Finished Aug 06 07:54:41 PM PDT 24
Peak memory 201460 kb
Host smart-cd743220-6034-43fc-b1b5-e7dc6c090f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862651450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2862651450
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2154046300
Short name T515
Test name
Test status
Simulation time 327492205043 ps
CPU time 358.13 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:41:51 PM PDT 24
Peak memory 201496 kb
Host smart-329020f2-6180-4c09-8721-1a86cda7ee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154046300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2154046300
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4294402305
Short name T779
Test name
Test status
Simulation time 500809783729 ps
CPU time 1035.53 seconds
Started Aug 06 07:35:52 PM PDT 24
Finished Aug 06 07:53:08 PM PDT 24
Peak memory 201376 kb
Host smart-79973058-9506-4862-ba4c-389f6233caa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294402305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4294402305
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3197215487
Short name T165
Test name
Test status
Simulation time 334014880298 ps
CPU time 286.25 seconds
Started Aug 06 07:35:54 PM PDT 24
Finished Aug 06 07:40:40 PM PDT 24
Peak memory 201412 kb
Host smart-84d2e19b-6662-4bff-bb0d-a3c6f84467e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197215487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3197215487
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1263587451
Short name T146
Test name
Test status
Simulation time 164805490093 ps
CPU time 204.8 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:39:18 PM PDT 24
Peak memory 201440 kb
Host smart-75639ff2-92ad-4a4b-b820-43579a5ec71a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263587451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1263587451
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2777060875
Short name T318
Test name
Test status
Simulation time 347116702364 ps
CPU time 826.33 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 201424 kb
Host smart-18d3c1f5-15fa-4e2c-89c7-0afcf4ad72d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777060875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2777060875
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3258595983
Short name T458
Test name
Test status
Simulation time 204235246112 ps
CPU time 468.34 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:43:42 PM PDT 24
Peak memory 201344 kb
Host smart-aa6ae09b-e78a-4454-977d-92c80584ed51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258595983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3258595983
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3464488648
Short name T542
Test name
Test status
Simulation time 36986852949 ps
CPU time 86.29 seconds
Started Aug 06 07:35:53 PM PDT 24
Finished Aug 06 07:37:20 PM PDT 24
Peak memory 201304 kb
Host smart-607f30b9-65f2-4629-b46b-57598f7cb887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464488648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3464488648
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1535430221
Short name T102
Test name
Test status
Simulation time 4201261334 ps
CPU time 11.12 seconds
Started Aug 06 07:36:01 PM PDT 24
Finished Aug 06 07:36:12 PM PDT 24
Peak memory 201348 kb
Host smart-7efe4ac9-f269-4871-b90a-873ea26c3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535430221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1535430221
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3066313210
Short name T533
Test name
Test status
Simulation time 5783432175 ps
CPU time 2.94 seconds
Started Aug 06 07:35:54 PM PDT 24
Finished Aug 06 07:35:57 PM PDT 24
Peak memory 201376 kb
Host smart-ab3fe976-c3e2-4c77-8c98-6cd8e07d5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066313210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3066313210
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3333069557
Short name T332
Test name
Test status
Simulation time 246177920764 ps
CPU time 34.98 seconds
Started Aug 06 07:36:11 PM PDT 24
Finished Aug 06 07:36:46 PM PDT 24
Peak memory 201500 kb
Host smart-ccd46085-8b38-49f0-a014-87bed4c74c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333069557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3333069557
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3289786775
Short name T495
Test name
Test status
Simulation time 424498550 ps
CPU time 1.1 seconds
Started Aug 06 07:36:09 PM PDT 24
Finished Aug 06 07:36:11 PM PDT 24
Peak memory 201248 kb
Host smart-b84adea4-9f21-4a1b-b985-f5092cdc10f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289786775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3289786775
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3198880975
Short name T322
Test name
Test status
Simulation time 165612340435 ps
CPU time 99.49 seconds
Started Aug 06 07:36:12 PM PDT 24
Finished Aug 06 07:37:51 PM PDT 24
Peak memory 201436 kb
Host smart-a81cb3fe-9083-4199-a3d9-225bb47dd05f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198880975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3198880975
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.69087683
Short name T757
Test name
Test status
Simulation time 168511749330 ps
CPU time 406.57 seconds
Started Aug 06 07:36:16 PM PDT 24
Finished Aug 06 07:43:02 PM PDT 24
Peak memory 201344 kb
Host smart-f792a248-ff03-40c0-8567-0b459db23bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69087683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.69087683
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3885168301
Short name T317
Test name
Test status
Simulation time 323395360784 ps
CPU time 213.59 seconds
Started Aug 06 07:36:10 PM PDT 24
Finished Aug 06 07:39:44 PM PDT 24
Peak memory 201472 kb
Host smart-3176920a-16e9-4467-9e2d-1b6bd68f40d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885168301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3885168301
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1296438082
Short name T621
Test name
Test status
Simulation time 329283581327 ps
CPU time 717.68 seconds
Started Aug 06 07:36:19 PM PDT 24
Finished Aug 06 07:48:17 PM PDT 24
Peak memory 201432 kb
Host smart-eaf38c08-c2b6-47c4-802f-913198b8bcce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296438082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1296438082
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3703361492
Short name T315
Test name
Test status
Simulation time 482970236907 ps
CPU time 539.28 seconds
Started Aug 06 07:36:11 PM PDT 24
Finished Aug 06 07:45:10 PM PDT 24
Peak memory 201428 kb
Host smart-8e07914e-4677-460f-bdcc-f63f1990c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703361492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3703361492
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2012233422
Short name T736
Test name
Test status
Simulation time 480022617343 ps
CPU time 284.43 seconds
Started Aug 06 07:36:12 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 201448 kb
Host smart-825f12e5-3720-4060-8061-5ad3e25ec66a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012233422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2012233422
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2068709992
Short name T566
Test name
Test status
Simulation time 187276238178 ps
CPU time 104.27 seconds
Started Aug 06 07:36:13 PM PDT 24
Finished Aug 06 07:37:57 PM PDT 24
Peak memory 201476 kb
Host smart-e0cf6398-f0a9-484c-be72-d5847f771c5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068709992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2068709992
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.944368334
Short name T578
Test name
Test status
Simulation time 398296413339 ps
CPU time 64.85 seconds
Started Aug 06 07:36:15 PM PDT 24
Finished Aug 06 07:37:19 PM PDT 24
Peak memory 201468 kb
Host smart-736e99a5-be52-40c4-ae7f-ead633f62c94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944368334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.944368334
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2043375481
Short name T596
Test name
Test status
Simulation time 71432297165 ps
CPU time 272.76 seconds
Started Aug 06 07:36:14 PM PDT 24
Finished Aug 06 07:40:47 PM PDT 24
Peak memory 201792 kb
Host smart-3930b6f1-276c-4f5c-bb2a-220ae11f33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043375481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2043375481
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2905708174
Short name T390
Test name
Test status
Simulation time 27819046228 ps
CPU time 63.96 seconds
Started Aug 06 07:36:12 PM PDT 24
Finished Aug 06 07:37:16 PM PDT 24
Peak memory 201304 kb
Host smart-89eea6fc-c968-4787-b15b-660a2d531ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905708174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2905708174
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1448605739
Short name T201
Test name
Test status
Simulation time 4737689599 ps
CPU time 11 seconds
Started Aug 06 07:36:13 PM PDT 24
Finished Aug 06 07:36:24 PM PDT 24
Peak memory 201364 kb
Host smart-4fb4b7be-c5d0-4bd9-bd4b-7eb2151da0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448605739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1448605739
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.737643595
Short name T468
Test name
Test status
Simulation time 5497561121 ps
CPU time 7.05 seconds
Started Aug 06 07:36:12 PM PDT 24
Finished Aug 06 07:36:19 PM PDT 24
Peak memory 201336 kb
Host smart-c5900d44-4d91-4319-acfa-b6713270dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737643595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.737643595
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.760811250
Short name T794
Test name
Test status
Simulation time 328520794730 ps
CPU time 724.74 seconds
Started Aug 06 07:36:11 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 201444 kb
Host smart-8e7a98b2-22f1-473a-bb66-b39ff01d52fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760811250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
760811250
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2282007059
Short name T219
Test name
Test status
Simulation time 250441822511 ps
CPU time 219.22 seconds
Started Aug 06 07:36:12 PM PDT 24
Finished Aug 06 07:39:51 PM PDT 24
Peak memory 210132 kb
Host smart-f5e78836-77be-4386-a99f-aa6633a805e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282007059 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2282007059
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3879602370
Short name T184
Test name
Test status
Simulation time 373031851 ps
CPU time 0.81 seconds
Started Aug 06 07:36:25 PM PDT 24
Finished Aug 06 07:36:26 PM PDT 24
Peak memory 201192 kb
Host smart-fab28167-8ae5-469f-828c-1ba412b415bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879602370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3879602370
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.276602981
Short name T290
Test name
Test status
Simulation time 536424583339 ps
CPU time 603.61 seconds
Started Aug 06 07:36:24 PM PDT 24
Finished Aug 06 07:46:28 PM PDT 24
Peak memory 201508 kb
Host smart-337d2f79-abb2-4cad-afd3-597afbcdb51d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276602981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.276602981
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.98671998
Short name T702
Test name
Test status
Simulation time 327730729347 ps
CPU time 769.85 seconds
Started Aug 06 07:36:25 PM PDT 24
Finished Aug 06 07:49:15 PM PDT 24
Peak memory 201524 kb
Host smart-7ae357e8-528b-4a9c-a708-257179cb7747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98671998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.98671998
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3434264556
Short name T316
Test name
Test status
Simulation time 168150767734 ps
CPU time 199.44 seconds
Started Aug 06 07:36:25 PM PDT 24
Finished Aug 06 07:39:44 PM PDT 24
Peak memory 201336 kb
Host smart-1d6bc246-ec33-43ab-bc80-0954388a361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434264556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3434264556
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.442616137
Short name T372
Test name
Test status
Simulation time 162290613200 ps
CPU time 351.05 seconds
Started Aug 06 07:36:24 PM PDT 24
Finished Aug 06 07:42:15 PM PDT 24
Peak memory 201480 kb
Host smart-16ade635-fbc5-4f1e-8d1b-d3b02425def2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=442616137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.442616137
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.266483537
Short name T200
Test name
Test status
Simulation time 485970252291 ps
CPU time 298.98 seconds
Started Aug 06 07:36:11 PM PDT 24
Finished Aug 06 07:41:10 PM PDT 24
Peak memory 201452 kb
Host smart-378537f8-1135-4dbd-81ca-a4a71b72e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266483537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.266483537
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1302704061
Short name T426
Test name
Test status
Simulation time 162904090287 ps
CPU time 110.91 seconds
Started Aug 06 07:36:27 PM PDT 24
Finished Aug 06 07:38:18 PM PDT 24
Peak memory 201392 kb
Host smart-82a1b4f7-ebdd-47ad-bcd1-44446ee0d992
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302704061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1302704061
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3053125909
Short name T307
Test name
Test status
Simulation time 179948326108 ps
CPU time 109.89 seconds
Started Aug 06 07:36:23 PM PDT 24
Finished Aug 06 07:38:13 PM PDT 24
Peak memory 201420 kb
Host smart-b18010e4-9d44-4d2b-8836-7daeb91dfeeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053125909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3053125909
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.955631925
Short name T749
Test name
Test status
Simulation time 193665856857 ps
CPU time 107.42 seconds
Started Aug 06 07:36:23 PM PDT 24
Finished Aug 06 07:38:11 PM PDT 24
Peak memory 201428 kb
Host smart-a485b822-e8c3-49ba-a81f-513a22a994e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955631925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.955631925
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3925851678
Short name T52
Test name
Test status
Simulation time 83533419262 ps
CPU time 284.61 seconds
Started Aug 06 07:36:24 PM PDT 24
Finished Aug 06 07:41:09 PM PDT 24
Peak memory 201848 kb
Host smart-90846bf0-60dd-4ddc-bd30-1e6071b5ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925851678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3925851678
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.532558114
Short name T775
Test name
Test status
Simulation time 21461857739 ps
CPU time 6.64 seconds
Started Aug 06 07:36:25 PM PDT 24
Finished Aug 06 07:36:32 PM PDT 24
Peak memory 201360 kb
Host smart-94f6148b-1096-4bc1-9390-17dfc0e780d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532558114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.532558114
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1888471391
Short name T124
Test name
Test status
Simulation time 2695745783 ps
CPU time 6.96 seconds
Started Aug 06 07:36:27 PM PDT 24
Finished Aug 06 07:36:34 PM PDT 24
Peak memory 201272 kb
Host smart-5da9b8cc-1a47-453b-b0f0-62dd30bca250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888471391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1888471391
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2131422887
Short name T194
Test name
Test status
Simulation time 5965489401 ps
CPU time 12.35 seconds
Started Aug 06 07:36:13 PM PDT 24
Finished Aug 06 07:36:26 PM PDT 24
Peak memory 201380 kb
Host smart-31a0339d-d335-4318-99c7-203d8d673a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131422887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2131422887
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1835138534
Short name T545
Test name
Test status
Simulation time 420934047069 ps
CPU time 439.21 seconds
Started Aug 06 07:36:26 PM PDT 24
Finished Aug 06 07:43:45 PM PDT 24
Peak memory 201436 kb
Host smart-d7717076-74fe-4803-b79c-12ec10f5c78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835138534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1835138534
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2457224239
Short name T520
Test name
Test status
Simulation time 128694887700 ps
CPU time 233.34 seconds
Started Aug 06 07:36:23 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 210252 kb
Host smart-2cc5b747-0a4f-483c-8ee8-a98cdec1b405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457224239 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2457224239
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.278476372
Short name T457
Test name
Test status
Simulation time 470047523 ps
CPU time 0.75 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:36:53 PM PDT 24
Peak memory 201204 kb
Host smart-27fc57be-ac1b-4631-9944-11b2551aad0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278476372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.278476372
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.952749691
Short name T230
Test name
Test status
Simulation time 453807168894 ps
CPU time 157.78 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:39:30 PM PDT 24
Peak memory 201400 kb
Host smart-dba71bd4-bfc6-4604-a5a4-9c4389347ec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952749691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.952749691
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3314459478
Short name T686
Test name
Test status
Simulation time 172340704453 ps
CPU time 92.56 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:38:25 PM PDT 24
Peak memory 201436 kb
Host smart-75f3250b-687b-45b1-9064-07b610204c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314459478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3314459478
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1406643336
Short name T752
Test name
Test status
Simulation time 483218191640 ps
CPU time 1152.72 seconds
Started Aug 06 07:36:24 PM PDT 24
Finished Aug 06 07:55:37 PM PDT 24
Peak memory 201444 kb
Host smart-b74c35f4-45f5-4e2b-9632-b637e57d7729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406643336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1406643336
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3700653504
Short name T492
Test name
Test status
Simulation time 168365830899 ps
CPU time 29.56 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:37:22 PM PDT 24
Peak memory 201416 kb
Host smart-a577b815-4d3b-4f88-b2b3-6258220e367b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700653504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3700653504
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.674276329
Short name T664
Test name
Test status
Simulation time 491137998858 ps
CPU time 1158.08 seconds
Started Aug 06 07:36:26 PM PDT 24
Finished Aug 06 07:55:44 PM PDT 24
Peak memory 201440 kb
Host smart-b67e3218-2d58-468d-9f7e-f8ae23f99bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674276329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.674276329
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3685991701
Short name T486
Test name
Test status
Simulation time 489856872276 ps
CPU time 580.52 seconds
Started Aug 06 07:36:25 PM PDT 24
Finished Aug 06 07:46:05 PM PDT 24
Peak memory 201464 kb
Host smart-e99bf26c-eb2f-455e-80f5-90eb998652c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685991701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3685991701
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1990540973
Short name T330
Test name
Test status
Simulation time 201311719696 ps
CPU time 453.5 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:44:25 PM PDT 24
Peak memory 201448 kb
Host smart-29473606-d7b7-4662-b53e-2e68469a8ccc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990540973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1990540973
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2612046043
Short name T681
Test name
Test status
Simulation time 610005992703 ps
CPU time 735.24 seconds
Started Aug 06 07:36:54 PM PDT 24
Finished Aug 06 07:49:09 PM PDT 24
Peak memory 201320 kb
Host smart-72528b76-2f23-4a84-8d00-169c06d95e62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612046043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2612046043
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1676549305
Short name T208
Test name
Test status
Simulation time 130157483042 ps
CPU time 433.37 seconds
Started Aug 06 07:36:51 PM PDT 24
Finished Aug 06 07:44:05 PM PDT 24
Peak memory 201900 kb
Host smart-ed7f99f6-149d-4247-a5e7-4d963fe0105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676549305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1676549305
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4079497398
Short name T585
Test name
Test status
Simulation time 46872378930 ps
CPU time 21.81 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:37:15 PM PDT 24
Peak memory 201348 kb
Host smart-074c8a47-e0ca-4c3a-9e9c-497a4f635531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079497398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4079497398
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3041804633
Short name T399
Test name
Test status
Simulation time 2774789683 ps
CPU time 2.25 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:36:55 PM PDT 24
Peak memory 201312 kb
Host smart-63cb5b23-7afd-4598-a364-4e0dc88e9b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041804633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3041804633
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.925348673
Short name T511
Test name
Test status
Simulation time 5810027230 ps
CPU time 3.88 seconds
Started Aug 06 07:36:24 PM PDT 24
Finished Aug 06 07:36:28 PM PDT 24
Peak memory 201312 kb
Host smart-3e420297-dc4a-4fdb-81f8-977f116811ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925348673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.925348673
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1644896288
Short name T680
Test name
Test status
Simulation time 25264865126 ps
CPU time 73 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:38:06 PM PDT 24
Peak memory 210152 kb
Host smart-d5fd9c72-822e-440e-bcfe-cbeb9c687c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644896288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1644896288
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1251566995
Short name T425
Test name
Test status
Simulation time 387365920 ps
CPU time 1.41 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:37:12 PM PDT 24
Peak memory 201216 kb
Host smart-0bc938f6-aa3d-4241-91ae-ab260fa9eb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251566995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1251566995
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1294971885
Short name T261
Test name
Test status
Simulation time 353737192365 ps
CPU time 208.73 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:40:40 PM PDT 24
Peak memory 201496 kb
Host smart-7395c63d-c6cc-4ec6-ac7e-0863c4e6b6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294971885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1294971885
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.494286494
Short name T273
Test name
Test status
Simulation time 204785205911 ps
CPU time 126.97 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:39:18 PM PDT 24
Peak memory 201416 kb
Host smart-99cee773-e867-4f6a-abb5-b4cf151d1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494286494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.494286494
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2037919843
Short name T314
Test name
Test status
Simulation time 160248987197 ps
CPU time 94.94 seconds
Started Aug 06 07:36:50 PM PDT 24
Finished Aug 06 07:38:26 PM PDT 24
Peak memory 201424 kb
Host smart-8f4edb46-2bdc-44d3-a687-2c9e3e73bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037919843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2037919843
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1874010407
Short name T617
Test name
Test status
Simulation time 496685064879 ps
CPU time 1044.73 seconds
Started Aug 06 07:36:50 PM PDT 24
Finished Aug 06 07:54:15 PM PDT 24
Peak memory 201396 kb
Host smart-5f8feccc-bdb1-4004-8179-171ab2b02814
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874010407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1874010407
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1522356413
Short name T601
Test name
Test status
Simulation time 160630330048 ps
CPU time 46.3 seconds
Started Aug 06 07:36:53 PM PDT 24
Finished Aug 06 07:37:39 PM PDT 24
Peak memory 201388 kb
Host smart-7eb2799a-7d02-471f-b992-9751d918ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522356413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1522356413
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.223209804
Short name T537
Test name
Test status
Simulation time 332917102926 ps
CPU time 376.16 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:43:08 PM PDT 24
Peak memory 201436 kb
Host smart-9d26b79c-a142-46ad-b4e3-d7cec312962a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=223209804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.223209804
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3985021373
Short name T751
Test name
Test status
Simulation time 396107236123 ps
CPU time 184.61 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:40:18 PM PDT 24
Peak memory 201448 kb
Host smart-6cb06625-5bf7-478d-a1e4-4a2b44160bdb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985021373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3985021373
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3788367550
Short name T509
Test name
Test status
Simulation time 76481758876 ps
CPU time 442.57 seconds
Started Aug 06 07:37:10 PM PDT 24
Finished Aug 06 07:44:33 PM PDT 24
Peak memory 201912 kb
Host smart-b4fd745e-6f8b-41b1-93ed-fdbf517e8c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788367550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3788367550
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3789067592
Short name T471
Test name
Test status
Simulation time 43811330288 ps
CPU time 24.94 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:37:36 PM PDT 24
Peak memory 201536 kb
Host smart-be7fb265-894f-4160-b408-e8095ce7b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789067592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3789067592
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.344339849
Short name T697
Test name
Test status
Simulation time 3041043263 ps
CPU time 7.79 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:37:20 PM PDT 24
Peak memory 201332 kb
Host smart-ce1e59ca-b3c0-41b3-aab5-471182dab1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344339849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.344339849
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.649109392
Short name T513
Test name
Test status
Simulation time 5740308715 ps
CPU time 13.15 seconds
Started Aug 06 07:36:52 PM PDT 24
Finished Aug 06 07:37:05 PM PDT 24
Peak memory 201248 kb
Host smart-e9c9ab23-ad51-49e5-a4ee-19fe7d4ad9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649109392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.649109392
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2519122472
Short name T35
Test name
Test status
Simulation time 166895274969 ps
CPU time 96 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:38:47 PM PDT 24
Peak memory 201392 kb
Host smart-6e760fea-8246-4f33-9068-604f371c7427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519122472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2519122472
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.717302197
Short name T15
Test name
Test status
Simulation time 486052806 ps
CPU time 1.71 seconds
Started Aug 06 07:37:13 PM PDT 24
Finished Aug 06 07:37:15 PM PDT 24
Peak memory 201260 kb
Host smart-d98cee72-838f-4c78-8244-e28067a5dad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717302197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.717302197
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2052366468
Short name T778
Test name
Test status
Simulation time 345862889683 ps
CPU time 776.9 seconds
Started Aug 06 07:37:13 PM PDT 24
Finished Aug 06 07:50:10 PM PDT 24
Peak memory 201508 kb
Host smart-a0baaaf5-dff0-4276-ac1e-99447a1374bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052366468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2052366468
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3106696005
Short name T764
Test name
Test status
Simulation time 482690967506 ps
CPU time 277.53 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:41:50 PM PDT 24
Peak memory 201408 kb
Host smart-b90d3f08-ce2f-417a-aa27-eefe1d5e390f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106696005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3106696005
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.562025911
Short name T610
Test name
Test status
Simulation time 162121997353 ps
CPU time 396.76 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:43:47 PM PDT 24
Peak memory 201408 kb
Host smart-3122cd56-8243-4ff6-bccf-ee698d8fcaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562025911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.562025911
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2781969203
Short name T521
Test name
Test status
Simulation time 495179300736 ps
CPU time 1082.21 seconds
Started Aug 06 07:37:11 PM PDT 24
Finished Aug 06 07:55:13 PM PDT 24
Peak memory 201416 kb
Host smart-b8f3d6e4-3ea0-4122-b4a0-c91bcebc6b9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781969203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2781969203
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2228572444
Short name T573
Test name
Test status
Simulation time 188082812397 ps
CPU time 430.1 seconds
Started Aug 06 07:37:13 PM PDT 24
Finished Aug 06 07:44:23 PM PDT 24
Peak memory 201432 kb
Host smart-74ba048b-44c8-4c00-a82b-d5f471cd7b63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228572444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2228572444
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1948005155
Short name T359
Test name
Test status
Simulation time 203785496413 ps
CPU time 127.68 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:39:22 PM PDT 24
Peak memory 201504 kb
Host smart-34f69b29-f4b6-4d6a-bf90-c848c2277ca5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948005155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1948005155
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1889474318
Short name T220
Test name
Test status
Simulation time 73231656384 ps
CPU time 322.31 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:42:36 PM PDT 24
Peak memory 201916 kb
Host smart-b44ce973-fa44-43b0-a57d-c755fc1be22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889474318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1889474318
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4017451202
Short name T408
Test name
Test status
Simulation time 35424661630 ps
CPU time 23.25 seconds
Started Aug 06 07:37:13 PM PDT 24
Finished Aug 06 07:37:36 PM PDT 24
Peak memory 201252 kb
Host smart-1a95fbc3-91f4-4bc0-b690-3dc54811335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017451202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4017451202
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1611717309
Short name T501
Test name
Test status
Simulation time 3653562369 ps
CPU time 9.24 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:37:23 PM PDT 24
Peak memory 201316 kb
Host smart-5092ae02-9826-4ce6-b9b4-6702a9d5642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611717309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1611717309
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2966009553
Short name T720
Test name
Test status
Simulation time 5660301285 ps
CPU time 1.94 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:37:14 PM PDT 24
Peak memory 201324 kb
Host smart-1ecc4da8-6edc-4d53-a907-83f9017e8914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966009553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2966009553
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1638186675
Short name T350
Test name
Test status
Simulation time 386489018624 ps
CPU time 885.64 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:52:00 PM PDT 24
Peak memory 201460 kb
Host smart-84ef1728-8da3-487a-a9c9-15303fc0646c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638186675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1638186675
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1341596903
Short name T45
Test name
Test status
Simulation time 31232131031 ps
CPU time 36.71 seconds
Started Aug 06 07:37:14 PM PDT 24
Finished Aug 06 07:37:50 PM PDT 24
Peak memory 209792 kb
Host smart-00e22e36-1c95-4588-97bf-7015d6729e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341596903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1341596903
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1195522108
Short name T693
Test name
Test status
Simulation time 341782913 ps
CPU time 1.35 seconds
Started Aug 06 07:37:29 PM PDT 24
Finished Aug 06 07:37:31 PM PDT 24
Peak memory 201204 kb
Host smart-e246ef25-2c4f-4b67-b338-a2720b76125d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195522108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1195522108
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.235143416
Short name T677
Test name
Test status
Simulation time 188490550919 ps
CPU time 429.56 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:44:40 PM PDT 24
Peak memory 201436 kb
Host smart-eb97884d-af2e-47c1-82ca-cd9090075280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235143416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.235143416
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2063862766
Short name T788
Test name
Test status
Simulation time 488827011802 ps
CPU time 307.85 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:42:38 PM PDT 24
Peak memory 201404 kb
Host smart-02d998a9-5fc2-4895-8a05-52032d639308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063862766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2063862766
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.146264416
Short name T721
Test name
Test status
Simulation time 157764817343 ps
CPU time 102.71 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:39:14 PM PDT 24
Peak memory 201496 kb
Host smart-f5ff0817-bfe9-435f-98cb-f4e0f11f466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146264416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.146264416
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1860719864
Short name T781
Test name
Test status
Simulation time 327405072226 ps
CPU time 758.2 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 201468 kb
Host smart-16bad62c-9b5a-46a0-8de2-6277ae059e64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860719864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1860719864
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2897848467
Short name T166
Test name
Test status
Simulation time 487234699051 ps
CPU time 1031.56 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:54:24 PM PDT 24
Peak memory 201336 kb
Host smart-d69603f2-cd4d-4a35-88f1-6413a4bbab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897848467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2897848467
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2593696392
Short name T546
Test name
Test status
Simulation time 487938709953 ps
CPU time 1093.4 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:55:45 PM PDT 24
Peak memory 201380 kb
Host smart-d7ede9d9-69af-4181-9aaf-75c41f25f4e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593696392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2593696392
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4114036452
Short name T385
Test name
Test status
Simulation time 401799604398 ps
CPU time 427.81 seconds
Started Aug 06 07:37:36 PM PDT 24
Finished Aug 06 07:44:44 PM PDT 24
Peak memory 201432 kb
Host smart-d7aca617-9bef-436c-b0f9-efb18563dad7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114036452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4114036452
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1929098485
Short name T209
Test name
Test status
Simulation time 134328165545 ps
CPU time 666.19 seconds
Started Aug 06 07:37:29 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 201848 kb
Host smart-5770d58b-48b9-4368-80cd-f8ea966bec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929098485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1929098485
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2348447668
Short name T574
Test name
Test status
Simulation time 39794663679 ps
CPU time 86.05 seconds
Started Aug 06 07:37:29 PM PDT 24
Finished Aug 06 07:38:55 PM PDT 24
Peak memory 201308 kb
Host smart-9b78a2fa-dfc7-4147-8201-49cd9e465ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348447668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2348447668
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.631740376
Short name T587
Test name
Test status
Simulation time 3478361602 ps
CPU time 8.51 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:37:39 PM PDT 24
Peak memory 201360 kb
Host smart-4a2f4736-343a-4770-9ba9-7de5ee5cd6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631740376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.631740376
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.333000620
Short name T713
Test name
Test status
Simulation time 5694509097 ps
CPU time 4.1 seconds
Started Aug 06 07:37:12 PM PDT 24
Finished Aug 06 07:37:17 PM PDT 24
Peak memory 201356 kb
Host smart-5c7db896-1b32-49a3-aac4-f5389b3d1715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333000620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.333000620
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2068580166
Short name T339
Test name
Test status
Simulation time 265008902077 ps
CPU time 895.08 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:52:26 PM PDT 24
Peak memory 210100 kb
Host smart-c1a9d8da-fa48-407e-9b12-dde1d9073221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068580166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2068580166
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2449196187
Short name T40
Test name
Test status
Simulation time 26942089571 ps
CPU time 63.76 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:38:34 PM PDT 24
Peak memory 210152 kb
Host smart-aa8c168e-f1e8-491c-b30b-024901dae92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449196187 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2449196187
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3705404316
Short name T504
Test name
Test status
Simulation time 308981693 ps
CPU time 0.76 seconds
Started Aug 06 07:37:53 PM PDT 24
Finished Aug 06 07:37:54 PM PDT 24
Peak memory 201132 kb
Host smart-c4d950ce-78f9-4826-8782-e763ce021bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705404316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3705404316
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.733428952
Short name T737
Test name
Test status
Simulation time 492795673926 ps
CPU time 277.83 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:42:08 PM PDT 24
Peak memory 201348 kb
Host smart-415e9049-3599-4ec8-803d-5e2874c322a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733428952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.733428952
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.356422177
Short name T238
Test name
Test status
Simulation time 492022234294 ps
CPU time 1172.44 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:57:03 PM PDT 24
Peak memory 201432 kb
Host smart-6b9fc4ea-7ea7-4175-8ac1-d173d97df907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356422177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.356422177
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3660970815
Short name T206
Test name
Test status
Simulation time 491912140965 ps
CPU time 1070.31 seconds
Started Aug 06 07:37:36 PM PDT 24
Finished Aug 06 07:55:27 PM PDT 24
Peak memory 201444 kb
Host smart-d44c4dc2-94da-45c6-a3a3-a0b0793c297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660970815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3660970815
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2159313749
Short name T645
Test name
Test status
Simulation time 487770758709 ps
CPU time 609.94 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 201400 kb
Host smart-336572d2-3c0b-4c43-a4f0-a0807d3e33f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159313749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2159313749
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1485069292
Short name T232
Test name
Test status
Simulation time 483889822789 ps
CPU time 515.13 seconds
Started Aug 06 07:37:29 PM PDT 24
Finished Aug 06 07:46:04 PM PDT 24
Peak memory 201388 kb
Host smart-6d1bff48-db44-4971-940c-363526c81096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485069292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1485069292
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.272716067
Short name T773
Test name
Test status
Simulation time 324580305668 ps
CPU time 685.6 seconds
Started Aug 06 07:37:30 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 201328 kb
Host smart-57ebf6c1-5175-42cd-857b-9c4c7758ea28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=272716067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.272716067
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.542800003
Short name T380
Test name
Test status
Simulation time 207257545636 ps
CPU time 123.02 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:39:34 PM PDT 24
Peak memory 201420 kb
Host smart-f235b4c1-364e-43af-a4e6-dfe90c7cfef1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542800003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.542800003
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4270084043
Short name T756
Test name
Test status
Simulation time 107573063416 ps
CPU time 359.73 seconds
Started Aug 06 07:37:47 PM PDT 24
Finished Aug 06 07:43:47 PM PDT 24
Peak memory 201768 kb
Host smart-e57ac7a5-c33a-488f-86cb-aad7a99e60c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270084043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4270084043
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3034762406
Short name T487
Test name
Test status
Simulation time 24471366306 ps
CPU time 4.42 seconds
Started Aug 06 07:37:45 PM PDT 24
Finished Aug 06 07:37:50 PM PDT 24
Peak memory 201344 kb
Host smart-3a811443-85fc-4d0b-8e78-5d840b66e67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034762406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3034762406
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3706622272
Short name T555
Test name
Test status
Simulation time 5444583448 ps
CPU time 3.9 seconds
Started Aug 06 07:37:46 PM PDT 24
Finished Aug 06 07:37:49 PM PDT 24
Peak memory 201328 kb
Host smart-dc079a46-58ac-46e7-8a3f-a70ec4135fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706622272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3706622272
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.283611962
Short name T767
Test name
Test status
Simulation time 5846070041 ps
CPU time 3.46 seconds
Started Aug 06 07:37:31 PM PDT 24
Finished Aug 06 07:37:34 PM PDT 24
Peak memory 201388 kb
Host smart-13d9af7a-7590-4242-ae2c-2257853e82a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283611962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.283611962
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3355090833
Short name T242
Test name
Test status
Simulation time 177320382141 ps
CPU time 275.29 seconds
Started Aug 06 07:37:46 PM PDT 24
Finished Aug 06 07:42:21 PM PDT 24
Peak memory 201444 kb
Host smart-6bd9b047-5789-4611-ac92-f5e85bf1c20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355090833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3355090833
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.314053695
Short name T708
Test name
Test status
Simulation time 203359440562 ps
CPU time 206.25 seconds
Started Aug 06 07:37:45 PM PDT 24
Finished Aug 06 07:41:12 PM PDT 24
Peak memory 218300 kb
Host smart-a6d960bd-644a-4c72-ad46-699fa0918b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314053695 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.314053695
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.400168146
Short name T688
Test name
Test status
Simulation time 383048771 ps
CPU time 0.67 seconds
Started Aug 06 07:38:00 PM PDT 24
Finished Aug 06 07:38:01 PM PDT 24
Peak memory 201228 kb
Host smart-353c5f00-189f-4ce9-867c-d0ee37ba243c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400168146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.400168146
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2644322632
Short name T740
Test name
Test status
Simulation time 339967802093 ps
CPU time 744.8 seconds
Started Aug 06 07:37:52 PM PDT 24
Finished Aug 06 07:50:17 PM PDT 24
Peak memory 201480 kb
Host smart-e09a1ce4-8cf3-4929-b0c5-62eb438b6428
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644322632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2644322632
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3996679631
Short name T684
Test name
Test status
Simulation time 333966554557 ps
CPU time 184.64 seconds
Started Aug 06 07:37:53 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 201428 kb
Host smart-5ef3a3ff-10a0-4a45-9c81-cd1c209ed01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996679631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3996679631
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2167108132
Short name T429
Test name
Test status
Simulation time 492731853390 ps
CPU time 110.59 seconds
Started Aug 06 07:37:52 PM PDT 24
Finished Aug 06 07:39:43 PM PDT 24
Peak memory 201428 kb
Host smart-b9c4889e-a174-48c1-adaf-85ae88394a47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167108132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2167108132
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3283196339
Short name T139
Test name
Test status
Simulation time 165585964090 ps
CPU time 187.29 seconds
Started Aug 06 07:37:53 PM PDT 24
Finished Aug 06 07:41:00 PM PDT 24
Peak memory 201416 kb
Host smart-c934f246-7071-4434-afbf-2cd4b2b86169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283196339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3283196339
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1168832756
Short name T82
Test name
Test status
Simulation time 326546610975 ps
CPU time 722.78 seconds
Started Aug 06 07:37:44 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 201404 kb
Host smart-cc293785-53e4-4606-b950-e5dc758fec95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168832756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1168832756
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1282376235
Short name T326
Test name
Test status
Simulation time 171159316017 ps
CPU time 415.12 seconds
Started Aug 06 07:37:47 PM PDT 24
Finished Aug 06 07:44:42 PM PDT 24
Peak memory 201524 kb
Host smart-601983ba-eaec-4d21-9e6a-4f1f8e214d4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282376235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1282376235
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2663194187
Short name T789
Test name
Test status
Simulation time 389902476221 ps
CPU time 250.09 seconds
Started Aug 06 07:37:47 PM PDT 24
Finished Aug 06 07:41:57 PM PDT 24
Peak memory 201444 kb
Host smart-a6f4b95c-b257-4da2-a947-a9e9cdeb41ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663194187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2663194187
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1854627405
Short name T452
Test name
Test status
Simulation time 57352709999 ps
CPU time 226.35 seconds
Started Aug 06 07:37:45 PM PDT 24
Finished Aug 06 07:41:31 PM PDT 24
Peak memory 201796 kb
Host smart-f861cd05-05e5-4b4e-99ad-90aa49609f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854627405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1854627405
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.129356157
Short name T439
Test name
Test status
Simulation time 30927051331 ps
CPU time 37.28 seconds
Started Aug 06 07:37:45 PM PDT 24
Finished Aug 06 07:38:22 PM PDT 24
Peak memory 201316 kb
Host smart-acb97aa8-f5ce-4f68-91c9-f344f853dadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129356157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.129356157
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4246040153
Short name T97
Test name
Test status
Simulation time 3359380657 ps
CPU time 4.21 seconds
Started Aug 06 07:37:47 PM PDT 24
Finished Aug 06 07:37:51 PM PDT 24
Peak memory 201216 kb
Host smart-6e2bf415-7260-40ea-9e3c-3570f18cf56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246040153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4246040153
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2252337461
Short name T196
Test name
Test status
Simulation time 5870707710 ps
CPU time 3.95 seconds
Started Aug 06 07:37:46 PM PDT 24
Finished Aug 06 07:37:50 PM PDT 24
Peak memory 201408 kb
Host smart-6d0d0cd4-a5b1-4b2c-8139-42be9da0771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252337461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2252337461
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3926542638
Short name T321
Test name
Test status
Simulation time 372438509696 ps
CPU time 308.01 seconds
Started Aug 06 07:38:00 PM PDT 24
Finished Aug 06 07:43:08 PM PDT 24
Peak memory 201504 kb
Host smart-7b2c5cc0-c8a7-4bba-af35-ad56262224ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926542638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3926542638
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.6492848
Short name T581
Test name
Test status
Simulation time 45109883037 ps
CPU time 138.47 seconds
Started Aug 06 07:37:46 PM PDT 24
Finished Aug 06 07:40:04 PM PDT 24
Peak memory 210124 kb
Host smart-84977d0c-e734-4b2a-89f1-6955926d1d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6492848 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.6492848
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2901154577
Short name T552
Test name
Test status
Simulation time 441779644 ps
CPU time 0.75 seconds
Started Aug 06 07:38:01 PM PDT 24
Finished Aug 06 07:38:02 PM PDT 24
Peak memory 201200 kb
Host smart-35c0a954-25a0-4827-a6de-8ee0f42c3f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901154577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2901154577
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2959287081
Short name T163
Test name
Test status
Simulation time 163932463928 ps
CPU time 71.38 seconds
Started Aug 06 07:38:03 PM PDT 24
Finished Aug 06 07:39:14 PM PDT 24
Peak memory 201428 kb
Host smart-d19458b4-17ae-49b6-af67-c93f6684675b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959287081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2959287081
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3619248176
Short name T526
Test name
Test status
Simulation time 169122649687 ps
CPU time 405.71 seconds
Started Aug 06 07:38:03 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 201464 kb
Host smart-a2e5fbc5-ed00-47a2-a543-fb55335d3926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619248176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3619248176
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3018739102
Short name T182
Test name
Test status
Simulation time 161261225661 ps
CPU time 66.56 seconds
Started Aug 06 07:38:03 PM PDT 24
Finished Aug 06 07:39:10 PM PDT 24
Peak memory 201376 kb
Host smart-f2513c2d-0337-456f-8eac-bd546fc1a244
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018739102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3018739102
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.167161174
Short name T508
Test name
Test status
Simulation time 330639820870 ps
CPU time 209.62 seconds
Started Aug 06 07:38:04 PM PDT 24
Finished Aug 06 07:41:33 PM PDT 24
Peak memory 201444 kb
Host smart-62cd2eda-3991-45ea-8838-e19ac777c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167161174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.167161174
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1381399557
Short name T185
Test name
Test status
Simulation time 507162893494 ps
CPU time 171.66 seconds
Started Aug 06 07:38:01 PM PDT 24
Finished Aug 06 07:40:53 PM PDT 24
Peak memory 201484 kb
Host smart-ae8f020a-715e-4b08-9523-9fc863b28570
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381399557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1381399557
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3654763482
Short name T138
Test name
Test status
Simulation time 444723973531 ps
CPU time 881.81 seconds
Started Aug 06 07:38:04 PM PDT 24
Finished Aug 06 07:52:46 PM PDT 24
Peak memory 201396 kb
Host smart-33abc2a8-8ac6-48ab-abe4-83e5a03039c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654763482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3654763482
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2797730632
Short name T792
Test name
Test status
Simulation time 219744486377 ps
CPU time 446.12 seconds
Started Aug 06 07:38:01 PM PDT 24
Finished Aug 06 07:45:27 PM PDT 24
Peak memory 201452 kb
Host smart-6c52f2fc-63c0-43c3-9760-36acbbebef6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797730632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2797730632
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.788434242
Short name T733
Test name
Test status
Simulation time 133901901548 ps
CPU time 407.02 seconds
Started Aug 06 07:38:02 PM PDT 24
Finished Aug 06 07:44:49 PM PDT 24
Peak memory 201916 kb
Host smart-87258b64-55f7-4e07-a476-5ad5230f5f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788434242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.788434242
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.335800013
Short name T769
Test name
Test status
Simulation time 45445159059 ps
CPU time 28.05 seconds
Started Aug 06 07:38:02 PM PDT 24
Finished Aug 06 07:38:30 PM PDT 24
Peak memory 201300 kb
Host smart-1e970163-5346-4343-b22a-7f148f201e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335800013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.335800013
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1720469455
Short name T535
Test name
Test status
Simulation time 4483808979 ps
CPU time 5.75 seconds
Started Aug 06 07:38:02 PM PDT 24
Finished Aug 06 07:38:08 PM PDT 24
Peak memory 201360 kb
Host smart-ac3cc4f4-1c2b-4f8b-b35c-cc0c0230c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720469455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1720469455
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2577139036
Short name T368
Test name
Test status
Simulation time 6115706943 ps
CPU time 8.39 seconds
Started Aug 06 07:38:03 PM PDT 24
Finished Aug 06 07:38:12 PM PDT 24
Peak memory 201296 kb
Host smart-d3b6e4b0-13b5-44f4-92b6-0923a99bc800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577139036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2577139036
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.154372038
Short name T722
Test name
Test status
Simulation time 750911706647 ps
CPU time 552.69 seconds
Started Aug 06 07:38:02 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 212356 kb
Host smart-369378aa-2f98-4a93-a0f0-777bd43ec42f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154372038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
154372038
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3278591592
Short name T518
Test name
Test status
Simulation time 356727559309 ps
CPU time 196.92 seconds
Started Aug 06 07:38:01 PM PDT 24
Finished Aug 06 07:41:18 PM PDT 24
Peak memory 209808 kb
Host smart-069854a7-9e8b-47cf-a595-120e709682e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278591592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3278591592
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2263763798
Short name T449
Test name
Test status
Simulation time 340493167 ps
CPU time 1.43 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 201204 kb
Host smart-463d8ebd-8bd3-460a-8f83-a51f798a3208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263763798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2263763798
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.57797626
Short name T493
Test name
Test status
Simulation time 489358858665 ps
CPU time 1111.58 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 201512 kb
Host smart-99ff43c5-7183-44fc-aa55-f1d1337406c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57797626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.57797626
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.377257199
Short name T791
Test name
Test status
Simulation time 164255957537 ps
CPU time 397.77 seconds
Started Aug 06 07:32:18 PM PDT 24
Finished Aug 06 07:38:56 PM PDT 24
Peak memory 201488 kb
Host smart-f906707c-57a6-4215-96d1-5760d78eedac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377257199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.377257199
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.667252639
Short name T551
Test name
Test status
Simulation time 494991376137 ps
CPU time 276.61 seconds
Started Aug 06 07:32:13 PM PDT 24
Finished Aug 06 07:36:50 PM PDT 24
Peak memory 201384 kb
Host smart-aa4cb996-d97c-49e8-8197-f9ae254b385b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=667252639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.667252639
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2548920486
Short name T663
Test name
Test status
Simulation time 174435648324 ps
CPU time 68.56 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:33:32 PM PDT 24
Peak memory 201420 kb
Host smart-44d47452-87fe-4c2f-8d69-70b0738a7887
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548920486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2548920486
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1952245400
Short name T178
Test name
Test status
Simulation time 615683300763 ps
CPU time 371.83 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:38:35 PM PDT 24
Peak memory 201384 kb
Host smart-b61d1424-2194-4a39-a2fa-e508c787bef2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952245400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1952245400
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.544309604
Short name T438
Test name
Test status
Simulation time 99931674579 ps
CPU time 514.19 seconds
Started Aug 06 07:32:28 PM PDT 24
Finished Aug 06 07:41:02 PM PDT 24
Peak memory 201824 kb
Host smart-55cf0869-78e8-4ec3-80e4-17ad737d2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544309604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.544309604
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2726139401
Short name T499
Test name
Test status
Simulation time 43703835008 ps
CPU time 106.07 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:34:19 PM PDT 24
Peak memory 201320 kb
Host smart-75dde03b-06f8-4572-9197-1c20980a7af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726139401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2726139401
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.644637570
Short name T541
Test name
Test status
Simulation time 4049298670 ps
CPU time 2.92 seconds
Started Aug 06 07:32:31 PM PDT 24
Finished Aug 06 07:32:34 PM PDT 24
Peak memory 200524 kb
Host smart-47a13ce4-8193-4a2d-8898-51ffd0f4f376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644637570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.644637570
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.995252085
Short name T67
Test name
Test status
Simulation time 7708184108 ps
CPU time 5.16 seconds
Started Aug 06 07:32:22 PM PDT 24
Finished Aug 06 07:32:27 PM PDT 24
Peak memory 218224 kb
Host smart-59f00be3-356b-4dd6-bec3-243919dac3c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995252085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.995252085
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2747322513
Short name T152
Test name
Test status
Simulation time 6001275497 ps
CPU time 7.61 seconds
Started Aug 06 07:32:15 PM PDT 24
Finished Aug 06 07:32:23 PM PDT 24
Peak memory 201356 kb
Host smart-32e9bfb5-f65a-4f4a-b0f9-261730df8f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747322513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2747322513
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.916094228
Short name T224
Test name
Test status
Simulation time 157222656211 ps
CPU time 57.78 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:33:22 PM PDT 24
Peak memory 217236 kb
Host smart-b63d435b-2928-4b9e-82d1-8f7ac14d870d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916094228 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.916094228
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2812678919
Short name T765
Test name
Test status
Simulation time 503981027 ps
CPU time 1.86 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:38:20 PM PDT 24
Peak memory 201240 kb
Host smart-95453ecf-60f8-4644-9d0f-af32ba84e105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812678919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2812678919
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2196199726
Short name T523
Test name
Test status
Simulation time 205396024244 ps
CPU time 498.01 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:46:37 PM PDT 24
Peak memory 201392 kb
Host smart-46a65999-2f01-432d-91ab-aec43ffc515b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196199726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2196199726
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2275592503
Short name T575
Test name
Test status
Simulation time 395952414956 ps
CPU time 859.19 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:52:37 PM PDT 24
Peak memory 201476 kb
Host smart-f6081d37-4361-4fdf-9c30-7073d1378d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275592503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2275592503
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3136103628
Short name T560
Test name
Test status
Simulation time 163129703629 ps
CPU time 365.67 seconds
Started Aug 06 07:38:17 PM PDT 24
Finished Aug 06 07:44:23 PM PDT 24
Peak memory 201448 kb
Host smart-14bceed2-dfdf-4248-8431-a9df304991a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136103628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3136103628
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3677319322
Short name T626
Test name
Test status
Simulation time 330402979300 ps
CPU time 775.74 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 201444 kb
Host smart-e2963dd9-3cf1-45a9-9a88-bf4ca963a396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677319322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3677319322
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1956989036
Short name T600
Test name
Test status
Simulation time 332808227314 ps
CPU time 787.22 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:51:27 PM PDT 24
Peak memory 201448 kb
Host smart-787450fd-fdc6-4467-b15b-d289d23dbd7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956989036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1956989036
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.670736123
Short name T271
Test name
Test status
Simulation time 384193807412 ps
CPU time 544.05 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 201464 kb
Host smart-e5498b12-bb12-4851-8c19-186faf9d0470
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670736123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.670736123
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1271615189
Short name T421
Test name
Test status
Simulation time 205099206364 ps
CPU time 119.67 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:40:18 PM PDT 24
Peak memory 201424 kb
Host smart-ae3f8b79-9ae7-47d4-bc85-83cddaa72556
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271615189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1271615189
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2592462176
Short name T780
Test name
Test status
Simulation time 76397320325 ps
CPU time 272.56 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:42:51 PM PDT 24
Peak memory 202068 kb
Host smart-19310e88-21a8-43e9-9e3e-aaf4e339dc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592462176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2592462176
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2747554910
Short name T651
Test name
Test status
Simulation time 42511003371 ps
CPU time 22.79 seconds
Started Aug 06 07:38:17 PM PDT 24
Finished Aug 06 07:38:40 PM PDT 24
Peak memory 201356 kb
Host smart-cc548594-1616-49ba-b6e6-3e850786e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747554910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2747554910
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1651745868
Short name T550
Test name
Test status
Simulation time 3957265178 ps
CPU time 9.7 seconds
Started Aug 06 07:38:17 PM PDT 24
Finished Aug 06 07:38:27 PM PDT 24
Peak memory 201324 kb
Host smart-e3640146-e111-4220-ae66-500876d5a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651745868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1651745868
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.65234220
Short name T435
Test name
Test status
Simulation time 5670136890 ps
CPU time 3.93 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:38:23 PM PDT 24
Peak memory 201300 kb
Host smart-b68ec926-9dec-499b-9c4e-bb16f6d9b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65234220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.65234220
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2122971410
Short name T309
Test name
Test status
Simulation time 536514879565 ps
CPU time 1191.68 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:58:11 PM PDT 24
Peak memory 201444 kb
Host smart-db355843-ddf1-4626-9409-eb9b49c1c433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122971410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2122971410
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.185746140
Short name T417
Test name
Test status
Simulation time 359740477 ps
CPU time 1.01 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:38:33 PM PDT 24
Peak memory 201172 kb
Host smart-55f2d56a-58ee-4a19-818a-2b908a0be8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185746140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.185746140
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2497037603
Short name T609
Test name
Test status
Simulation time 162324330534 ps
CPU time 65.7 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:39:38 PM PDT 24
Peak memory 201404 kb
Host smart-4c44bb9d-e408-48f7-b4a4-f2c7a48a8c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497037603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2497037603
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1807070750
Short name T654
Test name
Test status
Simulation time 160727206458 ps
CPU time 97.08 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:39:55 PM PDT 24
Peak memory 201488 kb
Host smart-23247b3e-218f-4f1b-985d-932d9e2f200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807070750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1807070750
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.261903659
Short name T98
Test name
Test status
Simulation time 493744285192 ps
CPU time 924.67 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:53:43 PM PDT 24
Peak memory 201460 kb
Host smart-4ea077d6-78b1-43ef-83df-5a6babc68db7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=261903659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.261903659
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2333212744
Short name T140
Test name
Test status
Simulation time 327396209599 ps
CPU time 159.41 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:40:58 PM PDT 24
Peak memory 201392 kb
Host smart-6a803868-9b7b-48c8-a64b-edf90232c651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333212744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2333212744
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2467763868
Short name T147
Test name
Test status
Simulation time 166999110753 ps
CPU time 95.68 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:39:54 PM PDT 24
Peak memory 201372 kb
Host smart-e5a2b415-2a3f-4d54-9691-75beef779b8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467763868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2467763868
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2029611651
Short name T717
Test name
Test status
Simulation time 557186323170 ps
CPU time 301.66 seconds
Started Aug 06 07:38:19 PM PDT 24
Finished Aug 06 07:43:21 PM PDT 24
Peak memory 201444 kb
Host smart-a2f9224d-baeb-4648-af61-14be87a5ea3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029611651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2029611651
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.447432567
Short name T405
Test name
Test status
Simulation time 581334398501 ps
CPU time 1203.41 seconds
Started Aug 06 07:38:17 PM PDT 24
Finished Aug 06 07:58:20 PM PDT 24
Peak memory 201348 kb
Host smart-deae15ca-81c2-40f7-bc73-abbe3a2d5249
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447432567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.447432567
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4188834164
Short name T481
Test name
Test status
Simulation time 140557297186 ps
CPU time 552.05 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:47:45 PM PDT 24
Peak memory 201880 kb
Host smart-237fef30-0cd6-46d9-91fe-5a75b91e182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188834164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4188834164
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.326619176
Short name T193
Test name
Test status
Simulation time 29309283607 ps
CPU time 35.52 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:39:08 PM PDT 24
Peak memory 201312 kb
Host smart-59da0213-b14b-4211-acdf-5a87c5e1264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326619176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.326619176
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.137061453
Short name T442
Test name
Test status
Simulation time 4248239062 ps
CPU time 1.58 seconds
Started Aug 06 07:38:35 PM PDT 24
Finished Aug 06 07:38:36 PM PDT 24
Peak memory 201308 kb
Host smart-e7986ea8-bad8-40ae-b835-fa66c013eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137061453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.137061453
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2830511257
Short name T462
Test name
Test status
Simulation time 6091012215 ps
CPU time 4.82 seconds
Started Aug 06 07:38:18 PM PDT 24
Finished Aug 06 07:38:23 PM PDT 24
Peak memory 201252 kb
Host smart-640fcb34-4fc1-4692-9960-d65390e7d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830511257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2830511257
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.134553477
Short name T655
Test name
Test status
Simulation time 306791325839 ps
CPU time 849.91 seconds
Started Aug 06 07:38:34 PM PDT 24
Finished Aug 06 07:52:44 PM PDT 24
Peak memory 209968 kb
Host smart-78e91b8b-fe24-40c8-bbba-4aa04302d93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134553477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
134553477
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3620958158
Short name T43
Test name
Test status
Simulation time 77379356204 ps
CPU time 37.79 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:39:10 PM PDT 24
Peak memory 209724 kb
Host smart-bba338bb-7c9d-4151-a29b-c5762b1eb115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620958158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3620958158
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1797914371
Short name T490
Test name
Test status
Simulation time 456578270 ps
CPU time 0.84 seconds
Started Aug 06 07:38:31 PM PDT 24
Finished Aug 06 07:38:32 PM PDT 24
Peak memory 201236 kb
Host smart-f74df296-7311-4fc4-97cb-a72900e49e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797914371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1797914371
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1093051230
Short name T743
Test name
Test status
Simulation time 568806816426 ps
CPU time 162.05 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:41:15 PM PDT 24
Peak memory 201448 kb
Host smart-4667cc42-38d5-4850-b6b6-189065117c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093051230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1093051230
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.402994912
Short name T292
Test name
Test status
Simulation time 181870621512 ps
CPU time 200.64 seconds
Started Aug 06 07:38:35 PM PDT 24
Finished Aug 06 07:41:56 PM PDT 24
Peak memory 201464 kb
Host smart-72b57097-72ad-4e45-b3ef-85152e5009b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402994912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.402994912
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2683423943
Short name T579
Test name
Test status
Simulation time 494350106936 ps
CPU time 103.79 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:40:16 PM PDT 24
Peak memory 201508 kb
Host smart-e1ca9e5c-8978-419c-928e-4a7319fecb92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683423943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2683423943
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2846601574
Short name T130
Test name
Test status
Simulation time 495240223134 ps
CPU time 203.74 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:41:56 PM PDT 24
Peak memory 201448 kb
Host smart-f962b018-eaa6-4e4e-ab27-ad2e727f9785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846601574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2846601574
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3282494974
Short name T718
Test name
Test status
Simulation time 323510328665 ps
CPU time 226.94 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:42:20 PM PDT 24
Peak memory 201392 kb
Host smart-03391cd0-8e2c-4e83-a5d2-ad565d570836
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282494974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3282494974
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1515605790
Short name T198
Test name
Test status
Simulation time 555014759327 ps
CPU time 75.48 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:39:49 PM PDT 24
Peak memory 201452 kb
Host smart-edca0cd6-2c00-4795-86fa-5702522a189d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515605790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1515605790
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.13248189
Short name T714
Test name
Test status
Simulation time 604364668071 ps
CPU time 692.62 seconds
Started Aug 06 07:38:34 PM PDT 24
Finished Aug 06 07:50:07 PM PDT 24
Peak memory 201452 kb
Host smart-fec52264-34b8-41ac-ada0-c57d1444f620
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.a
dc_ctrl_filters_wakeup_fixed.13248189
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.4059106833
Short name T214
Test name
Test status
Simulation time 99878233194 ps
CPU time 538.47 seconds
Started Aug 06 07:38:34 PM PDT 24
Finished Aug 06 07:47:32 PM PDT 24
Peak memory 201864 kb
Host smart-02cad134-db3e-4559-a086-f5d6148f56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059106833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.4059106833
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.952223659
Short name T461
Test name
Test status
Simulation time 30522827327 ps
CPU time 67.01 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:39:39 PM PDT 24
Peak memory 201384 kb
Host smart-9156b00b-e916-4681-8fb4-5bfe1e52e9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952223659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.952223659
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3457165045
Short name T366
Test name
Test status
Simulation time 3044970096 ps
CPU time 3.87 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:38:37 PM PDT 24
Peak memory 201332 kb
Host smart-fbca70bb-c8b3-4502-82e1-507f3d5e28e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457165045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3457165045
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1232795031
Short name T6
Test name
Test status
Simulation time 6051000976 ps
CPU time 4.21 seconds
Started Aug 06 07:38:37 PM PDT 24
Finished Aug 06 07:38:41 PM PDT 24
Peak memory 201408 kb
Host smart-4f75b1eb-e6fd-4f82-b4b6-1ad848f9fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232795031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1232795031
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2605944972
Short name T262
Test name
Test status
Simulation time 200811073389 ps
CPU time 120.81 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:40:34 PM PDT 24
Peak memory 201424 kb
Host smart-1b64ae67-96dc-4e42-83f0-b6f26b4dcb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605944972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2605944972
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.579690500
Short name T477
Test name
Test status
Simulation time 23951515127 ps
CPU time 57.08 seconds
Started Aug 06 07:38:33 PM PDT 24
Finished Aug 06 07:39:30 PM PDT 24
Peak memory 209792 kb
Host smart-c33954c7-dc45-4e40-9eb0-f96c23232d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579690500 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.579690500
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2961678136
Short name T370
Test name
Test status
Simulation time 434177647 ps
CPU time 1.58 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:38:51 PM PDT 24
Peak memory 201116 kb
Host smart-d8a60a63-58eb-4859-86ea-7ca6c1785888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961678136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2961678136
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.647364249
Short name T613
Test name
Test status
Simulation time 174703413821 ps
CPU time 224.18 seconds
Started Aug 06 07:38:50 PM PDT 24
Finished Aug 06 07:42:34 PM PDT 24
Peak memory 201384 kb
Host smart-beb44de9-dea3-4e0d-a6f0-ad81d4f35c3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647364249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.647364249
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4046397143
Short name T553
Test name
Test status
Simulation time 164675994821 ps
CPU time 408.82 seconds
Started Aug 06 07:38:52 PM PDT 24
Finished Aug 06 07:45:41 PM PDT 24
Peak memory 201416 kb
Host smart-3b85f5b6-b2c9-4c5e-97f8-5b33e6b8705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046397143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4046397143
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2991681720
Short name T345
Test name
Test status
Simulation time 324522118318 ps
CPU time 751.17 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:51:20 PM PDT 24
Peak memory 201452 kb
Host smart-0cc45aff-9d8d-4cb9-9912-6525f0b21e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991681720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2991681720
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1162270253
Short name T174
Test name
Test status
Simulation time 162431600841 ps
CPU time 88.09 seconds
Started Aug 06 07:38:48 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 201492 kb
Host smart-6eaeba80-cb65-4446-bdd2-6452013e1a19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162270253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1162270253
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2184669375
Short name T254
Test name
Test status
Simulation time 333597907441 ps
CPU time 410.26 seconds
Started Aug 06 07:38:47 PM PDT 24
Finished Aug 06 07:45:38 PM PDT 24
Peak memory 201332 kb
Host smart-b944b421-db79-434d-8d62-bfa85ff6c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184669375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2184669375
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3209303563
Short name T494
Test name
Test status
Simulation time 488051163974 ps
CPU time 1151.02 seconds
Started Aug 06 07:38:50 PM PDT 24
Finished Aug 06 07:58:01 PM PDT 24
Peak memory 201372 kb
Host smart-f21568b9-12df-4011-b33a-e9f1544433b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209303563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3209303563
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3112819140
Short name T662
Test name
Test status
Simulation time 326134106919 ps
CPU time 398.9 seconds
Started Aug 06 07:38:48 PM PDT 24
Finished Aug 06 07:45:27 PM PDT 24
Peak memory 201396 kb
Host smart-0d50e256-2311-46b0-85df-068d7a3c3145
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112819140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3112819140
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1131664947
Short name T443
Test name
Test status
Simulation time 197168855163 ps
CPU time 486.51 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:46:56 PM PDT 24
Peak memory 201444 kb
Host smart-a4bf2fdd-fc11-46ea-af1f-eefca8f86cda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131664947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1131664947
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.608062800
Short name T433
Test name
Test status
Simulation time 100909469207 ps
CPU time 339.67 seconds
Started Aug 06 07:38:50 PM PDT 24
Finished Aug 06 07:44:30 PM PDT 24
Peak memory 202008 kb
Host smart-e4ce7077-18d1-4820-8b01-f8b1cf03e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608062800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.608062800
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1858472631
Short name T517
Test name
Test status
Simulation time 44114856480 ps
CPU time 103.51 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:40:33 PM PDT 24
Peak memory 201384 kb
Host smart-4fd1296f-17c7-40f5-ac27-4a16e54436c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858472631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1858472631
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3620813281
Short name T26
Test name
Test status
Simulation time 5239174240 ps
CPU time 2.87 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:38:52 PM PDT 24
Peak memory 201304 kb
Host smart-57b016ac-f8c0-42c3-a51f-7657ea9729c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620813281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3620813281
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3712750769
Short name T561
Test name
Test status
Simulation time 6022838675 ps
CPU time 14.85 seconds
Started Aug 06 07:38:32 PM PDT 24
Finished Aug 06 07:38:47 PM PDT 24
Peak memory 201360 kb
Host smart-52552bf8-3dae-4985-ad57-12ba47a2f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712750769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3712750769
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2522754878
Short name T39
Test name
Test status
Simulation time 13863969549 ps
CPU time 52.75 seconds
Started Aug 06 07:38:52 PM PDT 24
Finished Aug 06 07:39:45 PM PDT 24
Peak memory 201984 kb
Host smart-d2814921-f921-47c8-be8d-07f503d624d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522754878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2522754878
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1190512717
Short name T605
Test name
Test status
Simulation time 359144255 ps
CPU time 0.71 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:39:17 PM PDT 24
Peak memory 201156 kb
Host smart-4e0e34d3-e532-4d3a-9426-c0c319643b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190512717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1190512717
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2032081554
Short name T175
Test name
Test status
Simulation time 516379751207 ps
CPU time 1097.89 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:57:34 PM PDT 24
Peak memory 201456 kb
Host smart-414e1634-8b73-49c0-8008-ba3b06dada3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032081554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2032081554
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.603164917
Short name T226
Test name
Test status
Simulation time 496910393876 ps
CPU time 280.51 seconds
Started Aug 06 07:38:50 PM PDT 24
Finished Aug 06 07:43:30 PM PDT 24
Peak memory 201428 kb
Host smart-c9c665dd-edf8-4e18-b430-cabc305c18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603164917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.603164917
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1166567283
Short name T584
Test name
Test status
Simulation time 322739275330 ps
CPU time 663.38 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:49:52 PM PDT 24
Peak memory 201480 kb
Host smart-9b25d698-9dad-4112-88b2-799ba09b47dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166567283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1166567283
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3080660874
Short name T730
Test name
Test status
Simulation time 335340918825 ps
CPU time 754.83 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:51:24 PM PDT 24
Peak memory 201444 kb
Host smart-430a650b-bac4-4475-9157-2d699ac18ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080660874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3080660874
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.802004342
Short name T563
Test name
Test status
Simulation time 159388318713 ps
CPU time 32.67 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:39:22 PM PDT 24
Peak memory 201428 kb
Host smart-f887926a-b19c-4bad-b621-9f0e16943ccd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=802004342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.802004342
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1648585382
Short name T760
Test name
Test status
Simulation time 370870163947 ps
CPU time 856.72 seconds
Started Aug 06 07:38:50 PM PDT 24
Finished Aug 06 07:53:06 PM PDT 24
Peak memory 201420 kb
Host smart-59a9fb1f-c6e0-4c11-9e2b-5392a1520305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648585382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1648585382
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2810460271
Short name T606
Test name
Test status
Simulation time 398837914073 ps
CPU time 876.41 seconds
Started Aug 06 07:39:15 PM PDT 24
Finished Aug 06 07:53:51 PM PDT 24
Peak memory 201420 kb
Host smart-820d3b07-68e8-4af6-9cbf-678b9d504a89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810460271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2810460271
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3284081057
Short name T55
Test name
Test status
Simulation time 122744171212 ps
CPU time 663.45 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:50:19 PM PDT 24
Peak memory 201844 kb
Host smart-89ab077e-f1c8-4e4c-b122-6a33cd36b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284081057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3284081057
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.905960368
Short name T554
Test name
Test status
Simulation time 40898805352 ps
CPU time 99.88 seconds
Started Aug 06 07:39:15 PM PDT 24
Finished Aug 06 07:40:55 PM PDT 24
Peak memory 201388 kb
Host smart-13a16a32-beec-4d31-a67d-aece93ac7e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905960368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.905960368
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1057588022
Short name T776
Test name
Test status
Simulation time 4523202189 ps
CPU time 11.77 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:39:28 PM PDT 24
Peak memory 201344 kb
Host smart-f29dd740-3aa2-4c49-bdcd-1c9c7883b4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057588022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1057588022
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3204302322
Short name T527
Test name
Test status
Simulation time 5944741840 ps
CPU time 4.42 seconds
Started Aug 06 07:38:49 PM PDT 24
Finished Aug 06 07:38:54 PM PDT 24
Peak memory 201324 kb
Host smart-c83dc732-209a-4c0a-8473-46618a192834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204302322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3204302322
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4001429549
Short name T607
Test name
Test status
Simulation time 468205531946 ps
CPU time 640.86 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:49:57 PM PDT 24
Peak memory 209924 kb
Host smart-ed42c927-4788-4673-9d6a-72db07d204ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001429549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4001429549
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3961856678
Short name T625
Test name
Test status
Simulation time 57830458205 ps
CPU time 77.88 seconds
Started Aug 06 07:39:17 PM PDT 24
Finished Aug 06 07:40:35 PM PDT 24
Peak memory 210216 kb
Host smart-43616159-e1e0-4737-8239-cbdf2fd8c5a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961856678 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3961856678
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.96583718
Short name T548
Test name
Test status
Simulation time 434373770 ps
CPU time 0.89 seconds
Started Aug 06 07:39:50 PM PDT 24
Finished Aug 06 07:39:51 PM PDT 24
Peak memory 201260 kb
Host smart-10a37cd1-fb64-4bea-8de9-2fdfe89fe445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96583718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.96583718
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.113890104
Short name T287
Test name
Test status
Simulation time 503819777437 ps
CPU time 721.62 seconds
Started Aug 06 07:39:15 PM PDT 24
Finished Aug 06 07:51:17 PM PDT 24
Peak memory 201488 kb
Host smart-44475d21-38bb-440b-a533-7bed4a50b12b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113890104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.113890104
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4290185375
Short name T745
Test name
Test status
Simulation time 495033640403 ps
CPU time 306.05 seconds
Started Aug 06 07:39:15 PM PDT 24
Finished Aug 06 07:44:21 PM PDT 24
Peak memory 201464 kb
Host smart-b9d96917-936d-44d8-8360-bd13b52eca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290185375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4290185375
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1910360474
Short name T466
Test name
Test status
Simulation time 166579049455 ps
CPU time 186.6 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:42:22 PM PDT 24
Peak memory 201432 kb
Host smart-7f2a7100-c1eb-43de-abcc-e17466706fed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910360474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1910360474
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3116043834
Short name T478
Test name
Test status
Simulation time 164918653011 ps
CPU time 363.7 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:45:20 PM PDT 24
Peak memory 201400 kb
Host smart-3f8d7284-1d87-486d-b299-89956d52cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116043834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3116043834
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3009924002
Short name T376
Test name
Test status
Simulation time 159965717170 ps
CPU time 92.12 seconds
Started Aug 06 07:39:17 PM PDT 24
Finished Aug 06 07:40:49 PM PDT 24
Peak memory 201412 kb
Host smart-7f71686e-a401-486e-af45-11ebbf5a3688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009924002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3009924002
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.337607488
Short name T634
Test name
Test status
Simulation time 490979566029 ps
CPU time 295.07 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:44:11 PM PDT 24
Peak memory 201308 kb
Host smart-faeb1a92-c132-4d08-906b-1e9e0e87f489
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337607488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.337607488
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.825587648
Short name T374
Test name
Test status
Simulation time 401562057099 ps
CPU time 979.72 seconds
Started Aug 06 07:39:16 PM PDT 24
Finished Aug 06 07:55:36 PM PDT 24
Peak memory 201380 kb
Host smart-2aafab63-bb93-4ab3-8c84-32e4abe3a0d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825587648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.825587648
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.486107292
Short name T707
Test name
Test status
Simulation time 88414319054 ps
CPU time 303.84 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:44:50 PM PDT 24
Peak memory 201900 kb
Host smart-e7256084-b20a-4aba-aa83-398622b36b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486107292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.486107292
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1171640987
Short name T473
Test name
Test status
Simulation time 40570432316 ps
CPU time 48.48 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:40:38 PM PDT 24
Peak memory 201308 kb
Host smart-94b030bb-3f28-44be-95c6-17167c1ed933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171640987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1171640987
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3987822429
Short name T790
Test name
Test status
Simulation time 4691712464 ps
CPU time 3.34 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:39:50 PM PDT 24
Peak memory 201336 kb
Host smart-22bfc0ba-3ae6-4771-9b99-cb44056d7c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987822429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3987822429
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4139966270
Short name T715
Test name
Test status
Simulation time 6091446071 ps
CPU time 8.07 seconds
Started Aug 06 07:39:20 PM PDT 24
Finished Aug 06 07:39:28 PM PDT 24
Peak memory 201344 kb
Host smart-a893833c-f8f1-4aca-b1d0-f9b869a56e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139966270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4139966270
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2277785575
Short name T666
Test name
Test status
Simulation time 337988790238 ps
CPU time 758.4 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:52:24 PM PDT 24
Peak memory 201424 kb
Host smart-b4a4fa1a-0786-43ff-882f-5aee6d2a60c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277785575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2277785575
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2661943562
Short name T469
Test name
Test status
Simulation time 407505997 ps
CPU time 0.84 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:39:50 PM PDT 24
Peak memory 201192 kb
Host smart-77bc04d4-847b-4920-ba36-3304e670c478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661943562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2661943562
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2451072113
Short name T243
Test name
Test status
Simulation time 160544659382 ps
CPU time 371.47 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:46:01 PM PDT 24
Peak memory 201432 kb
Host smart-a1e21c9a-98b4-4736-b8cc-737d0f6d8c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451072113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2451072113
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.843679228
Short name T313
Test name
Test status
Simulation time 162733916409 ps
CPU time 95.74 seconds
Started Aug 06 07:39:48 PM PDT 24
Finished Aug 06 07:41:23 PM PDT 24
Peak memory 201412 kb
Host smart-9e92d76d-8753-4ef6-8a50-d4bb00f2e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843679228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.843679228
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.498388675
Short name T364
Test name
Test status
Simulation time 162474263789 ps
CPU time 183.44 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:42:49 PM PDT 24
Peak memory 201404 kb
Host smart-e9ece0f3-83b1-4ce6-ad4a-be1b17e51a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=498388675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.498388675
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1472998882
Short name T340
Test name
Test status
Simulation time 324179825208 ps
CPU time 187.64 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:42:54 PM PDT 24
Peak memory 201444 kb
Host smart-8df85552-7d59-4dc6-b2ce-fad7fe594223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472998882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1472998882
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1918043396
Short name T685
Test name
Test status
Simulation time 168638352359 ps
CPU time 99.22 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:41:28 PM PDT 24
Peak memory 201484 kb
Host smart-e613d10a-d2cc-4c2f-9da5-be10214d26a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918043396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1918043396
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1870006754
Short name T491
Test name
Test status
Simulation time 591005024653 ps
CPU time 1480.38 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 08:04:27 PM PDT 24
Peak memory 201424 kb
Host smart-924bd647-2e73-4f92-8b21-7e1ac7958f97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870006754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1870006754
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4052869825
Short name T177
Test name
Test status
Simulation time 110607365527 ps
CPU time 465.17 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:47:32 PM PDT 24
Peak memory 201884 kb
Host smart-0485fcba-f857-4d60-9184-32fd39b56f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052869825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4052869825
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3499584760
Short name T706
Test name
Test status
Simulation time 29241283220 ps
CPU time 14.39 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:40:00 PM PDT 24
Peak memory 201344 kb
Host smart-acb65568-2ca1-4472-a5aa-8dc62304cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499584760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3499584760
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3999074413
Short name T687
Test name
Test status
Simulation time 4213816583 ps
CPU time 5.33 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:39:54 PM PDT 24
Peak memory 201312 kb
Host smart-262af04d-f899-4944-8974-3dc90b24fe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999074413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3999074413
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1472165327
Short name T770
Test name
Test status
Simulation time 5825161251 ps
CPU time 14.55 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:40:01 PM PDT 24
Peak memory 201300 kb
Host smart-47479c1e-598e-4fe6-9600-e25cab7c3f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472165327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1472165327
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1135992509
Short name T289
Test name
Test status
Simulation time 415607731500 ps
CPU time 128.33 seconds
Started Aug 06 07:39:45 PM PDT 24
Finished Aug 06 07:41:53 PM PDT 24
Peak memory 201424 kb
Host smart-1ed01c14-bfd9-46d2-9f84-580862e3686b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135992509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1135992509
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1429523427
Short name T415
Test name
Test status
Simulation time 60061184215 ps
CPU time 120.42 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:41:48 PM PDT 24
Peak memory 209940 kb
Host smart-11a03551-bb05-42f5-a218-9e5f0ce5c8e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429523427 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1429523427
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.430942411
Short name T528
Test name
Test status
Simulation time 404328343 ps
CPU time 1.47 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:39:50 PM PDT 24
Peak memory 201192 kb
Host smart-875a8b2e-6167-4685-bee3-40a8ee6762d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430942411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.430942411
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.378793965
Short name T127
Test name
Test status
Simulation time 327433529313 ps
CPU time 734.65 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:52:04 PM PDT 24
Peak memory 201400 kb
Host smart-0a8a1ee3-455d-4cf7-adde-ad877aef4e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378793965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.378793965
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1478943041
Short name T349
Test name
Test status
Simulation time 501401752757 ps
CPU time 599.95 seconds
Started Aug 06 07:39:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 201468 kb
Host smart-ad6650b8-8ab9-42f8-8296-75cc110fb58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478943041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1478943041
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3972433187
Short name T758
Test name
Test status
Simulation time 165382589821 ps
CPU time 118.6 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:41:44 PM PDT 24
Peak memory 201480 kb
Host smart-0e5b9d70-6cd5-4f33-aac8-155e7e5cb5f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972433187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3972433187
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.579481366
Short name T255
Test name
Test status
Simulation time 485982224074 ps
CPU time 1117.61 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:58:25 PM PDT 24
Peak memory 201408 kb
Host smart-23788670-26ee-4eab-8877-d94b5863d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579481366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.579481366
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2627791493
Short name T423
Test name
Test status
Simulation time 330920802573 ps
CPU time 188.97 seconds
Started Aug 06 07:39:44 PM PDT 24
Finished Aug 06 07:42:53 PM PDT 24
Peak memory 201392 kb
Host smart-eb35863c-9b99-49b4-a513-ce7a0db0e813
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627791493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2627791493
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3316644609
Short name T604
Test name
Test status
Simulation time 198378820401 ps
CPU time 235.49 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:43:43 PM PDT 24
Peak memory 201416 kb
Host smart-5940f577-24fe-44d1-bf10-0c1109e0cdde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316644609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3316644609
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1271299256
Short name T357
Test name
Test status
Simulation time 61032764074 ps
CPU time 250.27 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:43:56 PM PDT 24
Peak memory 201832 kb
Host smart-d8cace48-42d4-41d6-a9dc-6ac1d3c260d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271299256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1271299256
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.441737702
Short name T181
Test name
Test status
Simulation time 30491791514 ps
CPU time 16.55 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:40:03 PM PDT 24
Peak memory 201356 kb
Host smart-57bbf397-acf4-472c-9852-80f2a3df9c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441737702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.441737702
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1478716201
Short name T394
Test name
Test status
Simulation time 3670334881 ps
CPU time 1.49 seconds
Started Aug 06 07:39:45 PM PDT 24
Finished Aug 06 07:39:47 PM PDT 24
Peak memory 201300 kb
Host smart-be6c38a0-6ef3-4113-aada-f048885cbea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478716201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1478716201
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3072262727
Short name T728
Test name
Test status
Simulation time 5734199779 ps
CPU time 6.34 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:39:52 PM PDT 24
Peak memory 201352 kb
Host smart-b5fa338d-b890-4e5b-b631-f9e09b4f7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072262727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3072262727
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3467307377
Short name T241
Test name
Test status
Simulation time 221092709170 ps
CPU time 139.49 seconds
Started Aug 06 07:39:48 PM PDT 24
Finished Aug 06 07:42:07 PM PDT 24
Peak memory 201392 kb
Host smart-006ee533-4964-4ea9-8d20-04b1e4b4c4da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467307377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3467307377
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.701141424
Short name T274
Test name
Test status
Simulation time 128480719014 ps
CPU time 187.66 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:42:56 PM PDT 24
Peak memory 211168 kb
Host smart-128c1bd8-993c-4f80-aa99-5755b1f9f71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701141424 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.701141424
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3848258776
Short name T647
Test name
Test status
Simulation time 465630202 ps
CPU time 0.85 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:40:07 PM PDT 24
Peak memory 201280 kb
Host smart-eec975b0-1273-43a5-88b1-9418efa3ff8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848258776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3848258776
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2493909272
Short name T311
Test name
Test status
Simulation time 182058634019 ps
CPU time 415 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:47:04 PM PDT 24
Peak memory 201348 kb
Host smart-d5c0b493-004b-4bad-bf3d-85ed4fd0b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493909272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2493909272
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2631143501
Short name T79
Test name
Test status
Simulation time 163781715356 ps
CPU time 381.41 seconds
Started Aug 06 07:39:47 PM PDT 24
Finished Aug 06 07:46:09 PM PDT 24
Peak memory 201460 kb
Host smart-b4c1087f-24eb-4147-8fba-0937fa79a87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631143501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2631143501
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2636870302
Short name T485
Test name
Test status
Simulation time 164471997914 ps
CPU time 100.41 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:41:47 PM PDT 24
Peak memory 201452 kb
Host smart-cd649d35-5d5f-43c3-908a-6e417fd1a0a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636870302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2636870302
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2776361194
Short name T203
Test name
Test status
Simulation time 491545810265 ps
CPU time 293.21 seconds
Started Aug 06 07:39:46 PM PDT 24
Finished Aug 06 07:44:39 PM PDT 24
Peak memory 201384 kb
Host smart-344f61ac-c234-46f6-8ada-3f27dcda0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776361194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2776361194
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2782725579
Short name T398
Test name
Test status
Simulation time 328959113197 ps
CPU time 354.47 seconds
Started Aug 06 07:39:49 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 201432 kb
Host smart-9e1f905e-13e6-4aff-ae4b-2e9b945538c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782725579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2782725579
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.452094510
Short name T5
Test name
Test status
Simulation time 184258497131 ps
CPU time 433.48 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:47:19 PM PDT 24
Peak memory 201444 kb
Host smart-fd12d3ab-6772-4d7e-89b6-40a8322bb0b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452094510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.452094510
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3627918899
Short name T759
Test name
Test status
Simulation time 204021542348 ps
CPU time 93.98 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:41:39 PM PDT 24
Peak memory 201412 kb
Host smart-1e702c68-c640-42df-b1f0-eb8863dbd493
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627918899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3627918899
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3813158660
Short name T699
Test name
Test status
Simulation time 108790298402 ps
CPU time 564.26 seconds
Started Aug 06 07:40:08 PM PDT 24
Finished Aug 06 07:49:32 PM PDT 24
Peak memory 201876 kb
Host smart-6e53aec8-d462-440e-afe8-6ff801be77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813158660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3813158660
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1092088383
Short name T388
Test name
Test status
Simulation time 29656355658 ps
CPU time 38.01 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:40:47 PM PDT 24
Peak memory 201284 kb
Host smart-981b1d2c-c0e5-4f14-b3c5-536c994ccdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092088383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1092088383
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3803992451
Short name T618
Test name
Test status
Simulation time 3746761957 ps
CPU time 8.48 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:40:14 PM PDT 24
Peak memory 201312 kb
Host smart-8a911f0b-a8eb-425c-8ecb-ccdedda2e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803992451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3803992451
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1488441314
Short name T410
Test name
Test status
Simulation time 6000412140 ps
CPU time 6.3 seconds
Started Aug 06 07:39:45 PM PDT 24
Finished Aug 06 07:39:52 PM PDT 24
Peak memory 201308 kb
Host smart-1c2be02b-46f6-4832-8997-c53df4183b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488441314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1488441314
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.172338924
Short name T24
Test name
Test status
Simulation time 760772720882 ps
CPU time 204.44 seconds
Started Aug 06 07:40:08 PM PDT 24
Finished Aug 06 07:43:32 PM PDT 24
Peak memory 209684 kb
Host smart-a36854da-6b31-4f3f-a6be-4eb6bfc389ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172338924 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.172338924
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.915891730
Short name T16
Test name
Test status
Simulation time 538550200 ps
CPU time 0.95 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:40:06 PM PDT 24
Peak memory 201244 kb
Host smart-d49fe78d-3ccb-4543-a43a-b14400f972d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915891730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.915891730
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.383146573
Short name T99
Test name
Test status
Simulation time 173779408926 ps
CPU time 100.32 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:41:46 PM PDT 24
Peak memory 201492 kb
Host smart-4ca3e36c-03e0-414f-8850-096f006268be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383146573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.383146573
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1870228959
Short name T276
Test name
Test status
Simulation time 512898392349 ps
CPU time 164.16 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:42:49 PM PDT 24
Peak memory 201476 kb
Host smart-a2926b5a-da47-4054-9bfd-bd0912a8eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870228959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1870228959
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2124685015
Short name T562
Test name
Test status
Simulation time 165758948353 ps
CPU time 78.45 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:41:24 PM PDT 24
Peak memory 201496 kb
Host smart-e8d506e0-3fbb-4704-8964-8b6c684993f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124685015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2124685015
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3953338702
Short name T464
Test name
Test status
Simulation time 159123052413 ps
CPU time 180.64 seconds
Started Aug 06 07:40:04 PM PDT 24
Finished Aug 06 07:43:05 PM PDT 24
Peak memory 201500 kb
Host smart-65bbf860-e280-4a57-8794-3c1f53e5c28a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953338702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3953338702
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3301388359
Short name T599
Test name
Test status
Simulation time 165647806156 ps
CPU time 350.25 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:45:59 PM PDT 24
Peak memory 201344 kb
Host smart-73e618cf-b00d-4889-85fd-7b9c899030f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301388359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3301388359
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1893880069
Short name T470
Test name
Test status
Simulation time 484968693657 ps
CPU time 290.67 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:44:56 PM PDT 24
Peak memory 201404 kb
Host smart-619fc422-e113-4866-8fc2-f9b0d766a92f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893880069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1893880069
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1697233429
Short name T782
Test name
Test status
Simulation time 354582820453 ps
CPU time 170.62 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:42:56 PM PDT 24
Peak memory 201368 kb
Host smart-0a17777f-58dd-451c-9b3b-8eee0ef75bb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697233429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1697233429
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.4258597325
Short name T641
Test name
Test status
Simulation time 594610727824 ps
CPU time 1296.54 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 08:01:46 PM PDT 24
Peak memory 201496 kb
Host smart-b9be7bb4-a74f-4925-88e2-e7bc72b1d21f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258597325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.4258597325
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3455595258
Short name T377
Test name
Test status
Simulation time 25248941569 ps
CPU time 51.61 seconds
Started Aug 06 07:40:05 PM PDT 24
Finished Aug 06 07:40:57 PM PDT 24
Peak memory 201324 kb
Host smart-2b916784-bcca-48d7-b35f-0873f1ac85f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455595258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3455595258
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1889063713
Short name T648
Test name
Test status
Simulation time 4977566554 ps
CPU time 2.18 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:40:11 PM PDT 24
Peak memory 201328 kb
Host smart-e6e0d4d6-2051-4ada-a8a4-4661e7092dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889063713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1889063713
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1404014525
Short name T623
Test name
Test status
Simulation time 5929368551 ps
CPU time 7.76 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:40:17 PM PDT 24
Peak memory 201336 kb
Host smart-935c70cb-212e-4c83-844c-27a76cfb3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404014525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1404014525
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1084454664
Short name T285
Test name
Test status
Simulation time 391117651173 ps
CPU time 81.38 seconds
Started Aug 06 07:40:06 PM PDT 24
Finished Aug 06 07:41:28 PM PDT 24
Peak memory 201396 kb
Host smart-b8260222-5e44-4063-9411-9e722525f5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084454664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1084454664
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.757929664
Short name T126
Test name
Test status
Simulation time 315483375743 ps
CPU time 254.79 seconds
Started Aug 06 07:40:09 PM PDT 24
Finished Aug 06 07:44:24 PM PDT 24
Peak memory 210108 kb
Host smart-1560122a-cc26-4adc-9035-4d88b90a66b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757929664 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.757929664
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2435350425
Short name T653
Test name
Test status
Simulation time 502137980 ps
CPU time 0.83 seconds
Started Aug 06 07:32:26 PM PDT 24
Finished Aug 06 07:32:27 PM PDT 24
Peak memory 201228 kb
Host smart-127afd7f-303e-49e1-a0b5-bb742d0d7980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435350425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2435350425
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.250993365
Short name T30
Test name
Test status
Simulation time 187458043582 ps
CPU time 112.25 seconds
Started Aug 06 07:32:25 PM PDT 24
Finished Aug 06 07:34:17 PM PDT 24
Peak memory 200684 kb
Host smart-2409eccb-c584-4ef8-b085-f82cf546c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250993365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.250993365
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.894590668
Short name T132
Test name
Test status
Simulation time 494112168556 ps
CPU time 1085.13 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:50:30 PM PDT 24
Peak memory 201528 kb
Host smart-0f2519eb-2acb-47a8-abe5-db4d3f692b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894590668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.894590668
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1520470897
Short name T772
Test name
Test status
Simulation time 167816159699 ps
CPU time 48.11 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:33:13 PM PDT 24
Peak memory 201412 kb
Host smart-5d47f5f0-c4af-4029-9387-afbfa5b9ea6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520470897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1520470897
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3669949777
Short name T172
Test name
Test status
Simulation time 489711281267 ps
CPU time 1025.22 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:49:28 PM PDT 24
Peak memory 201448 kb
Host smart-bd551831-c9e3-440d-8255-bbfe04b7b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669949777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3669949777
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2062449398
Short name T660
Test name
Test status
Simulation time 490949870488 ps
CPU time 1070.26 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:50:14 PM PDT 24
Peak memory 201420 kb
Host smart-f441c77d-0d2a-4898-a0ac-408388ac500e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062449398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2062449398
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1498177068
Short name T157
Test name
Test status
Simulation time 364516125541 ps
CPU time 198.39 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:35:51 PM PDT 24
Peak memory 201440 kb
Host smart-e4b0195f-1445-4f46-aeb6-d4ff2c3bdcb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498177068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1498177068
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.836689206
Short name T637
Test name
Test status
Simulation time 404215098387 ps
CPU time 926.28 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:47:59 PM PDT 24
Peak memory 201420 kb
Host smart-b8389b9d-cdbd-4377-bcb8-ada2a5a622a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836689206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.836689206
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1697970458
Short name T431
Test name
Test status
Simulation time 119152687406 ps
CPU time 606.77 seconds
Started Aug 06 07:32:24 PM PDT 24
Finished Aug 06 07:42:31 PM PDT 24
Peak memory 201828 kb
Host smart-250db6ed-20aa-4ec6-a504-977c7fd9286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697970458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1697970458
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2422947500
Short name T731
Test name
Test status
Simulation time 28964064967 ps
CPU time 57.4 seconds
Started Aug 06 07:32:25 PM PDT 24
Finished Aug 06 07:33:22 PM PDT 24
Peak memory 201312 kb
Host smart-37f11690-a903-46b1-9320-16c03e678204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422947500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2422947500
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2954344723
Short name T616
Test name
Test status
Simulation time 3351315041 ps
CPU time 2.33 seconds
Started Aug 06 07:32:31 PM PDT 24
Finished Aug 06 07:32:34 PM PDT 24
Peak memory 201312 kb
Host smart-c6ddc62a-cb98-4fd3-8c72-c8812015c80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954344723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2954344723
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.883718697
Short name T762
Test name
Test status
Simulation time 5942416590 ps
CPU time 13.63 seconds
Started Aug 06 07:32:31 PM PDT 24
Finished Aug 06 07:32:45 PM PDT 24
Peak memory 201336 kb
Host smart-18a7257f-0c12-4137-9268-dcfab655cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883718697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.883718697
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2374323616
Short name T22
Test name
Test status
Simulation time 148320270128 ps
CPU time 163.42 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:35:07 PM PDT 24
Peak memory 210256 kb
Host smart-c1483109-3648-4b7d-969c-941472cc3589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374323616 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2374323616
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4288333236
Short name T747
Test name
Test status
Simulation time 489607946 ps
CPU time 0.76 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:32:42 PM PDT 24
Peak memory 201224 kb
Host smart-d7506e40-2c35-4262-9d8d-988931855e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288333236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4288333236
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1224378204
Short name T341
Test name
Test status
Simulation time 176338781572 ps
CPU time 49.42 seconds
Started Aug 06 07:32:26 PM PDT 24
Finished Aug 06 07:33:16 PM PDT 24
Peak memory 201368 kb
Host smart-edcbd8fd-4a2a-45dd-bf9b-6a7fdd2c447a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224378204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1224378204
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3924841832
Short name T31
Test name
Test status
Simulation time 167263430937 ps
CPU time 404.23 seconds
Started Aug 06 07:32:31 PM PDT 24
Finished Aug 06 07:39:16 PM PDT 24
Peak memory 201436 kb
Host smart-4a8f55f6-6241-436d-a9db-dbc2e8afeea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924841832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3924841832
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3444378578
Short name T612
Test name
Test status
Simulation time 484281615227 ps
CPU time 312.45 seconds
Started Aug 06 07:32:25 PM PDT 24
Finished Aug 06 07:37:38 PM PDT 24
Peak memory 201456 kb
Host smart-adf97120-aae6-4e7a-9dfa-8b17586eabdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444378578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3444378578
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.825794991
Short name T577
Test name
Test status
Simulation time 499584850142 ps
CPU time 1103.85 seconds
Started Aug 06 07:32:25 PM PDT 24
Finished Aug 06 07:50:49 PM PDT 24
Peak memory 201524 kb
Host smart-42d55405-2271-4678-a449-d7d934ce849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825794991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.825794991
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2596537283
Short name T768
Test name
Test status
Simulation time 493013437695 ps
CPU time 1065.69 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:50:09 PM PDT 24
Peak memory 201424 kb
Host smart-1b3f6655-022a-4551-96ad-816b8e73a5fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596537283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2596537283
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3212853540
Short name T143
Test name
Test status
Simulation time 572262803431 ps
CPU time 271.04 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:36:55 PM PDT 24
Peak memory 201464 kb
Host smart-77a6f5c9-5b85-4d8c-93b7-4a5835c7e680
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212853540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3212853540
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1337738996
Short name T413
Test name
Test status
Simulation time 400426710396 ps
CPU time 233.74 seconds
Started Aug 06 07:32:33 PM PDT 24
Finished Aug 06 07:36:27 PM PDT 24
Peak memory 201428 kb
Host smart-6849c29f-c38f-480a-9569-d10d0329f32b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337738996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1337738996
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.771621660
Short name T50
Test name
Test status
Simulation time 95646427887 ps
CPU time 409.93 seconds
Started Aug 06 07:32:44 PM PDT 24
Finished Aug 06 07:39:34 PM PDT 24
Peak memory 201880 kb
Host smart-6542fe12-0449-4d5d-92e0-28d07cc70987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771621660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.771621660
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.313993097
Short name T404
Test name
Test status
Simulation time 42705330471 ps
CPU time 26.5 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:33:08 PM PDT 24
Peak memory 201292 kb
Host smart-96ce725a-4766-48cd-87b9-68f07cc0e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313993097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.313993097
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1897663173
Short name T456
Test name
Test status
Simulation time 3175982389 ps
CPU time 3.86 seconds
Started Aug 06 07:32:25 PM PDT 24
Finished Aug 06 07:32:28 PM PDT 24
Peak memory 201356 kb
Host smart-c605045f-b69d-4180-a14f-fab42b021195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897663173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1897663173
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4244897959
Short name T689
Test name
Test status
Simulation time 5716760628 ps
CPU time 3.77 seconds
Started Aug 06 07:32:23 PM PDT 24
Finished Aug 06 07:32:26 PM PDT 24
Peak memory 201352 kb
Host smart-82fb8340-7778-44ab-b773-e97a7695c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244897959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4244897959
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1106058934
Short name T361
Test name
Test status
Simulation time 71885961102 ps
CPU time 86.62 seconds
Started Aug 06 07:32:41 PM PDT 24
Finished Aug 06 07:34:08 PM PDT 24
Peak memory 201344 kb
Host smart-da168999-840b-48ab-878e-f61ef150e8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106058934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1106058934
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.690239031
Short name T86
Test name
Test status
Simulation time 76972668120 ps
CPU time 44.25 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:33:27 PM PDT 24
Peak memory 210192 kb
Host smart-767e0173-8438-4b12-b50c-2380fd707ee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690239031 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.690239031
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.443639725
Short name T424
Test name
Test status
Simulation time 637119969 ps
CPU time 0.7 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:32:43 PM PDT 24
Peak memory 201228 kb
Host smart-6410f90a-cbb8-41c5-9110-9d4c132b64b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443639725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.443639725
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2998873725
Short name T784
Test name
Test status
Simulation time 488753339369 ps
CPU time 1097.44 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:51:01 PM PDT 24
Peak memory 201448 kb
Host smart-ff98f841-dfc0-4d5f-b694-0eb27961284f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998873725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2998873725
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2157103830
Short name T253
Test name
Test status
Simulation time 162331225606 ps
CPU time 153.87 seconds
Started Aug 06 07:32:45 PM PDT 24
Finished Aug 06 07:35:19 PM PDT 24
Peak memory 201188 kb
Host smart-b9572021-4c13-4662-9089-89008aaf7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157103830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2157103830
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1729003128
Short name T189
Test name
Test status
Simulation time 329467247456 ps
CPU time 819.41 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:46:21 PM PDT 24
Peak memory 201440 kb
Host smart-198132fc-8e2b-4b24-9b81-8882ac87f13a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729003128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1729003128
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3815167153
Short name T251
Test name
Test status
Simulation time 328444130295 ps
CPU time 780.71 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:45:44 PM PDT 24
Peak memory 201416 kb
Host smart-94192b67-578d-438c-b202-6fbbc43ce789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815167153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3815167153
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1965506599
Short name T591
Test name
Test status
Simulation time 489746628564 ps
CPU time 275.2 seconds
Started Aug 06 07:32:47 PM PDT 24
Finished Aug 06 07:37:22 PM PDT 24
Peak memory 201456 kb
Host smart-b45ecae0-57b3-4f79-9912-ae572c5fcf6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965506599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1965506599
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3805537679
Short name T343
Test name
Test status
Simulation time 362080252813 ps
CPU time 858.91 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:47:01 PM PDT 24
Peak memory 201444 kb
Host smart-1405a72c-523e-4aa6-add2-02a987366114
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805537679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3805537679
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1770766138
Short name T565
Test name
Test status
Simulation time 403341989071 ps
CPU time 936.29 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:48:18 PM PDT 24
Peak memory 201520 kb
Host smart-25e56058-62bb-4d09-9be2-a213cbe1ac63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770766138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1770766138
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1725933215
Short name T629
Test name
Test status
Simulation time 89321577720 ps
CPU time 315.14 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:37:57 PM PDT 24
Peak memory 201788 kb
Host smart-48473e4d-bb8e-4444-94df-3ec897d89869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725933215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1725933215
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1372791521
Short name T453
Test name
Test status
Simulation time 36014291235 ps
CPU time 22.81 seconds
Started Aug 06 07:32:41 PM PDT 24
Finished Aug 06 07:33:04 PM PDT 24
Peak memory 201360 kb
Host smart-89805ec9-b781-4152-aaac-7f27515f6fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372791521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1372791521
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2267927147
Short name T619
Test name
Test status
Simulation time 3447003867 ps
CPU time 8.47 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:32:52 PM PDT 24
Peak memory 201344 kb
Host smart-2a3e6edf-fd33-4bd9-b32d-50ac5975595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267927147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2267927147
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3705687305
Short name T672
Test name
Test status
Simulation time 5736254796 ps
CPU time 14.18 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:32:56 PM PDT 24
Peak memory 201384 kb
Host smart-df543330-311e-4cb5-a6df-f25158e08066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705687305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3705687305
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.527061154
Short name T246
Test name
Test status
Simulation time 173071813938 ps
CPU time 191.2 seconds
Started Aug 06 07:32:47 PM PDT 24
Finished Aug 06 07:35:58 PM PDT 24
Peak memory 201452 kb
Host smart-4e10fa66-c03e-404b-a1dd-c4212ef72204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527061154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.527061154
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1392644891
Short name T46
Test name
Test status
Simulation time 123915800609 ps
CPU time 187.84 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:35:50 PM PDT 24
Peak memory 217380 kb
Host smart-e3775bdd-c691-438e-8412-dd880abf7444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392644891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1392644891
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1807562339
Short name T698
Test name
Test status
Simulation time 368809854 ps
CPU time 1.43 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:33:00 PM PDT 24
Peak memory 201240 kb
Host smart-1a2066de-f57f-46d1-8e39-811e7a2b711c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807562339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1807562339
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1638206547
Short name T161
Test name
Test status
Simulation time 171314049377 ps
CPU time 103.66 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:34:26 PM PDT 24
Peak memory 201420 kb
Host smart-bef5cda9-ee20-4400-87c9-304f4157a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638206547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1638206547
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3337980049
Short name T327
Test name
Test status
Simulation time 484840032237 ps
CPU time 122.98 seconds
Started Aug 06 07:32:44 PM PDT 24
Finished Aug 06 07:34:47 PM PDT 24
Peak memory 201544 kb
Host smart-dff4674b-aaf8-4ffe-8c5d-4a7969166f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337980049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3337980049
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.55842759
Short name T679
Test name
Test status
Simulation time 499668203718 ps
CPU time 1118.25 seconds
Started Aug 06 07:32:44 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 201360 kb
Host smart-0871f976-6601-41f0-8b83-96d53e304958
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55842759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_
fixed.55842759
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.7761989
Short name T348
Test name
Test status
Simulation time 325351568156 ps
CPU time 378.83 seconds
Started Aug 06 07:32:41 PM PDT 24
Finished Aug 06 07:39:00 PM PDT 24
Peak memory 201464 kb
Host smart-a310a0a6-7895-4776-b6a3-c60516b0cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7761989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.7761989
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2665323219
Short name T80
Test name
Test status
Simulation time 159971252127 ps
CPU time 360.45 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:38:42 PM PDT 24
Peak memory 201348 kb
Host smart-bf4bc2b2-98cc-4485-b2ee-d8c403f410a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665323219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2665323219
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2466145710
Short name T162
Test name
Test status
Simulation time 163214961587 ps
CPU time 81.72 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:34:05 PM PDT 24
Peak memory 201492 kb
Host smart-b71e10e4-9982-4561-bcf5-da20bbdaa90d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466145710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2466145710
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1571471699
Short name T27
Test name
Test status
Simulation time 195035414612 ps
CPU time 81.7 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:34:05 PM PDT 24
Peak memory 201464 kb
Host smart-0a884833-2df0-4bd5-b068-df1f9a3d91d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571471699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1571471699
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1846779014
Short name T85
Test name
Test status
Simulation time 35375258316 ps
CPU time 42.64 seconds
Started Aug 06 07:32:40 PM PDT 24
Finished Aug 06 07:33:23 PM PDT 24
Peak memory 201336 kb
Host smart-1f4b90ef-e311-4744-9156-a01c4110da23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846779014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1846779014
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4274766370
Short name T657
Test name
Test status
Simulation time 3768009908 ps
CPU time 10.25 seconds
Started Aug 06 07:32:45 PM PDT 24
Finished Aug 06 07:32:55 PM PDT 24
Peak memory 200984 kb
Host smart-cebe688f-0063-4a86-8e13-5099897a5f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274766370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4274766370
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1911659976
Short name T482
Test name
Test status
Simulation time 5979842924 ps
CPU time 4.14 seconds
Started Aug 06 07:32:44 PM PDT 24
Finished Aug 06 07:32:49 PM PDT 24
Peak memory 201296 kb
Host smart-5d085d42-38c8-4718-bad8-d4c0eba13211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911659976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1911659976
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.480204710
Short name T36
Test name
Test status
Simulation time 168569666365 ps
CPU time 29.83 seconds
Started Aug 06 07:32:43 PM PDT 24
Finished Aug 06 07:33:13 PM PDT 24
Peak memory 201400 kb
Host smart-e68ed8d3-72cc-456d-b968-d7bfc93f5814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480204710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.480204710
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1601999553
Short name T20
Test name
Test status
Simulation time 532123169739 ps
CPU time 308.97 seconds
Started Aug 06 07:32:42 PM PDT 24
Finished Aug 06 07:37:51 PM PDT 24
Peak memory 210188 kb
Host smart-25d1b986-8f0c-4605-b355-2d75f022e254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601999553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1601999553
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2961936345
Short name T524
Test name
Test status
Simulation time 542425336 ps
CPU time 0.76 seconds
Started Aug 06 07:33:03 PM PDT 24
Finished Aug 06 07:33:04 PM PDT 24
Peak memory 201232 kb
Host smart-ec391007-2ebe-43e5-8874-a21afb0d117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961936345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2961936345
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.163408006
Short name T674
Test name
Test status
Simulation time 204559393586 ps
CPU time 125.55 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:35:06 PM PDT 24
Peak memory 201412 kb
Host smart-5bd82bd9-a48a-4a74-b2c0-a65c2f2e2f36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163408006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.163408006
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4128399360
Short name T704
Test name
Test status
Simulation time 493190458251 ps
CPU time 619.84 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:43:17 PM PDT 24
Peak memory 201388 kb
Host smart-54d5bbd2-1e8b-4488-a43e-ece65e4366c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128399360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4128399360
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2480571714
Short name T263
Test name
Test status
Simulation time 495293245130 ps
CPU time 1070.01 seconds
Started Aug 06 07:32:56 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 201424 kb
Host smart-a3dd277f-05d9-49b3-82e6-61f93670839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480571714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2480571714
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3295131098
Short name T183
Test name
Test status
Simulation time 503449819485 ps
CPU time 267.19 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:37:24 PM PDT 24
Peak memory 201404 kb
Host smart-cfa9f96e-db8a-46c2-9ff1-7d63a0d76a4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295131098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3295131098
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3357989139
Short name T145
Test name
Test status
Simulation time 524634715485 ps
CPU time 262.84 seconds
Started Aug 06 07:32:57 PM PDT 24
Finished Aug 06 07:37:20 PM PDT 24
Peak memory 201408 kb
Host smart-28905b6b-5ce9-4e3c-9dbd-c57594eee4f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357989139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3357989139
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.840758278
Short name T483
Test name
Test status
Simulation time 606333062064 ps
CPU time 1063.55 seconds
Started Aug 06 07:32:55 PM PDT 24
Finished Aug 06 07:50:39 PM PDT 24
Peak memory 201372 kb
Host smart-77a6c0d9-1d6b-41e3-ac3b-aee6e0aad2db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840758278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.840758278
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2290363376
Short name T732
Test name
Test status
Simulation time 91685104128 ps
CPU time 299.25 seconds
Started Aug 06 07:33:01 PM PDT 24
Finished Aug 06 07:38:01 PM PDT 24
Peak memory 202016 kb
Host smart-977fc10d-36c5-44a8-9b79-83f0e4ef5384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290363376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2290363376
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.137989869
Short name T403
Test name
Test status
Simulation time 42145440584 ps
CPU time 27.84 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:33:28 PM PDT 24
Peak memory 201324 kb
Host smart-d6cb37fb-92bd-48a7-92c9-6f7f9d99f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137989869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.137989869
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2985455581
Short name T588
Test name
Test status
Simulation time 3173762607 ps
CPU time 7.34 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:33:08 PM PDT 24
Peak memory 201312 kb
Host smart-a6b33673-6a47-4ee9-825f-9ec4ca0b5d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985455581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2985455581
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.331848753
Short name T531
Test name
Test status
Simulation time 5844639540 ps
CPU time 2.04 seconds
Started Aug 06 07:32:58 PM PDT 24
Finished Aug 06 07:33:00 PM PDT 24
Peak memory 201416 kb
Host smart-f6dbbe81-0155-4417-b085-2f10abff12e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331848753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.331848753
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4238092503
Short name T280
Test name
Test status
Simulation time 364172528742 ps
CPU time 439.58 seconds
Started Aug 06 07:33:00 PM PDT 24
Finished Aug 06 07:40:20 PM PDT 24
Peak memory 201464 kb
Host smart-1a9f67e9-44f8-413b-9613-f96ae356d20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238092503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4238092503
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2645535486
Short name T726
Test name
Test status
Simulation time 67199444737 ps
CPU time 150.29 seconds
Started Aug 06 07:33:04 PM PDT 24
Finished Aug 06 07:35:34 PM PDT 24
Peak memory 210056 kb
Host smart-65409b2b-4d6b-463c-8c76-941faeb9fa81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645535486 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2645535486
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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