Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6926	1			T8	20		T54	2		T11	43
testmodes[AdcCtrlTestmodeNormal]	5412	1			T1	3		T2	1		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5525	1			T2	1		T4	2		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3770	1			T8	19		T54	1		T11	42
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1729	1			T54	1		T11	1		T56	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1311	1			T66	19		T69	17		T71	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1702	1			T54	1		T11	1		T56	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1961	1			T1	2		T3	2		T6	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1423	1			T2	1		T7	1		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1334	1			T66	17		T69	9		T71	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1381	1			T51	1		T66	17		T69	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2555	1			T4	1		T72	14		T66	10