Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22366

1

T1

2

T2

24

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3520

1

T1

1

T2

1

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20094

1

T1

1

T2

24

T3

2

auto[1]

5792

1

T1

2

T2

1

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T231	27		T232	1		-	-
values[0]	14	1			T233	2		T234	10		T235	1
values[1]	610	1			T6	14		T7	24		T165	2
values[2]	705	1			T1	1		T4	14		T166	3
values[3]	668	1			T51	20		T67	34		T81	2
values[4]	866	1			T6	11		T51	28		T151	14
values[5]	743	1			T236	40		T80	20		T199	14
values[6]	581	1			T1	1		T4	13		T11	6
values[7]	668	1			T1	1		T3	1		T63	9
values[8]	2710	1			T2	25		T3	1		T5	6
values[9]	1366	1			T3	1		T7	25		T55	7
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T4	14		T6	14		T7	24
values[1]	609	1			T1	1		T166	3		T81	2
values[2]	805	1			T51	20		T161	11		T67	34
values[3]	885	1			T6	11		T51	28		T151	14
values[4]	516	1			T55	14		T236	19		T162	11
values[5]	660	1			T1	1		T4	13		T11	6
values[6]	2844	1			T1	1		T3	1		T5	6
values[7]	595	1			T2	25		T3	1		T55	7
values[8]	1006	1			T3	1		T7	25		T51	18
values[9]	205	1			T58	1		T151	11		T237	3
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T165	2		T167	11		T163	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T4	14		T6	1		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T166	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T81	1		T45	1		T75	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T161	1		T67	13		T50	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T51	10		T153	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T51	13		T64	26		T80	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	1		T151	1		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T162	1		T80	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	1		T236	13		T49	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T11	5		T236	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	13		T79	12		T50	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T3	1		T5	6		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T65	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	12		T3	1		T63	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	1		T55	1		T238	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T65	15		T237	16		T67	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T7	14		T51	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T151	1		T237	3		T174	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T58	1		T212	15		T239	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T167	2		T163	12		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	13		T7	13		T63	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T166	2		T70	9		T182	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	1		T45	16		T174	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T161	10		T67	21		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	10		T209	12		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	15		T80	13		T178	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	10		T151	13		T38	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T162	10		T80	1		T48	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T55	13		T236	6		T49	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T236	8		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T79	16		T27	4		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T9	19		T59	5		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T65	11		T170	12		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	12		T63	2		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T55	6		T238	8		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T65	11		T67	12		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	11		T51	8		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T151	10		T174	4		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T212	10		T239	1		T242	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	15		T232	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T234	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T233	2		T235	1		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T165	2		T158	1		T167	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T7	11		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	1		T166	1		T70	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	14		T45	1		T243	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T67	13		T152	1		T154	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	10		T81	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T51	13		T64	26		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T151	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T236	13		T80	6		T199	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T236	13		T244	1		T38	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T11	5		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	13		T55	1		T49	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T63	7		T199	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T65	13		T79	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T2	12		T3	1		T5	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	1		T238	13		T199	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T151	1		T65	15		T237	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T3	1		T7	14		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T231	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T167	2		T40	2		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	13		T7	13		T63	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T166	2		T70	9		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	16		T174	8		T16	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T67	21		T168	13		T246	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	10		T81	1		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	15		T161	10		T50	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	10		T151	13		T209	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T236	8		T80	14		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T236	6		T38	12		T183	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T59	5		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T55	13		T49	3		T167	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T63	2		T168	8		T163	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	11		T79	16		T170	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T2	12		T9	19		T160	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T238	8		T170	10		T156	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T151	10		T65	11		T67	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	11		T55	6		T51	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T165	2		T167	3		T163	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	1		T6	14		T7	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T166	3		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T81	2		T45	17		T75	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T161	11		T67	22		T50	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	11		T153	1		T209	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T51	16		T64	2		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	11		T151	14		T38	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T162	11		T80	2		T48	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T55	14		T236	7		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T11	5		T236	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	1		T79	17		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T3	1		T5	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T65	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	13		T3	1		T63	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	1		T55	7		T238	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T65	12		T237	1		T67	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T7	12		T51	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T151	11		T237	1		T174	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T58	1		T212	11		T239	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T167	10		T163	12		T40	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	13		T7	10		T63	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T169	12		T182	5		T206	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T75	7		T174	10		T16	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T67	12		T50	4		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	9		T182	2		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T51	12		T64	24		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	8		T240	14		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T181	12		T248	1		T249	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T236	12		T49	1		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T236	12		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	12		T79	11		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T5	5		T59	8		T250	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T65	12		T170	11		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	11		T63	6		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T238	12		T199	2		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T65	14		T237	15		T67	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	13		T51	9		T64	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T237	2		T174	9		T251	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T212	14		T239	1		T242	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	13		T232	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T233	1		T235	1		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T165	2		T158	1		T167	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	14		T7	14		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T166	3		T70	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T45	17		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T67	22		T152	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	11		T81	2		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T51	16		T64	2		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	11		T151	14		T209	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T236	9		T80	16		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T236	7		T244	1		T38	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T11	5		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	1		T55	14		T49	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T63	3		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T65	12		T79	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	13		T3	1		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T238	9		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T151	11		T65	12		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T3	1		T7	12		T55	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T234	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T167	10		T40	11		T245	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	10		T63	13		T80	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T163	12		T169	12		T182	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	13		T243	12		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T67	12		T154	12		T177	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T51	9		T75	7		T252	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	12		T64	24		T50	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T240	14		T182	2		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T236	12		T80	4		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T236	12		T38	8		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	1		T59	8		T182	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	12		T49	1		T167	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T63	6		T199	1		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T65	12		T79	11		T50	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T2	11		T5	5		T250	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T238	12		T199	2		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T65	14		T237	17		T67	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T7	13		T51	9		T64	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22394

1

T1

1

T2

25

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3492

1

T1

2

T3

1

T4

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19723

1

T1

1

T2

25

T3

2

auto[1]

6163

1

T1

2

T3

1

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	429	1			T11	1		T66	1		T69	1
values[0]	22	1			T151	5		T152	1		T253	1
values[1]	594	1			T3	1		T7	25		T161	11
values[2]	2885	1			T5	6		T9	21		T10	3
values[3]	730	1			T1	1		T3	1		T11	6
values[4]	759	1			T165	1		T168	24		T164	10
values[5]	585	1			T1	2		T2	1		T4	13
values[6]	711	1			T4	14		T6	14		T64	13
values[7]	593	1			T3	1		T6	11		T51	28
values[8]	741	1			T58	1		T238	21		T152	1
values[9]	1332	1			T2	24		T55	14		T51	20
minimum	16505	1			T8	20		T54	10		T11	47

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	797	1			T3	1		T7	25		T151	5
values[1]	2827	1			T1	1		T5	6		T9	21
values[2]	818	1			T3	1		T165	1		T81	2
values[3]	627	1			T199	3		T50	15		T70	1
values[4]	666	1			T1	2		T2	1		T4	13
values[5]	579	1			T3	1		T4	14		T51	28
values[6]	810	1			T6	11		T151	11		T236	19
values[7]	700	1			T51	20		T58	1		T236	21
values[8]	892	1			T2	24		T55	14		T165	1
values[9]	224	1			T63	9		T163	29		T38	21
minimum	16946	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T7	14		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T67	13		T244	1		T163	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T5	6		T9	2		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T11	5		T51	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	1		T81	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	1		T176	1		T212	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	7		T170	12		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T199	3		T70	1		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T2	1		T4	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	1		T6	1		T64	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T51	13		T237	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	14		T151	1		T64	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T162	1		T238	13		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	1		T151	1		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	6		T209	1		T182	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T51	10		T58	1		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	12		T165	1		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T55	1		T161	1		T65	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T63	7		T38	9		T182	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T163	16		T121	1		T192	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16818	1			T8	20		T54	10		T11	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	11		T151	4		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T67	21		T163	12		T45	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T9	19		T160	8		T65	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T51	8		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T81	1		T254	5		T170	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T212	10		T168	13		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	8		T170	10		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T255	17		T256	13		T257	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	13		T55	6		T59	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	13		T166	14		T170	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	15		T80	7		T158	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T151	13		T80	13		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T162	10		T238	8		T167	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	10		T151	10		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T209	12		T182	10		T258	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	10		T236	8		T45	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	12		T63	13		T166	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	13		T65	11		T153	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T63	2		T38	12		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T163	13		T121	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	4		T67	1		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	429	1			T11	1		T66	1		T69	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T151	1		T152	1		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T253	1		T259	8		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	1		T7	14		T163	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T161	1		T244	1		T163	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T5	6		T9	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T51	10		T64	13		T67	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T81	1		T158	1		T245	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T1	1		T3	1		T11	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T165	1		T254	1		T170	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T168	11		T164	1		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T2	1		T4	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T151	1		T64	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T237	16		T166	1		T158	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	14		T6	1		T64	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T51	13		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T151	1		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T238	13		T176	4		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T58	1		T152	1		T177	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T2	12		T165	1		T63	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T55	1		T51	10		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16386	1			T8	20		T54	10		T11	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T151	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	11		T163	12		T178	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T161	10		T163	12		T45	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T9	19		T160	8		T65	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	8		T67	21		T80	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T81	1		T245	6		T261	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	1		T79	16		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T254	5		T170	22		T183	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T168	13		T164	9		T246	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	13		T55	6		T59	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T151	13		T166	14		T170	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T166	2		T158	14		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	13		T40	2		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T51	15		T162	10		T80	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	10		T151	10		T236	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T238	8		T209	12		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	7		T240	13		T174	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T2	12		T63	15		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T55	13		T51	10		T65	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1