Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22318

1

T1

2

T2

24

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3568

1

T1

1

T2

1

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20134

1

T1

1

T2

25

T3

2

auto[1]

5752

1

T1

2

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	421	1			T3	1		T151	5		T65	26
values[0]	12	1			T234	10		T214	2		-	-
values[1]	696	1			T6	14		T7	24		T165	2
values[2]	621	1			T1	1		T4	14		T166	3
values[3]	585	1			T51	20		T67	34		T81	2
values[4]	913	1			T6	11		T51	28		T151	14
values[5]	693	1			T80	20		T199	14		T244	1
values[6]	688	1			T1	1		T4	13		T11	6
values[7]	630	1			T1	1		T3	1		T65	24
values[8]	2705	1			T2	25		T3	1		T5	6
values[9]	995	1			T7	25		T55	7		T51	18
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	614	1			T6	14		T7	24		T165	1
values[1]	630	1			T1	1		T4	14		T166	3
values[2]	727	1			T51	20		T161	11		T67	34
values[3]	930	1			T6	11		T51	28		T151	14
values[4]	601	1			T55	14		T236	19		T162	11
values[5]	605	1			T1	1		T3	1		T4	13
values[6]	2825	1			T1	1		T5	6		T9	21
values[7]	599	1			T2	25		T3	1		T55	7
values[8]	1122	1			T3	1		T7	25		T51	18
values[9]	112	1			T58	1		T151	11		T237	3
minimum	17121	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T165	1		T167	11		T163	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T7	11		T63	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T166	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	14		T45	1		T75	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T161	1		T67	13		T50	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	10		T81	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T51	13		T64	26		T80	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	1		T151	1		T199	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T162	1		T80	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T55	1		T236	13		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T3	1		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	13		T79	12		T49	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T5	6		T9	2		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T65	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	12		T3	1		T63	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	1		T55	1		T238	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T65	15		T237	16		T67	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T3	1		T7	14		T51	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T151	1		T237	3		T174	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T58	1		T212	15		T239	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16838	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T80	15		T164	1		T283	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T167	2		T163	12		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	13		T7	13		T63	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T166	2		T70	9		T182	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	16		T174	8		T16	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T161	10		T67	21		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	10		T81	1		T209	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T51	15		T80	13		T178	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	10		T151	13		T38	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T162	10		T80	1		T48	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T55	13		T236	6		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T236	8		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T79	16		T49	3		T27	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T9	19		T59	5		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T65	11		T170	2		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	12		T63	2		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T55	6		T238	8		T170	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T65	11		T67	12		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	11		T51	8		T151	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T151	10		T174	4		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T212	10		T239	1		T242	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T80	7		T283	2		T255	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T65	15		T258	4		T231	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T3	1		T151	1		T156	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T234	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T214	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T165	2		T167	11		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T7	11		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T166	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	14		T45	1		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T67	13		T152	1		T154	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T51	10		T81	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	13		T64	26		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	1		T151	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T80	6		T178	1		T264	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T199	14		T244	1		T183	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T11	5		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	13		T55	1		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T166	1		T199	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T65	13		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	12		T3	1		T5	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T238	13		T199	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T151	1		T237	19		T67	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T7	14		T55	1		T51	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T65	11		T258	8		T231	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T151	4		T53	6		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T167	2		T40	2		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	13		T7	13		T63	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T166	2		T70	9		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	16		T174	8		T16	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T67	21		T168	13		T246	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T51	10		T81	1		T45	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	15		T161	10		T50	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	10		T151	13		T209	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T80	14		T178	12		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T183	13		T105	2		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	1		T59	5		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T55	13		T236	6		T79	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T166	14		T164	9		T178	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T65	11		T170	2		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T2	12		T9	19		T160	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T238	8		T170	10		T156	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T151	10		T67	12		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	11		T55	6		T51	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	1		T167	3		T163	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	14		T7	14		T63	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T166	3		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	1		T45	17		T75	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T161	11		T67	22		T50	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	11		T81	2		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T51	16		T64	2		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	11		T151	14		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T162	11		T80	2		T48	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T55	14		T236	7		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T3	1		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	1		T79	17		T49	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T5	1		T9	21		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	1		T65	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	13		T3	1		T63	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	1		T55	7		T238	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T65	12		T237	1		T67	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T7	12		T51	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T151	11		T237	1		T174	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T58	1		T212	11		T239	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16967	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T80	8		T164	1		T283	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T167	10		T163	12		T40	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	10		T63	13		T70	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T169	12		T182	5		T206	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	13		T75	7		T174	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T67	12		T50	4		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	9		T182	2		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	12		T64	24		T80	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T199	13		T38	8		T240	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T181	12		T248	1		T249	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T236	12		T167	14		T26	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	1		T236	12		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	12		T79	11		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	5		T59	8		T250	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T65	12		T50	3		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	11		T63	6		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T238	12		T199	2		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T65	14		T237	15		T67	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	13		T51	9		T64	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T237	2		T174	9		T251	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T212	14		T239	1		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T245	4		T234	9		T323	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T80	14		T255	10		T324	23

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T65	12		T258	9		T231	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	1		T151	5		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T214	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T165	2		T167	3		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	14		T7	14		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T166	3		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T45	17		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T67	22		T152	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	11		T81	2		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T51	16		T64	2		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T6	11		T151	14		T209	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T80	16		T178	13		T264	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T199	1		T244	1		T183	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T11	5		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	1		T55	14		T236	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T166	15		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T65	12		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T2	13		T3	1		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T238	9		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T151	11		T237	2		T67	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	12		T55	7		T51	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T65	14		T258	3		T231	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T156	2		T53	1		T256	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T234	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T167	10		T40	11		T245	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	10		T63	13		T80	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T163	12		T169	12		T182	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	13		T174	10		T16	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T67	12		T154	12		T177	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T51	9		T243	12		T75	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	12		T64	24		T50	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T38	8		T240	14		T182	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T80	4		T264	9		T181	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T199	13		T247	9		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T59	8		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	12		T236	12		T79	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T199	1		T262	10		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T65	12		T50	3		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T2	11		T5	5		T63	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T238	12		T199	2		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T237	17		T67	10		T154	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	13		T51	9		T64	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5