Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22203

1

T1

1

T2

24

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3683

1

T1

2

T2

1

T4

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20201

1

T1

2

T2

1

T3

1

auto[1]

5685

1

T1

1

T2

24

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T51	18		T166	3		T70	17
values[0]	11	1			T176	1		T257	10		-	-
values[1]	977	1			T1	1		T2	24		T4	13
values[2]	2774	1			T4	14		T5	6		T9	21
values[3]	541	1			T6	11		T64	13		T236	19
values[4]	699	1			T165	1		T64	13		T153	10
values[5]	533	1			T1	1		T3	1		T7	25
values[6]	886	1			T1	1		T55	14		T151	11
values[7]	603	1			T6	14		T151	14		T166	12
values[8]	693	1			T2	1		T3	1		T11	6
values[9]	966	1			T3	1		T7	24		T51	28
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T2	24		T51	20		T151	5
values[1]	2779	1			T4	14		T5	6		T6	11
values[2]	551	1			T165	1		T64	13		T236	19
values[3]	677	1			T1	1		T3	1		T64	13
values[4]	661	1			T7	25		T58	1		T161	1
values[5]	700	1			T1	1		T55	14		T151	11
values[6]	755	1			T2	1		T6	14		T59	14
values[7]	632	1			T3	1		T7	24		T11	6
values[8]	945	1			T3	1		T51	46		T165	1
values[9]	114	1			T237	16		T158	1		T245	26
minimum	17297	1			T1	1		T4	13		T8	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	12		T64	17		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	10		T151	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T5	6		T6	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	14		T63	7		T163	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	1		T64	13		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T236	13		T50	7		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T64	13		T167	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T236	13		T199	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	14		T161	1		T50	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T58	1		T65	13		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	1		T166	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T55	1		T80	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	1		T59	9		T67	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T151	1		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T7	11		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T158	1		T163	13		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	1		T51	23		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T165	1		T237	3		T79	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T237	16		T279	14		T276	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T158	1		T245	13		T279	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16861	1			T1	1		T4	13		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T55	1		T67	11		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	12		T161	10		T22	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	10		T151	4		T80	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T6	10		T9	19		T160	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T63	2		T163	13		T240	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T209	12		T170	2		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T236	6		T50	8		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T167	9		T168	8		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T236	8		T153	8		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	11		T167	2		T246	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T65	11		T162	10		T80	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	10		T166	14		T81	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T55	13		T80	13		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	13		T59	5		T67	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	13		T63	13		T166	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	13		T11	1		T65	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T158	14		T163	12		T38	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T51	23		T166	2		T45	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T79	16		T49	3		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T279	7		T276	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T245	13		T279	13		T282	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T55	6		T67	12		T240	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T51	10		T166	1		T231	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T70	12		T183	1		T245	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T257	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T176	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	1		T2	12		T4	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T55	1		T51	10		T67	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T5	6		T9	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	14		T151	1		T63	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	1		T64	13		T177	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T236	13		T50	7		T163	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	1		T64	13		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T153	1		T154	13		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T7	14		T176	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T58	1		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	1		T161	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	1		T55	1		T65	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T67	13		T154	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	1		T166	1		T80	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T11	5		T59	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T63	14		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	1		T7	11		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T165	1		T237	3		T79	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T51	8		T166	2		T231	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T70	5		T183	2		T245	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T257	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	12		T161	10		T246	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T55	6		T51	10		T67	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T9	19		T160	8		T270	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	4		T63	2		T212	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	10		T170	2		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T236	6		T50	8		T163	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T209	12		T168	8		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T153	8		T164	9		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	11		T167	11		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T236	8		T70	9		T14	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T151	10		T166	14		T81	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T55	13		T65	11		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	13		T67	21		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	13		T166	11		T80	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T59	5		T238	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T63	13		T158	14		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	13		T51	15		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T79	16		T49	3		T38	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	13		T64	1		T161	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T51	11		T151	5		T80	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T5	1		T6	11		T9	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	1		T63	3		T163	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T165	1		T64	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T236	7		T50	11		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T64	1		T167	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T236	9		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	12		T161	1		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T58	1		T65	12		T162	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	11		T166	15		T81	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T55	14		T80	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	14		T59	6		T67	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T151	14		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T7	14		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T158	15		T163	13		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	1		T51	25		T166	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T165	1		T237	1		T79	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T237	1		T279	9		T276	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T158	1		T245	14		T279	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16968	1			T1	1		T4	1		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T55	7		T67	13		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	11		T64	16		T298	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T51	9		T212	14		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T5	5		T250	14		T219	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	13		T63	6		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T64	12		T177	6		T179	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T236	12		T50	4		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T64	12		T167	14		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T236	12		T199	1		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	13		T50	3		T176	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T65	12		T80	14		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T256	7		T261	13		T277	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T80	4		T40	11		T240	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	8		T67	12		T238	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T63	13		T168	10		T40	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T7	10		T11	1		T65	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T163	12		T38	8		T36	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	21		T179	4		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T237	2		T79	11		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T237	15		T279	12		T276	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T245	12		T279	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T4	12		T306	15		T325	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T67	10		T240	2		T75	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T51	9		T166	3		T231	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T70	6		T183	3		T245	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T257	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T176	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T2	13		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T55	7		T51	11		T67	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T5	1		T9	21		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T151	5		T63	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	11		T64	1		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T236	7		T50	11		T163	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	1		T64	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T153	9		T154	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T7	12		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T58	1		T236	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T151	11		T161	1		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T55	14		T65	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	14		T67	22		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T151	14		T166	12		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T11	5		T59	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T63	14		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	1		T7	14		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T165	1		T237	1		T79	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T51	9		T231	14		T174	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T70	11		T245	12		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	11		T4	12		T303	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T51	9		T67	10		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	5		T64	16		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	13		T63	6		T212	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T64	12		T177	6		T179	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T236	12		T50	4		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T64	12		T168	9		T184	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T154	12		T156	14		T231	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	13		T176	3		T167	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T236	12		T199	1		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T50	3		T53	1		T256	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T65	12		T80	14		T40	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T67	12		T154	4		T231	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T80	4		T40	4		T182	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	1		T59	8		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T63	13		T168	10		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	10		T51	12		T65	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T237	2		T79	11		T49	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5