Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22521

1

T1

1

T3

2

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3365

1

T1

2

T2

25

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19893

1

T2

1

T3

2

T4

14

auto[1]

5993

1

T1

3

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T2	24		T199	14		T45	17
values[0]	38	1			T183	13		T279	20		T207	5
values[1]	519	1			T2	1		T151	11		T64	13
values[2]	738	1			T6	25		T236	19		T152	1
values[3]	748	1			T1	1		T7	25		T58	1
values[4]	648	1			T55	14		T51	20		T165	1
values[5]	2705	1			T5	6		T7	24		T9	21
values[6]	1033	1			T4	14		T11	6		T51	28
values[7]	600	1			T3	1		T64	17		T236	21
values[8]	903	1			T1	2		T4	13		T63	27
values[9]	829	1			T3	2		T55	7		T165	1
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	666	1			T6	14		T151	11		T64	13
values[1]	688	1			T6	11		T236	19		T152	1
values[2]	744	1			T1	1		T7	25		T58	1
values[3]	2771	1			T5	6		T7	24		T9	21
values[4]	891	1			T51	28		T64	13		T80	2
values[5]	636	1			T4	14		T11	6		T59	14
values[6]	715	1			T3	1		T64	17		T236	21
values[7]	834	1			T1	2		T4	13		T63	27
values[8]	726	1			T3	1		T55	7		T165	1
values[9]	179	1			T2	24		T3	1		T161	1
minimum	17036	1			T2	1		T8	20		T54	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	1		T209	1		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T64	13		T176	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T152	1		T212	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T236	13		T179	5		T258	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	14		T151	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	1		T58	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T5	6		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	11		T55	1		T51	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T64	13		T199	2		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T51	13		T80	1		T154	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T151	1		T65	15		T67	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	14		T11	5		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T64	17		T50	6		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	1		T236	13		T79	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T1	1		T4	13		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T80	5		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T237	19		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T55	1		T165	1		T63	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T3	1		T161	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T2	12		T166	1		T238	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16847	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T2	1		T183	1		T326	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	10		T209	12		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	13		T170	2		T231	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	10		T212	10		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T236	6		T258	3		T39	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	11		T151	4		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T81	1		T163	12		T182	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T9	19		T160	8		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	13		T55	13		T51	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T167	2		T163	12		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	15		T80	1		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	13		T65	11		T67	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	1		T59	5		T216	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T240	13		T178	12		T258	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T236	8		T79	16		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T63	13		T166	2		T67	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T80	13		T240	13		T14	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T166	11		T162	10		T49	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T55	6		T63	2		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T45	16		T30	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T2	12		T166	14		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T183	12		T287	3		T327	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T45	1		T241	1		T328	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T2	12		T199	14		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T279	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T183	1		T207	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	1		T209	1		T70	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	1		T64	13		T176	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T152	1		T40	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	1		T236	13		T179	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	14		T151	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T58	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T152	1		T244	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T55	1		T51	10		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T5	6		T9	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	11		T51	10		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T151	1		T64	13		T65	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	14		T11	5		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T64	17		T67	11		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T236	13		T79	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T1	1		T4	13		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T80	5		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	2		T161	1		T237	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T55	1		T165	1		T63	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T45	16		T241	8		T30	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T2	12		T121	11		T20	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T279	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T183	12		T207	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	10		T209	12		T163	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T170	2		T255	17		T121	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	10		T40	2		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	13		T236	6		T231	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	11		T151	4		T161	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T81	1		T163	12		T182	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T70	9		T283	2		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	13		T51	10		T80	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T9	19		T160	8		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	13		T51	8		T80	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T151	13		T65	11		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T51	15		T59	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T67	12		T178	12		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T236	8		T79	16		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T63	13		T166	2		T67	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T80	13		T48	12		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T166	11		T162	10		T49	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T55	6		T63	2		T65	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T151	11		T209	13		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	14		T64	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	11		T152	1		T212	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T236	7		T179	1		T258	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	12		T151	5		T161	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	1		T58	1		T81	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T5	1		T9	21		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	14		T55	14		T51	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T64	1		T199	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T51	16		T80	2		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	14		T65	12		T67	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	1		T11	5		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T64	1		T50	3		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T236	9		T79	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	1		T4	1		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T80	14		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T237	2		T166	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	7		T165	1		T63	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T3	1		T161	1		T45	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	13		T166	15		T238	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16949	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T2	1		T183	13		T326	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	11		T182	2		T245	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T64	12		T176	3		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T212	14		T163	15		T281	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T236	12		T179	4		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	13		T50	4		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T199	2		T154	12		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	5		T250	14		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	10		T51	18		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T64	12		T199	1		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	12		T154	4		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T65	14		T67	10		T38	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	13		T11	1		T59	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T64	16		T50	3		T240	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T236	12		T79	11		T40	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	12		T63	13		T67	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T80	4		T240	14		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T237	17		T49	1		T182	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T63	6		T65	12		T199	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	4		T30	3		T284	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T2	11		T238	12		T181	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T26	3		T206	10		T330	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T331	6		T130	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T45	17		T241	9		T328	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T2	13		T199	1		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T279	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T183	13		T207	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T151	11		T209	13		T70	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T2	1		T64	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	11		T152	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	14		T236	7		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	12		T151	5		T161	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T58	1		T81	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T152	1		T244	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T55	14		T51	11		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T5	1		T9	21		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	14		T51	9		T80	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T151	14		T64	1		T65	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	1		T11	5		T51	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T64	1		T67	13		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T236	9		T79	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T1	1		T4	1		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T80	14		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T161	1		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T55	7		T165	1		T63	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T328	12		T30	3		T332	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T2	11		T199	13		T20	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T163	15		T182	2		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T64	12		T176	3		T255	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	11		T27	1		T255	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T236	12		T179	4		T231	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	13		T50	4		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T199	2		T163	16		T182	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T231	14		T256	10		T324	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	9		T80	14		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	5		T250	14		T219	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	10		T51	9		T154	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T64	12		T65	14		T199	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	13		T11	1		T51	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T64	16		T67	10		T50	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T236	12		T79	11		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	12		T63	13		T67	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T80	4		T240	14		T14	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T237	17		T49	1		T169	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T63	6		T65	12		T238	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5