interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
176 |
1 |
|
|
T166 |
1 |
|
T158 |
1 |
|
T163 |
17 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
226 |
1 |
|
|
T236 |
13 |
|
T170 |
1 |
|
T243 |
13 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
153 |
1 |
|
|
T2 |
1 |
|
T67 |
13 |
|
T40 |
5 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1559 |
1 |
|
|
T5 |
6 |
|
T9 |
2 |
|
T10 |
3 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
200 |
1 |
|
|
T1 |
1 |
|
T64 |
17 |
|
T166 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
196 |
1 |
|
|
T4 |
13 |
|
T63 |
7 |
|
T64 |
13 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
172 |
1 |
|
|
T1 |
1 |
|
T50 |
6 |
|
T231 |
16 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
199 |
1 |
|
|
T1 |
1 |
|
T4 |
14 |
|
T6 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
169 |
1 |
|
|
T2 |
12 |
|
T244 |
1 |
|
T154 |
5 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
237 |
1 |
|
|
T51 |
10 |
|
T59 |
9 |
|
T166 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
175 |
1 |
|
|
T65 |
15 |
|
T81 |
1 |
|
T163 |
16 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
239 |
1 |
|
|
T6 |
1 |
|
T7 |
14 |
|
T63 |
14 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
204 |
1 |
|
|
T3 |
1 |
|
T55 |
1 |
|
T165 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
260 |
1 |
|
|
T51 |
13 |
|
T165 |
1 |
|
T162 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
177 |
1 |
|
|
T161 |
1 |
|
T154 |
13 |
|
T168 |
11 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
227 |
1 |
|
|
T58 |
1 |
|
T151 |
2 |
|
T65 |
13 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
213 |
1 |
|
|
T80 |
1 |
|
T158 |
1 |
|
T45 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
196 |
1 |
|
|
T67 |
11 |
|
T199 |
2 |
|
T176 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
41 |
1 |
|
|
T3 |
1 |
|
T14 |
15 |
|
T313 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
52 |
1 |
|
|
T156 |
5 |
|
T310 |
12 |
|
T286 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
16889 |
1 |
|
|
T3 |
1 |
|
T7 |
11 |
|
T8 |
20 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
84 |
1 |
|
|
T64 |
13 |
|
T184 |
12 |
|
T241 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
152 |
1 |
|
|
T166 |
2 |
|
T163 |
12 |
|
T178 |
12 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
189 |
1 |
|
|
T236 |
8 |
|
T170 |
12 |
|
T174 |
6 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
103 |
1 |
|
|
T67 |
21 |
|
T40 |
6 |
|
T246 |
2 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
951 |
1 |
|
|
T9 |
19 |
|
T55 |
13 |
|
T160 |
8 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
84 |
1 |
|
|
T166 |
14 |
|
T236 |
6 |
|
T49 |
3 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
151 |
1 |
|
|
T63 |
2 |
|
T161 |
10 |
|
T79 |
16 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
193 |
1 |
|
|
T231 |
12 |
|
T26 |
12 |
|
T27 |
1 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
101 |
1 |
|
|
T6 |
10 |
|
T11 |
1 |
|
T51 |
10 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
126 |
1 |
|
|
T2 |
12 |
|
T70 |
9 |
|
T167 |
9 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
135 |
1 |
|
|
T51 |
8 |
|
T59 |
5 |
|
T166 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
140 |
1 |
|
|
T65 |
11 |
|
T81 |
1 |
|
T163 |
13 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
219 |
1 |
|
|
T6 |
13 |
|
T7 |
11 |
|
T63 |
13 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
152 |
1 |
|
|
T55 |
6 |
|
T238 |
8 |
|
T45 |
16 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
185 |
1 |
|
|
T51 |
15 |
|
T162 |
10 |
|
T80 |
13 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
128 |
1 |
|
|
T168 |
13 |
|
T314 |
13 |
|
T304 |
4 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T151 |
14 |
|
T65 |
11 |
|
T212 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
186 |
1 |
|
|
T80 |
1 |
|
T158 |
14 |
|
T45 |
7 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
161 |
1 |
|
|
T67 |
12 |
|
T164 |
9 |
|
T245 |
13 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
31 |
1 |
|
|
T14 |
11 |
|
T309 |
13 |
|
T334 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
5 |
1 |
|
|
T156 |
5 |
|
- |
- |
|
- |
- |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T7 |
13 |
|
T11 |
4 |
|
T67 |
1 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
94 |
1 |
|
|
T241 |
8 |
|
T217 |
15 |
|
T287 |
3 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
109 |
1 |
|
|
T254 |
1 |
|
T240 |
15 |
|
T52 |
1 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
53 |
1 |
|
|
T156 |
5 |
|
T245 |
13 |
|
T216 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
1 |
1 |
|
|
T283 |
1 |
|
- |
- |
|
- |
- |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
6 |
1 |
|
|
T333 |
5 |
|
T318 |
1 |
|
- |
- |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
227 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
11 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
267 |
1 |
|
|
T64 |
13 |
|
T243 |
13 |
|
T13 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
169 |
1 |
|
|
T67 |
13 |
|
T158 |
1 |
|
T40 |
5 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
154 |
1 |
|
|
T55 |
1 |
|
T151 |
1 |
|
T236 |
13 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
174 |
1 |
|
|
T1 |
1 |
|
T64 |
17 |
|
T166 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
236 |
1 |
|
|
T4 |
13 |
|
T63 |
7 |
|
T64 |
13 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
153 |
1 |
|
|
T1 |
1 |
|
T152 |
1 |
|
T153 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
186 |
1 |
|
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
5 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
218 |
1 |
|
|
T2 |
12 |
|
T244 |
1 |
|
T70 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
252 |
1 |
|
|
T4 |
14 |
|
T51 |
10 |
|
T59 |
9 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
130 |
1 |
|
|
T154 |
5 |
|
T163 |
16 |
|
T170 |
12 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
221 |
1 |
|
|
T6 |
1 |
|
T63 |
14 |
|
T166 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
189 |
1 |
|
|
T3 |
1 |
|
T55 |
1 |
|
T165 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
231 |
1 |
|
|
T7 |
14 |
|
T51 |
13 |
|
T165 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
208 |
1 |
|
|
T152 |
1 |
|
T154 |
13 |
|
T168 |
11 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
255 |
1 |
|
|
T58 |
1 |
|
T151 |
2 |
|
T65 |
13 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T3 |
1 |
|
T161 |
1 |
|
T80 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1614 |
1 |
|
|
T5 |
6 |
|
T9 |
2 |
|
T10 |
3 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
16808 |
1 |
|
|
T8 |
20 |
|
T54 |
10 |
|
T11 |
44 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
80 |
1 |
|
|
T254 |
5 |
|
T240 |
13 |
|
T335 |
5 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
71 |
1 |
|
|
T156 |
5 |
|
T245 |
13 |
|
T216 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
2 |
1 |
|
|
T283 |
2 |
|
- |
- |
|
- |
- |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
7 |
1 |
|
|
T318 |
7 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
184 |
1 |
|
|
T7 |
13 |
|
T166 |
2 |
|
T163 |
12 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
213 |
1 |
|
|
T174 |
6 |
|
T241 |
8 |
|
T261 |
14 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
126 |
1 |
|
|
T67 |
21 |
|
T40 |
6 |
|
T246 |
2 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
203 |
1 |
|
|
T55 |
13 |
|
T151 |
13 |
|
T236 |
8 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
95 |
1 |
|
|
T166 |
14 |
|
T236 |
6 |
|
T49 |
3 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
135 |
1 |
|
|
T63 |
2 |
|
T161 |
10 |
|
T80 |
7 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
133 |
1 |
|
|
T153 |
8 |
|
T105 |
2 |
|
T26 |
12 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
136 |
1 |
|
|
T6 |
10 |
|
T11 |
1 |
|
T51 |
10 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
169 |
1 |
|
|
T2 |
12 |
|
T70 |
9 |
|
T167 |
9 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
114 |
1 |
|
|
T51 |
8 |
|
T59 |
5 |
|
T50 |
8 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
122 |
1 |
|
|
T163 |
13 |
|
T170 |
10 |
|
T182 |
12 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
224 |
1 |
|
|
T6 |
13 |
|
T63 |
13 |
|
T166 |
11 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
125 |
1 |
|
|
T55 |
6 |
|
T65 |
11 |
|
T238 |
8 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T7 |
11 |
|
T51 |
15 |
|
T80 |
13 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
178 |
1 |
|
|
T168 |
13 |
|
T45 |
16 |
|
T314 |
13 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
178 |
1 |
|
|
T151 |
14 |
|
T65 |
11 |
|
T162 |
10 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
145 |
1 |
|
|
T80 |
1 |
|
T158 |
14 |
|
T45 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
910 |
1 |
|
|
T9 |
19 |
|
T160 |
8 |
|
T270 |
9 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
119 |
1 |
|
|
T11 |
4 |
|
T67 |
1 |
|
T49 |
1 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
199 |
1 |
|
|
T166 |
3 |
|
T158 |
1 |
|
T163 |
13 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
231 |
1 |
|
|
T236 |
9 |
|
T170 |
13 |
|
T243 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
134 |
1 |
|
|
T2 |
1 |
|
T67 |
22 |
|
T40 |
7 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1283 |
1 |
|
|
T5 |
1 |
|
T9 |
21 |
|
T10 |
3 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
138 |
1 |
|
|
T1 |
1 |
|
T64 |
1 |
|
T166 |
15 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
189 |
1 |
|
|
T4 |
1 |
|
T63 |
3 |
|
T64 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
232 |
1 |
|
|
T1 |
1 |
|
T50 |
3 |
|
T231 |
13 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
138 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T6 |
11 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
157 |
1 |
|
|
T2 |
13 |
|
T244 |
1 |
|
T154 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
177 |
1 |
|
|
T51 |
9 |
|
T59 |
6 |
|
T166 |
12 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
171 |
1 |
|
|
T65 |
12 |
|
T81 |
2 |
|
T163 |
14 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
266 |
1 |
|
|
T6 |
14 |
|
T7 |
12 |
|
T63 |
14 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
199 |
1 |
|
|
T3 |
1 |
|
T55 |
7 |
|
T165 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
229 |
1 |
|
|
T51 |
16 |
|
T165 |
1 |
|
T162 |
11 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
160 |
1 |
|
|
T161 |
1 |
|
T154 |
1 |
|
T168 |
14 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
207 |
1 |
|
|
T58 |
1 |
|
T151 |
16 |
|
T65 |
12 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
229 |
1 |
|
|
T80 |
2 |
|
T158 |
15 |
|
T45 |
8 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
201 |
1 |
|
|
T67 |
13 |
|
T199 |
1 |
|
T176 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
44 |
1 |
|
|
T3 |
1 |
|
T14 |
18 |
|
T313 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
12 |
1 |
|
|
T156 |
6 |
|
T310 |
1 |
|
T286 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17002 |
1 |
|
|
T3 |
1 |
|
T7 |
14 |
|
T8 |
20 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
107 |
1 |
|
|
T64 |
1 |
|
T184 |
1 |
|
T241 |
9 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
129 |
1 |
|
|
T163 |
16 |
|
T330 |
2 |
|
T313 |
18 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
184 |
1 |
|
|
T236 |
12 |
|
T243 |
12 |
|
T278 |
4 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
122 |
1 |
|
|
T67 |
12 |
|
T40 |
4 |
|
T262 |
10 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1227 |
1 |
|
|
T5 |
5 |
|
T250 |
14 |
|
T219 |
17 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
146 |
1 |
|
|
T64 |
16 |
|
T236 |
12 |
|
T49 |
1 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
158 |
1 |
|
|
T4 |
12 |
|
T63 |
6 |
|
T64 |
12 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
133 |
1 |
|
|
T50 |
3 |
|
T231 |
15 |
|
T26 |
14 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
162 |
1 |
|
|
T4 |
13 |
|
T11 |
1 |
|
T51 |
9 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
138 |
1 |
|
|
T2 |
11 |
|
T154 |
4 |
|
T167 |
14 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
195 |
1 |
|
|
T51 |
9 |
|
T59 |
8 |
|
T167 |
10 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
144 |
1 |
|
|
T65 |
14 |
|
T163 |
15 |
|
T170 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
192 |
1 |
|
|
T7 |
13 |
|
T63 |
13 |
|
T199 |
13 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
157 |
1 |
|
|
T237 |
15 |
|
T238 |
12 |
|
T243 |
9 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
216 |
1 |
|
|
T51 |
12 |
|
T80 |
4 |
|
T154 |
8 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
145 |
1 |
|
|
T154 |
12 |
|
T168 |
10 |
|
T296 |
11 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
193 |
1 |
|
|
T65 |
12 |
|
T237 |
2 |
|
T199 |
2 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
170 |
1 |
|
|
T240 |
14 |
|
T243 |
2 |
|
T258 |
3 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
156 |
1 |
|
|
T67 |
10 |
|
T199 |
1 |
|
T245 |
12 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
28 |
1 |
|
|
T14 |
8 |
|
T309 |
17 |
|
T334 |
3 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
45 |
1 |
|
|
T156 |
4 |
|
T310 |
11 |
|
T336 |
9 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
70 |
1 |
|
|
T7 |
10 |
|
T174 |
10 |
|
T277 |
13 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
71 |
1 |
|
|
T64 |
12 |
|
T184 |
11 |
|
T233 |
1 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
98 |
1 |
|
|
T254 |
6 |
|
T240 |
14 |
|
T52 |
1 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
84 |
1 |
|
|
T156 |
6 |
|
T245 |
14 |
|
T216 |
2 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
3 |
1 |
|
|
T283 |
3 |
|
- |
- |
|
- |
- |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
9 |
1 |
|
|
T333 |
1 |
|
T318 |
8 |
|
- |
- |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
233 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
14 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
257 |
1 |
|
|
T64 |
1 |
|
T243 |
1 |
|
T13 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
162 |
1 |
|
|
T67 |
22 |
|
T158 |
1 |
|
T40 |
7 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
246 |
1 |
|
|
T55 |
14 |
|
T151 |
14 |
|
T236 |
9 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
136 |
1 |
|
|
T1 |
1 |
|
T64 |
1 |
|
T166 |
15 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T4 |
1 |
|
T63 |
3 |
|
T64 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
181 |
1 |
|
|
T1 |
1 |
|
T152 |
1 |
|
T153 |
9 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
174 |
1 |
|
|
T1 |
1 |
|
T6 |
11 |
|
T11 |
5 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
201 |
1 |
|
|
T2 |
13 |
|
T244 |
1 |
|
T70 |
10 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
152 |
1 |
|
|
T4 |
1 |
|
T51 |
9 |
|
T59 |
6 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
147 |
1 |
|
|
T154 |
1 |
|
T163 |
14 |
|
T170 |
11 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
272 |
1 |
|
|
T6 |
14 |
|
T63 |
14 |
|
T166 |
12 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
166 |
1 |
|
|
T3 |
1 |
|
T55 |
7 |
|
T165 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
213 |
1 |
|
|
T7 |
12 |
|
T51 |
16 |
|
T165 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
223 |
1 |
|
|
T152 |
1 |
|
T154 |
1 |
|
T168 |
14 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
221 |
1 |
|
|
T58 |
1 |
|
T151 |
16 |
|
T65 |
12 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
188 |
1 |
|
|
T3 |
1 |
|
T161 |
1 |
|
T80 |
2 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1241 |
1 |
|
|
T5 |
1 |
|
T9 |
21 |
|
T10 |
3 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
16927 |
1 |
|
|
T8 |
20 |
|
T54 |
10 |
|
T11 |
48 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
91 |
1 |
|
|
T240 |
14 |
|
T335 |
5 |
|
T337 |
13 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
40 |
1 |
|
|
T156 |
4 |
|
T245 |
12 |
|
T53 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
4 |
1 |
|
|
T333 |
4 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
178 |
1 |
|
|
T7 |
10 |
|
T163 |
16 |
|
T174 |
10 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
223 |
1 |
|
|
T64 |
12 |
|
T243 |
12 |
|
T278 |
4 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
133 |
1 |
|
|
T67 |
12 |
|
T40 |
4 |
|
T262 |
10 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
111 |
1 |
|
|
T236 |
12 |
|
T240 |
2 |
|
T75 |
7 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
133 |
1 |
|
|
T64 |
16 |
|
T236 |
12 |
|
T49 |
1 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
200 |
1 |
|
|
T4 |
12 |
|
T63 |
6 |
|
T64 |
12 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
105 |
1 |
|
|
T50 |
3 |
|
T169 |
4 |
|
T247 |
3 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
148 |
1 |
|
|
T11 |
1 |
|
T51 |
9 |
|
T79 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
186 |
1 |
|
|
T2 |
11 |
|
T167 |
14 |
|
T231 |
15 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
214 |
1 |
|
|
T4 |
13 |
|
T51 |
9 |
|
T59 |
8 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
105 |
1 |
|
|
T154 |
4 |
|
T163 |
15 |
|
T170 |
11 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T63 |
13 |
|
T199 |
13 |
|
T167 |
10 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
148 |
1 |
|
|
T65 |
14 |
|
T237 |
15 |
|
T238 |
12 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
191 |
1 |
|
|
T7 |
13 |
|
T51 |
12 |
|
T80 |
4 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
163 |
1 |
|
|
T154 |
12 |
|
T168 |
10 |
|
T265 |
10 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
212 |
1 |
|
|
T65 |
12 |
|
T237 |
2 |
|
T199 |
2 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
140 |
1 |
|
|
T243 |
2 |
|
T258 |
3 |
|
T14 |
8 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
1283 |
1 |
|
|
T5 |
5 |
|
T250 |
14 |
|
T219 |
17 |