Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22295

1

T1

1

T3

1

T5

6

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T1

2

T2

25

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20010

1

T1

2

T2

1

T3

1

auto[1]

5876

1

T1

1

T2

24

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T105	3		T36	1		T279	20
values[0]	55	1			T231	27		T338	5		T308	18
values[1]	697	1			T2	24		T4	14		T7	24
values[2]	656	1			T51	28		T63	27		T237	3
values[3]	776	1			T1	1		T151	11		T79	28
values[4]	709	1			T55	7		T51	20		T67	34
values[5]	848	1			T1	1		T3	2		T4	13
values[6]	597	1			T58	1		T59	14		T165	2
values[7]	725	1			T1	1		T3	1		T6	14
values[8]	602	1			T2	1		T64	13		T161	11
values[9]	3270	1			T5	6		T9	21		T10	3
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	716	1			T2	24		T7	24		T65	26
values[1]	868	1			T4	14		T51	28		T151	11
values[2]	673	1			T1	1		T154	18		T164	1
values[3]	742	1			T3	1		T4	13		T6	11
values[4]	832	1			T1	1		T7	25		T59	14
values[5]	579	1			T3	1		T58	1		T165	1
values[6]	2838	1			T1	1		T3	1		T5	6
values[7]	580	1			T2	1		T63	9		T64	13
values[8]	815	1			T51	18		T64	13		T161	1
values[9]	245	1			T11	6		T236	19		T67	23
minimum	16998	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T237	16		T184	8		T185	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	12		T7	11		T65	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T63	14		T264	10		T245	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T4	14		T51	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T164	1		T40	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T154	18		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	1		T51	10		T67	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T4	13		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T165	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	14		T59	9		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T58	1		T165	1		T151	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T64	17		T49	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T3	1		T5	6		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	1		T6	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T63	7		T64	13		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T166	1		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T161	1		T65	13		T176	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T51	10		T64	13		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T11	5		T178	1		T206	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T236	13		T67	11		T80	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16823	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T339	4		T282	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T185	6		T261	14		T175	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	12		T7	13		T65	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T63	13		T245	9		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T51	15		T151	10		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	2		T183	11		T14	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T303	8		T340	4		T109	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	10		T51	10		T67	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	6		T79	16		T53	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T209	12		T212	10		T182	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	11		T59	5		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T151	17		T50	8		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T49	3		T167	9		T163	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T9	19		T55	13		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	13		T166	11		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T63	2		T161	10		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T166	14		T81	1		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T65	11		T70	5		T156	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T51	8		T163	13		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T11	1		T178	12		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T236	6		T67	12		T80	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T339	3		T282	19		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T105	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T36	1		T279	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	15		T338	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	9		T295	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T237	16		T264	10		T185	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	12		T4	14		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T63	14		T183	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T51	13		T237	3		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T164	1		T182	1		T245	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T151	1		T79	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T51	10		T67	13		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	1		T154	18		T290	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T6	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	2		T4	13		T7	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T58	1		T165	2		T151	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T59	9		T64	17		T163	30
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T55	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T6	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T64	13		T161	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	1		T166	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T5	6		T9	2		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T51	10		T64	13		T236	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T105	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T279	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	12		T338	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T308	9		T295	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T185	6		T261	14		T257	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	12		T7	13		T65	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T63	13		T183	11		T241	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	15		T166	2		T236	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T245	9		T14	11		T121	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	10		T79	16		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	10		T67	21		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	6		T53	6		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	10		T212	10		T182	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	11		T48	12		T182	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T151	17		T50	8		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T59	5		T163	24		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	13		T164	9		T45	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	13		T166	11		T49	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T161	10		T45	16		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T166	14		T81	1		T158	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T9	19		T11	1		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T51	8		T236	6		T67	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T237	1		T184	1		T185	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	13		T7	14		T65	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T63	14		T264	1		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	1		T51	16		T151	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T164	1		T40	3		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T154	2		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	11		T51	11		T67	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T4	1		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T165	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	12		T59	6		T48	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T58	1		T165	1		T151	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T64	1		T49	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T3	1		T5	1		T9	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	1		T6	14		T166	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T63	3		T64	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T166	15		T81	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T161	1		T65	12		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	9		T64	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	5		T178	13		T206	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T236	7		T67	13		T80	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16940	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T339	4		T282	20		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T237	15		T184	7		T185	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	11		T7	10		T65	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T63	13		T264	9		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	13		T51	12		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	11		T14	8		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T154	16		T278	4		T303	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	9		T67	12		T50	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	12		T79	11		T199	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T212	14		T182	5		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	13		T59	8		T182	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T50	4		T167	10		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T64	16		T49	1		T167	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T5	5		T250	14		T219	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T243	2		T258	3		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T63	6		T64	12		T177	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T182	10		T247	3		T255	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T65	12		T176	3		T70	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T51	9		T64	12		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T11	1		T206	2		T249	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T236	12		T67	10		T80	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T339	3		T282	17		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T105	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T36	1		T279	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T231	13		T338	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T308	10		T295	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T237	1		T264	1		T185	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	13		T4	1		T7	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T63	14		T183	12		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	16		T237	1		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T164	1		T182	1		T245	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T151	11		T79	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T51	11		T67	22		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	7		T154	2		T290	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T6	11		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	2		T4	1		T7	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T58	1		T165	2		T151	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	6		T64	1		T163	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T55	14		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T6	14		T166	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T64	1		T161	11		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T166	15		T81	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T5	1		T9	21		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T51	9		T64	1		T236	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T279	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T231	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T308	8		T295	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T237	15		T264	9		T185	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	11		T4	13		T7	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T63	13		T184	18		T233	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	12		T237	2		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T245	11		T14	8		T192	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T79	11		T238	12		T26	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T51	9		T67	12		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T154	16		T53	1		T256	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	3		T212	14		T182	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	12		T7	13		T199	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T50	4		T167	10		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	8		T64	16		T163	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T199	1		T154	8		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T49	1		T167	14		T255	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T64	12		T169	4		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T182	10		T243	2		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T5	5		T11	1		T63	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T51	9		T64	12		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5