Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22273

1

T1

1

T3

2

T5

6

auto[ADC_CTRL_FILTER_COND_OUT]

3613

1

T1

2

T2

25

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19980

1

T1

2

T2

1

T3

2

auto[1]

5906

1

T1

1

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T11	6		T64	13		T65	24
values[0]	76	1			T65	26		T261	27		T328	13
values[1]	622	1			T2	24		T4	14		T7	24
values[2]	685	1			T51	28		T63	27		T237	3
values[3]	814	1			T1	1		T151	11		T166	3
values[4]	687	1			T55	7		T79	28		T67	34
values[5]	882	1			T1	1		T3	1		T4	13
values[6]	564	1			T3	1		T58	1		T165	2
values[7]	682	1			T1	1		T3	1		T6	14
values[8]	638	1			T2	1		T64	13		T161	11
values[9]	3042	1			T5	6		T9	21		T10	3
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	584	1			T2	24		T4	14		T7	24
values[1]	831	1			T51	28		T151	11		T63	27
values[2]	678	1			T1	1		T154	18		T164	1
values[3]	764	1			T3	1		T4	13		T6	11
values[4]	789	1			T1	1		T7	25		T59	14
values[5]	622	1			T3	2		T58	1		T165	1
values[6]	2828	1			T1	1		T5	6		T6	14
values[7]	615	1			T2	1		T63	9		T64	13
values[8]	864	1			T11	6		T51	18		T64	13
values[9]	147	1			T67	23		T80	18		T70	10
minimum	17164	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T185	2		T259	8		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	12		T4	14		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	13		T63	14		T264	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T151	1		T237	3		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T164	1		T40	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	1		T154	18		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T51	10		T67	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T4	13		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T165	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	14		T59	9		T199	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	2		T58	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T64	17		T49	4		T167	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T5	6		T9	2		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	1		T6	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T63	7		T64	13		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T166	1		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	5		T161	1		T65	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T51	10		T64	13		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T178	1		T341	7		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T67	11		T80	5		T70	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16898	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T65	15		T80	1		T170	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T185	6		T257	9		T311	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	12		T7	13		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T51	15		T63	13		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T151	10		T166	2		T236	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	2		T183	11		T14	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T186	3		T303	8		T340	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	10		T51	10		T67	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	6		T79	16		T53	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T209	12		T212	10		T182	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	11		T59	5		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T151	17		T50	8		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T49	3		T167	9		T163	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T9	19		T55	13		T160	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	13		T166	11		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T63	2		T161	10		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T166	14		T81	1		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T65	11		T70	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	8		T236	6		T163	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T178	12		T341	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T67	12		T80	13		T70	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T65	11		T80	1		T339	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T11	5		T65	13		T268	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T64	13		T67	11		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T261	13		T338	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T65	15		T328	13		T295	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T264	10		T231	15		T185	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	12		T4	14		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	13		T63	14		T26	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T237	3		T236	13		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T164	1		T40	12		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T151	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T67	13		T153	1		T168	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	1		T79	12		T154	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	1		T6	1		T51	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	1		T4	13		T7	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T58	1		T165	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T64	17		T163	30		T240	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T55	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T6	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T64	13		T161	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	1		T166	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T5	6		T9	2		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T51	10		T236	13		T80	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	1		T65	11		T314	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T67	12		T70	9		T22	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T261	14		T338	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T65	11		T295	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T231	12		T185	6		T217	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	12		T7	13		T80	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T51	15		T63	13		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T236	8		T162	10		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	2		T183	11		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T151	10		T166	2		T80	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T67	21		T153	8		T168	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T55	6		T79	16		T53	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	10		T51	10		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	11		T59	5		T48	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T151	17		T50	8		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T163	24		T240	10		T183	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T55	13		T164	9		T45	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	13		T166	11		T49	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T161	10		T45	16		T174	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T166	14		T81	1		T158	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T9	19		T160	8		T63	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	8		T236	6		T80	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T185	7		T259	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	13		T4	1		T7	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T51	16		T63	14		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T151	11		T237	1		T166	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T164	1		T40	3		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T154	2		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T51	11		T67	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T4	1		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T165	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	12		T59	6		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	2		T58	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T64	1		T49	6		T167	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T5	1		T9	21		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T6	14		T166	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T63	3		T64	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T166	15		T81	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	5		T161	1		T65	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	9		T64	1		T236	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T178	13		T341	7		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T67	13		T80	14		T70	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17018	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T65	12		T80	2		T170	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T185	1		T259	7		T333	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	11		T4	13		T7	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T51	12		T63	13		T264	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T237	2		T236	12		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	11		T14	8		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T154	16		T265	9		T278	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	9		T67	12		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	12		T79	11		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	3		T212	14		T182	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T59	8		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T50	4		T167	10		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T64	16		T49	1		T167	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T5	5		T250	14		T219	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T243	2		T247	3		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T63	6		T64	12		T177	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T182	10		T255	19		T310	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T65	12		T176	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T51	9		T64	12		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T341	3		T336	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T67	10		T80	4		T281	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T231	14		T261	12		T259	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T65	14		T328	12		T342	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	5		T65	12		T268	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T64	1		T67	13		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T261	15		T338	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T65	12		T328	1		T295	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T264	1		T231	13		T185	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	13		T4	1		T7	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T51	16		T63	14		T26	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T237	1		T236	9		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T164	1		T40	3		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T151	11		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T67	22		T153	9		T168	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T55	7		T79	17		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	1		T6	11		T51	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T4	1		T7	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T58	1		T165	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T64	1		T163	26		T240	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	1		T55	14		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T6	14		T166	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T64	1		T161	11		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T166	15		T81	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T5	1		T9	21		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T51	9		T236	7		T80	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T11	1		T65	12		T268	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T64	12		T67	10		T310	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T261	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T65	14		T328	12		T295	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T264	9		T231	14		T185	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	11		T4	13		T7	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T51	12		T63	13		T26	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T237	2		T236	12		T238	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	11		T245	11		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T80	14		T52	1		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T67	12		T168	9		T169	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T79	11		T154	16		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T51	9		T50	3		T212	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	12		T7	13		T59	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	4		T167	10		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T64	16		T163	28		T240	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T199	1		T154	8		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T49	1		T167	14		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T64	12		T169	4		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T182	10		T243	2		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T5	5		T63	6		T250	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T51	9		T236	12		T80	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5