Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22578

1

T1

3

T2

25

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3308

1

T3

2

T4

27

T7

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20253

1

T1

2

T2

25

T3

1

auto[1]

5633

1

T1

1

T3

2

T4

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	313	1			T151	11		T163	29		T183	12
values[0]	35	1			T154	5		T167	13		T182	13
values[1]	737	1			T4	14		T7	24		T58	1
values[2]	745	1			T3	1		T64	13		T237	16
values[3]	595	1			T1	1		T6	11		T51	28
values[4]	2783	1			T5	6		T9	21		T10	3
values[5]	427	1			T165	1		T80	22		T49	7
values[6]	719	1			T7	25		T11	6		T59	14
values[7]	722	1			T2	1		T3	1		T55	14
values[8]	971	1			T1	1		T4	13		T6	14
values[9]	912	1			T1	1		T2	24		T3	1
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	800	1			T4	14		T7	24		T166	15
values[1]	637	1			T3	1		T64	26		T237	16
values[2]	703	1			T1	1		T6	11		T51	28
values[3]	2651	1			T5	6		T9	21		T10	3
values[4]	499	1			T7	25		T11	6		T80	22
values[5]	780	1			T59	14		T63	27		T161	1
values[6]	673	1			T1	1		T2	1		T3	1
values[7]	803	1			T3	1		T4	13		T6	14
values[8]	1061	1			T1	1		T2	24		T51	18
values[9]	149	1			T151	11		T158	1		T70	10
minimum	17130	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T166	1		T153	1		T50	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	14		T7	11		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	1		T158	1		T70	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T64	26		T237	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T6	1		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T151	2		T236	26		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T5	6		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T55	1		T165	1		T65	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	14		T80	15		T49	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	5		T244	1		T176	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T161	1		T67	13		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T59	9		T63	14		T264	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T2	1		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T79	12		T67	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T6	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	13		T65	15		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T1	1		T2	12		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T80	1		T163	16		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T151	1		T158	1		T240	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T70	1		T179	5		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16865	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T167	11		T170	12		T246	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T166	14		T153	8		T50	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	13		T258	3		T206	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T158	14		T70	5		T178	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T166	11		T45	16		T105	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	10		T51	15		T63	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T151	17		T236	14		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T9	19		T160	8		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T55	6		T65	11		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	11		T80	7		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T11	1		T245	9		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T67	21		T164	9		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T59	5		T63	13		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T55	13		T51	10		T38	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T79	16		T67	12		T168	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	13		T161	10		T212	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T65	11		T166	2		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	12		T51	8		T167	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T80	1		T163	13		T183	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T151	10		T240	13		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T70	9		T235	11		T277	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	4		T67	1		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T167	2		T170	10		T246	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T151	1		T183	1		T281	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T163	16		T343	15		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T154	5		T182	3		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T167	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T58	1		T166	1		T238	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	14		T7	11		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T158	1		T70	12		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T64	13		T237	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	1		T6	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T151	1		T64	13		T236	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T5	6		T9	2		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T55	1		T151	1		T65	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T80	15		T49	4		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T165	1		T244	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	14		T161	1		T67	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	5		T59	9		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T55	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T67	11		T168	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T6	1		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T4	13		T65	15		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	1		T2	12		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T80	1		T70	1		T183	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T151	10		T183	11		T281	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T163	13		T343	15		T235	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T182	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T167	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T166	14		T238	8		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	13		T170	10		T246	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T158	14		T70	5		T178	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T166	11		T105	2		T216	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	10		T51	15		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T151	4		T236	8		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T9	19		T160	8		T270	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T55	6		T151	13		T65	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T80	7		T49	3		T170	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T231	4		T271	3		T340	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	11		T67	21		T48	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T59	5		T63	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T55	13		T164	9		T38	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T67	12		T168	8		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	13		T51	10		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T65	11		T166	2		T79	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	12		T51	8		T167	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T80	1		T70	9		T183	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T166	15		T153	9		T50	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	1		T7	14		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T152	1		T158	15		T70	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T64	2		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T6	11		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T151	19		T236	16		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T5	1		T9	21		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T55	7		T165	1		T65	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	12		T80	8		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	5		T244	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T161	1		T67	22		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T59	6		T63	14		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T2	1		T55	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T79	17		T67	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T6	14		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T65	12		T166	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	1		T2	13		T51	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T80	2		T163	14		T183	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T151	11		T158	1		T240	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T70	10		T179	1		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16989	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T167	3		T170	11		T246	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T50	4		T163	12		T156	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	13		T7	10		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T70	11		T27	1		T298	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T64	24		T237	15		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	12		T63	6		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T236	24		T199	1		T50	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T5	5		T250	14		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T65	12		T40	11		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	13		T80	14		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	1		T176	3		T245	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T67	12		T154	12		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T59	8		T63	13		T264	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T51	9		T38	8		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T79	11		T67	10		T168	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T64	16		T212	14		T240	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	12		T65	14		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	11		T51	9		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T163	15		T179	4		T248	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T240	13		T182	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T179	4		T277	10		T196	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T238	12		T199	2		T154	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T167	10		T170	11		T344	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T151	11		T183	12		T281	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T163	14		T343	16		T190	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T154	1		T182	11		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T167	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T58	1		T166	15		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T7	14		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	15		T70	6		T178	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T64	1		T237	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T6	11		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T151	5		T64	1		T236	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T5	1		T9	21		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T55	7		T151	14		T65	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T80	8		T49	6		T170	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T165	1		T244	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	12		T161	1		T67	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	5		T59	6		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	1		T55	14		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T67	13		T168	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	1		T6	14		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	1		T65	12		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	1		T2	13		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T80	2		T70	10		T183	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T281	10		T113	21		T342	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T163	15		T343	14		T345	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T154	4		T182	2		T259	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T167	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T238	12		T199	2		T50	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	13		T7	10		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T70	11		T36	4		T249	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T64	12		T237	15		T247	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	12		T63	6		T199	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T64	12		T236	12		T199	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T5	5		T250	14		T219	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T65	12		T236	12		T40	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T80	14		T49	1		T278	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T231	8		T265	9		T271	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	13		T67	12		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T59	8		T63	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	8		T206	10		T181	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T67	10		T168	9		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T51	9		T64	16		T212	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	12		T65	14		T79	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	11		T51	9		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T179	8		T248	1		T256	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5