Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T7	12		T151	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T67	22		T244	1		T163	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T5	1		T9	21		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T11	5		T51	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T165	1		T81	2		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	1		T176	1		T212	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T50	11		T170	11		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T199	1		T70	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T2	1		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T6	14		T64	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T51	16		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T4	1		T151	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T162	11		T238	9		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	11		T151	11		T236	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	3		T209	13		T182	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	11		T58	1		T236	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	13		T165	1		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T55	14		T161	1		T65	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T63	3		T38	13		T182	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T163	14		T121	12		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16938	1			T8	20		T54	10		T11	48
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	13		T199	1		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T67	12		T163	16		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T5	5		T65	14		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T51	9		T64	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T245	4		T261	13		T175	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T212	14		T168	10		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	4		T170	11		T258	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T199	2		T36	4		T263	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	12		T7	10		T59	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T64	16		T264	9		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T51	12		T237	15		T80	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	13		T64	12		T80	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T238	12		T176	3		T167	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T236	12		T67	10		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T50	3		T182	2		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	9		T236	12		T177	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	11		T63	13		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T65	12		T199	13		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T63	6		T38	8		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T163	15		T192	13		T196	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T11	1		T66	1		T69	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T151	5		T152	1		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T253	1		T259	1		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	1		T7	12		T163	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T161	11		T244	1		T163	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T5	1		T9	21		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	9		T64	1		T67	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T81	2		T158	1		T245	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	1		T3	1		T11	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T165	1		T254	6		T170	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T168	14		T164	10		T246	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T2	1		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T151	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T237	1		T166	3		T158	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T6	14		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T51	16		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	11		T151	11		T236	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T238	9		T176	1		T209	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	1		T152	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T2	13		T165	1		T63	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T55	14		T51	11		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16505	1			T8	20		T54	10		T11	47
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T267	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T268	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	13		T163	12		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T163	16		T245	12		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T5	5		T65	14		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T51	9		T64	12		T67	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T245	4		T261	13		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	1		T79	11		T212	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T170	11		T258	3		T231	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T168	10		T36	4		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	12		T7	10		T59	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T64	16		T199	2		T265	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T237	15		T169	4		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	13		T64	12		T154	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T51	12		T80	14		T167	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T236	12		T67	10		T80	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T238	12		T176	3		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T177	6		T169	12		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T2	11		T63	19		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T51	9		T65	12		T236	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5