Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22578

1

T1

3

T2

25

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3308

1

T3

2

T4

27

T7

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20253

1

T1

2

T2

25

T3

1

auto[1]

5633

1

T1

1

T3

2

T4

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T196	10		-	-		-	-
values[0]	65	1			T167	13		T269	1		T121	12
values[1]	711	1			T4	14		T7	24		T58	1
values[2]	761	1			T63	9		T64	13		T237	16
values[3]	583	1			T1	1		T3	1		T6	11
values[4]	2775	1			T5	6		T9	21		T10	3
values[5]	460	1			T11	6		T165	1		T80	22
values[6]	702	1			T7	25		T59	14		T63	27
values[7]	709	1			T2	1		T3	1		T55	14
values[8]	968	1			T1	1		T4	13		T6	14
values[9]	1215	1			T1	1		T2	24		T3	1
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1048	1			T4	14		T7	24		T58	1
values[1]	605	1			T3	1		T64	26		T237	16
values[2]	680	1			T1	1		T6	11		T55	7
values[3]	2676	1			T5	6		T9	21		T10	3
values[4]	511	1			T7	25		T11	6		T59	14
values[5]	790	1			T55	14		T63	27		T161	1
values[6]	722	1			T1	1		T2	1		T3	1
values[7]	696	1			T3	1		T4	13		T6	14
values[8]	960	1			T1	1		T2	24		T51	18
values[9]	271	1			T151	11		T158	1		T70	10
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T58	1		T166	1		T238	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T4	14		T7	11		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	1		T158	1		T70	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T64	26		T237	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T6	1		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	1		T151	2		T236	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T5	6		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T165	1		T65	13		T40	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	14		T80	15		T49	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	5		T59	9		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T55	1		T161	1		T67	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T63	14		T264	10		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T2	1		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T79	12		T67	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T6	1		T64	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	13		T65	15		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T1	1		T2	12		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T80	1		T183	1		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T151	1		T158	1		T240	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T70	1		T163	16		T179	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T166	14		T238	8		T153	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	13		T167	2		T170	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T158	14		T70	5		T178	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T166	11		T45	16		T105	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	10		T51	15		T63	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T55	6		T151	17		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T9	19		T160	8		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T65	11		T40	2		T271	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	11		T80	7		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	1		T59	5		T245	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	13		T67	21		T245	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T63	13		T246	2		T26	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	10		T161	10		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T79	16		T67	12		T168	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	13		T212	10		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T65	11		T166	2		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	12		T51	8		T167	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T80	1		T183	12		T246	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T151	10		T240	13		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T70	9		T163	13		T179	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T196	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T269	1		T272	8		T273	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T167	11		T121	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T58	1		T166	1		T238	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	14		T7	11		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T63	7		T158	1		T70	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T64	13		T237	16		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T6	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T151	2		T64	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T5	6		T9	2		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	1		T65	13		T236	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T80	15		T170	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	5		T165	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	14		T161	1		T67	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T59	9		T63	14		T176	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T55	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T67	11		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T6	1		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T4	13		T65	15		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T1	1		T2	12		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T80	1		T70	1		T163	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T272	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T167	2		T121	11		T275	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T166	14		T238	8		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	13		T170	10		T246	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T63	2		T158	14		T70	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T166	11		T105	2		T216	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	10		T51	15		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T151	17		T236	8		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T9	19		T160	8		T270	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T55	6		T65	11		T236	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T80	7		T170	2		T178	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T11	1		T216	13		T271	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	11		T67	21		T49	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T59	5		T63	13		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	13		T164	9		T38	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T67	12		T246	2		T174	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	13		T51	10		T161	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T65	11		T166	2		T79	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T2	12		T51	8		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T80	1		T70	9		T163	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T58	1		T166	15		T238	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T7	14		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	1		T158	15		T70	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T64	2		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T6	11		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T55	7		T151	19		T236	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T5	1		T9	21		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T165	1		T65	12		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	12		T80	8		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	5		T59	6		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T55	14		T161	1		T67	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T63	14		T264	1		T246	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T2	1		T51	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T79	17		T67	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T6	14		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	1		T65	12		T166	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T2	13		T51	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T80	2		T183	13		T246	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T151	11		T158	1		T240	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T70	10		T163	14		T179	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T238	12		T199	2		T50	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	13		T7	10		T167	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T70	11		T27	1		T263	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T64	24		T237	15		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	12		T63	6		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T236	24		T199	1		T50	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T5	5		T250	14		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T65	12		T40	11		T271	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	13		T80	14		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	1		T59	8		T176	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T67	12		T154	12		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T63	13		T264	9		T26	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T51	9		T38	8		T247	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T79	11		T67	10		T168	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T64	16		T212	14		T240	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	12		T65	14		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	11		T51	9		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T248	1		T256	7		T39	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T240	13		T182	10		T276	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T163	15		T179	8		T277	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T196	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T269	1		T272	11		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T167	3		T121	12		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T58	1		T166	15		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	1		T7	14		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T63	3		T158	15		T70	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T64	1		T237	1		T166	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T6	11		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T151	19		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T5	1		T9	21		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T55	7		T65	12		T236	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T80	8		T170	3		T178	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	5		T165	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	12		T161	1		T67	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T59	6		T63	14		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T55	14		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T67	13		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T6	14		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	1		T65	12		T166	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T1	1		T2	13		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T80	2		T70	10		T163	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T196	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T272	7		T273	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T167	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T238	12		T199	2		T50	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	13		T7	10		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T63	6		T70	11		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T64	12		T237	15		T247	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T51	12		T199	13		T169	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T64	12		T236	12		T199	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T5	5		T250	14		T219	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T65	12		T236	12		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T80	14		T278	4		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T265	9		T216	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	13		T67	12		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	8		T63	13		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	8		T206	10		T181	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T67	10		T156	2		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T51	9		T64	16		T212	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	12		T65	14		T79	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T2	11		T51	9		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T163	15		T179	8		T248	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5