Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22401

1

T1

1

T3

1

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3485

1

T1

2

T2

25

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19878

1

T2

1

T3

2

T4

14

auto[1]

6008

1

T1

3

T2

24

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T2	24		T165	1		-	-
values[0]	42	1			T183	13		T279	20		T197	1
values[1]	529	1			T2	1		T151	11		T64	13
values[2]	678	1			T6	25		T58	1		T236	19
values[3]	830	1			T1	1		T7	25		T151	5
values[4]	616	1			T55	14		T51	20		T165	1
values[5]	2681	1			T5	6		T7	24		T9	21
values[6]	1031	1			T4	14		T11	6		T51	28
values[7]	622	1			T3	1		T64	17		T236	21
values[8]	897	1			T1	1		T4	13		T63	27
values[9]	1008	1			T1	1		T3	2		T55	7
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T2	1		T6	14		T151	11
values[1]	624	1			T6	11		T236	19		T152	1
values[2]	852	1			T1	1		T7	25		T58	1
values[3]	2726	1			T5	6		T7	24		T9	21
values[4]	863	1			T51	46		T59	14		T80	2
values[5]	729	1			T4	14		T11	6		T151	14
values[6]	668	1			T3	1		T64	17		T236	21
values[7]	808	1			T1	2		T63	27		T166	3
values[8]	756	1			T3	1		T4	13		T55	7
values[9]	158	1			T2	24		T3	1		T161	1
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T151	1		T209	1		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T6	1		T64	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T199	3		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T236	13		T152	1		T179	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T151	1		T50	7		T154	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	1		T7	14		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T5	6		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	11		T55	1		T51	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T51	10		T59	9		T199	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T51	13		T80	1		T154	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T151	1		T64	13		T65	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	14		T11	5		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T64	17		T67	11		T50	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	1		T236	13		T79	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T63	14		T67	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T166	1		T80	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T4	13		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T55	1		T63	7		T65	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T30	8		T280	2		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T2	12		T3	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T151	10		T209	12		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	13		T170	2		T183	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	10		T163	13		T281	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T236	6		T258	3		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T151	4		T50	8		T70	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	11		T161	10		T81	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	862	1			T9	19		T160	8		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	13		T55	13		T51	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T51	8		T59	5		T167	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T51	15		T80	1		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	13		T65	11		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	1		T26	12		T249	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T67	12		T240	23		T178	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T236	8		T79	16		T40	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T63	13		T67	21		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T166	2		T80	13		T168	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T166	14		T162	10		T49	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T55	6		T63	2		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T30	3		T282	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T2	12		T153	8		T45	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T165	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T2	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T279	13		T266	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T183	1		T197	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	1		T70	1		T163	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	1		T64	13		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	1		T209	1		T40	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T58	1		T236	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T151	1		T199	3		T50	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T7	14		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T152	1		T244	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T55	1		T51	10		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T5	6		T9	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	11		T154	5		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T59	9		T151	1		T64	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T4	14		T11	5		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T64	17		T67	11		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T236	13		T79	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	1		T4	13		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T166	1		T80	5		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T237	19		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T1	1		T3	1		T55	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T2	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T279	7		T266	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	10		T163	13		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T170	2		T255	17		T121	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	10		T209	12		T40	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	13		T236	6		T248	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	4		T50	8		T70	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	11		T161	10		T81	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T70	9		T283	2		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	13		T51	10		T80	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T9	19		T51	8		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	13		T178	12		T246	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T59	5		T151	13		T65	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	1		T51	15		T80	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T67	12		T156	5		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T236	8		T79	16		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T63	13		T67	21		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T166	2		T80	13		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T166	14		T162	10		T49	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T55	6		T63	2		T65	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T151	11		T209	13		T70	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T6	14		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	11		T199	1		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T236	7		T152	1		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T151	5		T50	11		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	1		T7	12		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T5	1		T9	21		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	14		T55	14		T51	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T51	9		T59	6		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	16		T80	2		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	14		T64	1		T65	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	1		T11	5		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T64	1		T67	13		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T236	9		T79	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	1		T63	14		T67	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T166	3		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T4	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T55	7		T63	3		T65	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T30	8		T280	2		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T2	13		T3	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	11		T182	2		T245	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T64	12		T176	3		T255	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T199	2		T163	15		T281	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T236	12		T179	4		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	4		T154	8		T177	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	13		T154	12		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T5	5		T250	14		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	10		T51	9		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T51	9		T59	8		T199	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	12		T154	4		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T64	12		T65	14		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	13		T11	1		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T64	16		T67	10		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T236	12		T79	11		T40	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T63	13		T67	12		T240	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T80	4		T168	10		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	12		T237	17		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T63	6		T65	12		T238	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T30	3		T284	2		T285	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T2	11		T169	4		T243	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T165	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T2	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T279	8		T266	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T183	13		T197	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T151	11		T70	1		T163	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	1		T64	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	11		T209	13		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	14		T58	1		T236	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T151	5		T199	1		T50	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	1		T7	12		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T152	1		T244	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	14		T51	11		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T5	1		T9	21		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	14		T154	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T59	6		T151	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	1		T11	5		T51	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T64	1		T67	13		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T236	9		T79	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T1	1		T4	1		T63	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T166	3		T80	14		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T237	2		T166	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T1	1		T3	1		T55	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T2	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T279	12		T266	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T163	15		T182	2		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T64	12		T176	3		T255	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T40	11		T231	8		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T236	12		T179	4		T278	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T199	2		T50	4		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	13		T163	16		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T231	14		T15	1		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	9		T80	14		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T5	5		T51	9		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T7	10		T154	4		T27	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T59	8		T64	12		T65	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	13		T11	1		T51	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T64	16		T67	10		T50	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T236	12		T79	11		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	12		T63	13		T67	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T80	4		T168	10		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T237	17		T49	1		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T63	6		T65	12		T238	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5