Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22547

1

T2

25

T4

27

T5

6

auto[ADC_CTRL_FILTER_COND_OUT]

3339

1

T1

3

T3

3

T6

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20159

1

T1

2

T2

25

T3

1

auto[1]

5727

1

T1

1

T3

2

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	239	1			T4	14		T63	27		T176	4
values[0]	20	1			T288	3		T295	17		-	-
values[1]	772	1			T165	1		T161	1		T79	28
values[2]	931	1			T59	14		T165	1		T64	30
values[3]	879	1			T1	1		T3	1		T4	13
values[4]	805	1			T2	24		T151	5		T166	12
values[5]	2803	1			T5	6		T6	11		T7	25
values[6]	688	1			T1	1		T55	14		T51	38
values[7]	518	1			T1	1		T3	1		T55	7
values[8]	355	1			T6	14		T58	1		T166	3
values[9]	949	1			T2	1		T3	1		T11	6
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	788	1			T165	1		T161	11		T236	19
values[1]	986	1			T1	1		T4	13		T59	14
values[2]	826	1			T2	24		T3	1		T7	24
values[3]	2833	1			T5	6		T7	25		T9	21
values[4]	713	1			T6	11		T51	46		T67	23
values[5]	692	1			T1	1		T3	1		T55	14
values[6]	450	1			T1	1		T6	14		T55	7
values[7]	405	1			T64	13		T166	3		T236	21
values[8]	938	1			T2	1		T3	1		T4	14
values[9]	107	1			T163	29		T286	1		T304	6
minimum	17148	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T161	1		T80	15		T169	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	1		T236	13		T79	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	13		T59	9		T64	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T1	1		T165	1		T64	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	12		T7	11		T151	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	1		T151	1		T238	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T5	6		T9	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	14		T166	1		T154	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T51	23		T67	11		T49	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	1		T156	15		T290	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T51	10		T152	1		T50	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T3	1		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	1		T55	1		T199	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	1		T58	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T64	13		T170	1		T240	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T166	1		T236	13		T199	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	1		T4	14		T237	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T3	1		T11	5		T63	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T291	1		T292	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T163	16		T286	1		T304	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16863	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T154	5		T26	4		T278	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T161	10		T80	7		T170	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T236	6		T79	16		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T59	5		T81	1		T178	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T50	8		T167	2		T182	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	12		T7	13		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	13		T238	8		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T9	19		T160	8		T270	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	11		T166	11		T70	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T51	23		T67	12		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T6	10		T156	11		T75	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	10		T70	5		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T55	13		T65	11		T212	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	13		T55	6		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	12		T240	13		T287	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T170	12		T240	10		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T166	2		T236	8		T45	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T162	10		T170	10		T248	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T63	13		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T260	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T163	13		T304	4		T306	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T26	4		T261	14		T125	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T4	14		T176	4		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T63	14		T40	5		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	1		T295	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T161	1		T80	15		T169	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T165	1		T79	12		T154	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T59	9		T64	17		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T165	1		T64	13		T237	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	13		T7	11		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T3	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	12		T151	1		T80	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T166	1		T238	13		T154	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T5	6		T9	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	1		T7	14		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T51	20		T152	1		T50	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T55	1		T65	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T55	1		T199	2		T167	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T3	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T6	1		T170	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T58	1		T166	1		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T64	13		T237	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T3	1		T11	5		T65	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T248	7		T287	5		T308	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T63	13		T40	6		T307	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	2		T295	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T80	7		T254	5		T170	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T79	16		T240	13		T178	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T59	5		T161	10		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T236	6		T50	8		T167	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	13		T151	10		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T151	13		T153	8		T158	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	12		T151	4		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T166	11		T238	8		T70	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T9	19		T51	15		T160	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T6	10		T7	11		T75	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	18		T70	5		T38	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T55	13		T65	11		T212	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T55	6		T167	9		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T48	12		T240	13		T287	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T6	13		T170	12		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T166	2		T236	8		T45	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T162	10		T170	10		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	1		T65	11		T67	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T161	11		T80	8		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T165	1		T236	7		T79	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T59	6		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T1	1		T165	1		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	13		T7	14		T151	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T151	14		T238	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T5	1		T9	21		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	12		T166	12		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T51	25		T67	13		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	11		T156	12		T290	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T51	11		T152	1		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T3	1		T55	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	14		T55	7		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	1		T58	1		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T64	1		T170	13		T240	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T166	3		T236	9		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T4	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	1		T11	5		T63	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T291	1		T292	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T163	14		T286	1		T304	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16963	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T154	1		T26	5		T278	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T80	14		T169	4		T231	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T236	12		T79	11		T240	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	12		T59	8		T64	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T64	12		T237	2		T50	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	11		T7	10		T63	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T238	12		T163	12		T258	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T5	5		T250	14		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	13		T154	8		T245	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T51	21		T67	10		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T156	14		T243	2		T75	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T51	9		T50	3		T70	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	14		T212	14		T264	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T199	1		T167	14		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T240	14		T259	2		T277	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T64	12		T240	2		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T236	12		T199	2		T174	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	13		T237	15		T176	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	1		T63	13		T65	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T163	15		T304	1		T306	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T251	11		T234	12		T309	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T154	4		T26	3		T278	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T4	1		T176	1		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T63	14		T40	7		T307	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T288	3		T295	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T161	1		T80	8		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T165	1		T79	17		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T59	6		T64	1		T161	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T165	1		T64	1		T237	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T4	1		T7	14		T151	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	1		T3	1		T151	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	13		T151	5		T80	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T166	12		T238	9		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T5	1		T9	21		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	11		T7	12		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T51	20		T152	1		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T55	14		T65	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	7		T199	1		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	1		T3	1		T48	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	14		T170	13		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T58	1		T166	3		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T64	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	1		T11	5		T65	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T4	13		T176	3		T310	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T63	13		T40	4		T192	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T295	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T80	14		T169	4		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T79	11		T154	4		T240	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T59	8		T64	16		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T64	12		T237	2		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	12		T7	10		T63	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	12		T27	1		T269	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	11		T80	4		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T238	12		T154	8		T245	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T5	5		T51	12		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	13		T75	7		T265	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T51	18		T50	3		T70	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T65	14		T212	14		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T199	1		T167	14		T169	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T240	14		T264	9		T262	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T52	1		T296	1		T112	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T236	12		T298	10		T259	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T64	12		T237	15		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	1		T65	12		T67	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5