Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20113

1

T1

2

T2

25

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

5773

1

T1

1

T4

27

T5

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20007

1

T1

1

T2

1

T3

1

auto[1]

5879

1

T1

2

T2

24

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T158	15		T251	12		T300	1
values[0]	56	1			T17	6		T311	2		T312	14
values[1]	920	1			T3	1		T7	24		T64	13
values[2]	586	1			T2	1		T151	14		T236	21
values[3]	671	1			T1	1		T4	13		T55	14
values[4]	597	1			T1	2		T6	11		T11	6
values[5]	683	1			T2	24		T4	14		T59	14
values[6]	708	1			T6	14		T51	18		T165	1
values[7]	723	1			T3	1		T7	25		T55	7
values[8]	851	1			T51	28		T58	1		T151	16
values[9]	3136	1			T3	1		T5	6		T9	21
minimum	16927	1			T8	20		T54	10		T11	48

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1032	1			T3	1		T7	24		T64	13
values[1]	2756	1			T1	1		T2	1		T5	6
values[2]	613	1			T4	13		T51	20		T63	9
values[3]	702	1			T1	2		T4	14		T6	11
values[4]	683	1			T2	24		T51	18		T166	12
values[5]	784	1			T6	14		T7	25		T59	14
values[6]	726	1			T3	1		T55	7		T51	28
values[7]	741	1			T151	16		T161	1		T65	24
values[8]	696	1			T3	1		T58	1		T67	23
values[9]	182	1			T156	10		T14	26		T265	10
minimum	16971	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T7	11		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T64	13		T236	13		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	1		T2	1		T67	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1535	1			T5	6		T9	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T63	7		T64	17		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	13		T51	10		T64	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T50	6		T231	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T4	14		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	12		T154	5		T70	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T51	10		T166	1		T167	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T65	15		T244	1		T163	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T7	14		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T55	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T51	13		T165	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	1		T154	13		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T151	2		T65	13		T237	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T80	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T58	1		T67	11		T199	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T14	15		T265	10		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T156	5		T216	1		T310	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16836	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T197	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	13		T166	2		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T236	8		T170	12		T174	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T67	21		T40	6		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	935	1			T9	19		T55	13		T160	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T63	2		T166	14		T236	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T51	10		T161	10		T79	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T231	12		T26	12		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T6	10		T11	1		T80	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	12		T70	9		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T51	8		T166	11		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T65	11		T163	13		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	13		T7	11		T59	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	6		T238	8		T81	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	15		T162	10		T80	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T168	13		T45	7		T314	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T151	14		T65	11		T212	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T80	1		T158	14		T254	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T67	12		T164	9		T245	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T14	11		T309	13		T315	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T156	5		T216	1		T316	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	4		T67	1		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T158	1		T251	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T311	1		T317	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T17	3		T312	1		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T7	11		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T64	13		T170	1		T243	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T67	13		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	1		T236	13		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T63	7		T64	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	13		T55	1		T64	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T152	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T6	1		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	12		T244	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	14		T59	9		T50	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T165	1		T154	5		T163	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	1		T51	10		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T55	1		T65	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	14		T165	1		T80	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T152	1		T154	13		T168	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T51	13		T58	1		T151	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	1		T161	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1670	1			T5	6		T9	2		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16808	1			T8	20		T54	10		T11	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T158	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T311	1		T317	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T17	3		T312	13		T318	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	13		T166	2		T163	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T170	2		T174	6		T241	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T67	21		T40	6		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T151	13		T236	8		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T63	2		T166	14		T236	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T55	13		T161	10		T79	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T153	8		T105	2		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	10		T11	1		T51	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T70	9		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T59	5		T50	8		T168	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T163	13		T170	10		T182	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	13		T51	8		T63	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T55	6		T65	11		T238	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	11		T80	13		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T168	13		T45	16		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	15		T151	14		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T80	1		T45	7		T254	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	983	1			T9	19		T160	8		T270	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	1		T7	14		T166	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T64	1		T236	9		T170	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T2	1		T67	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1264	1			T5	1		T9	21		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T63	3		T64	1		T166	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	1		T51	11		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	1		T50	3		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T4	1		T6	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	13		T154	1		T70	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	9		T166	12		T167	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T65	12		T244	1		T163	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	14		T7	12		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T55	7		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T51	16		T165	1		T162	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T161	1		T154	1		T70	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	16		T65	12		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T80	2		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T58	1		T67	13		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T14	18		T265	1		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T156	6		T216	2		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16944	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T197	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	10		T163	16		T174	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T64	12		T236	12		T243	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T67	12		T40	4		T262	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1206	1			T5	5		T250	14		T219	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T63	6		T64	16		T236	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	12		T51	9		T64	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	3		T231	15		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	13		T11	1		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	11		T154	4		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T51	9		T167	10		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	14		T163	15		T170	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	13		T59	8		T63	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T237	15		T238	12		T319	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	12		T80	4		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	12		T168	10		T296	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	12		T237	2		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T240	14		T243	2		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T67	10		T199	1		T245	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T14	8		T265	9		T309	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T156	4		T310	11		T268	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T217	17		T302	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T158	15		T251	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T311	2		T317	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T17	6		T312	14		T318	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	1		T7	14		T166	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T64	1		T170	3		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	1		T67	22		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T151	14		T236	9		T170	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T63	3		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T55	14		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T152	1		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T6	11		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	13		T244	1		T70	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	1		T59	6		T50	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T165	1		T154	1		T163	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	14		T51	9		T63	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T55	7		T65	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	12		T165	1		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T152	1		T154	1		T168	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T51	16		T58	1		T151	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	1		T161	1		T80	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T5	1		T9	21		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T8	20		T54	10		T11	48
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T251	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T317	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	10		T163	16		T174	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T64	12		T243	12		T278	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T67	12		T40	4		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T236	12		T240	2		T185	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T63	6		T64	16		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	12		T64	12		T79	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T50	3		T169	4		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	1		T51	9		T40	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	11		T167	14		T231	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	13		T59	8		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T154	4		T163	15		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T51	9		T63	13		T199	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T65	14		T237	15		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	13		T80	4		T154	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T154	12		T168	10		T265	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T51	12		T65	12		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T240	14		T243	2		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T5	5		T250	14		T219	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5