Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25886

1

T1

3

T2

25

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22508

1

T1

2

T2

1

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3378

1

T1

1

T2

24

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19739

1

T1

2

T2

25

T3

2

auto[1]

6147

1

T1

1

T3

1

T5

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22044

1

T1

3

T2

13

T3

3

auto[1]

3842

1

T2

12

T6

23

T7

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	765	1			T11	1		T165	1		T66	1
values[0]	7	1			T151	5		T260	1		T197	1
values[1]	645	1			T3	1		T7	25		T161	11
values[2]	2846	1			T5	6		T9	21		T10	3
values[3]	766	1			T1	1		T3	1		T11	6
values[4]	736	1			T165	1		T168	24		T164	10
values[5]	552	1			T1	2		T2	1		T4	13
values[6]	691	1			T4	14		T6	14		T51	28
values[7]	722	1			T3	1		T6	11		T151	11
values[8]	661	1			T238	21		T152	1		T50	6
values[9]	990	1			T2	24		T55	14		T51	20
minimum	16505	1			T8	20		T54	10		T11	47

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	584	1			T3	1		T7	25		T151	5
values[1]	2887	1			T1	1		T5	6		T9	21
values[2]	801	1			T3	1		T165	1		T81	2
values[3]	713	1			T55	7		T199	3		T50	15
values[4]	577	1			T1	2		T2	1		T4	13
values[5]	600	1			T3	1		T4	14		T51	28
values[6]	820	1			T6	11		T151	11		T236	19
values[7]	716	1			T51	20		T236	21		T152	1
values[8]	892	1			T2	24		T55	14		T58	1
values[9]	197	1			T63	9		T163	29		T38	21
minimum	17099	1			T8	20		T54	10		T11	48

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

4181

1

T2

11

T4

25

T5

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	1		T7	14		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T67	13		T244	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T1	1		T5	6		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	5		T51	10		T64	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T165	1		T158	1		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T81	1		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T170	12		T183	1		T258	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	1		T199	3		T50	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	1		T2	1		T4	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T1	1		T6	1		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T51	13		T237	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	14		T151	1		T64	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T236	13		T162	1		T67	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T151	1		T80	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T152	1		T50	6		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T51	10		T236	13		T177	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T165	1		T63	14		T237	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T2	12		T55	1		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T63	7		T38	9		T182	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T163	16		T156	5		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16855	1			T8	20		T54	10		T11	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T163	17		T320	1		T213	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T7	11		T151	4		T178	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T67	21		T45	16		T245	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T9	19		T160	8		T65	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T51	8		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T254	5		T170	12		T245	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T81	1		T212	10		T168	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T170	10		T183	2		T258	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	6		T50	8		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	5		T166	2		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	13		T7	13		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	15		T158	14		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T151	13		T80	13		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T236	6		T162	10		T67	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	10		T151	10		T80	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T209	12		T26	12		T249	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T51	10		T236	8		T45	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T63	13		T166	11		T153	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	12		T55	13		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T63	2		T38	12		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T163	13		T156	5		T121	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	4		T67	1		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T163	12		T321	13		T266	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	522	1			T11	1		T165	1		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T163	16		T156	5		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T260	1		T197	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T7	14		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T161	1		T67	13		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T5	6		T9	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T51	10		T64	13		T49	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T79	12		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T11	5		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T165	1		T254	1		T170	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T168	11		T164	1		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T2	1		T4	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	1		T7	11		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T51	13		T166	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	14		T6	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T237	16		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T151	1		T80	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T238	13		T152	1		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T176	4		T45	1		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T63	21		T166	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T2	12		T55	1		T51	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16386	1			T8	20		T54	10		T11	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T153	8		T40	6		T182	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T163	13		T156	5		T322	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T151	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	11		T163	12		T178	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T161	10		T67	21		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T9	19		T160	8		T65	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	8		T49	3		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T79	16		T178	13		T245	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T81	1		T212	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T254	5		T170	22		T183	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T168	13		T164	9		T248	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T59	5		T170	2		T206	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	13		T55	6		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	15		T166	2		T158	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	13		T151	13		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T236	6		T162	10		T67	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	10		T151	10		T80	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T238	8		T209	12		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	7		T240	13		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T63	15		T166	11		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	12		T55	13		T51	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	4		T67	1		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T7	12		T151	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T67	22		T244	1		T45	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T1	1		T5	1		T9	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	5		T51	9		T64	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T165	1		T158	1		T254	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T81	2		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T170	11		T183	3		T258	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	7		T199	1		T50	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T2	1		T4	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T6	14		T7	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T51	16		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	1		T151	14		T64	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T236	7		T162	11		T67	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	11		T151	11		T80	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T152	1		T50	3		T209	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	11		T236	9		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T165	1		T63	14		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	13		T55	14		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T63	3		T38	13		T182	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T163	14		T156	6		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16972	1			T8	20		T54	10		T11	48
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T163	13		T320	1		T213	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	13		T199	1		T247	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T67	12		T245	12		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T5	5		T65	14		T79	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T11	1		T51	9		T64	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T245	4		T269	7		T261	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T212	14		T168	10		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T170	11		T258	3		T231	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T199	2		T50	4		T36	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	12		T59	8		T64	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T7	10		T256	14		T304	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	12		T237	15		T40	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	13		T64	12		T80	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T236	12		T67	10		T238	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T80	14		T176	3		T75	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	3		T169	12		T26	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	9		T236	12		T177	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T63	13		T237	2		T154	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	11		T65	12		T199	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T63	6		T38	8		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T163	15		T156	4		T296	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T163	12		T243	2		T251	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T163	16		T213	13		T321	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	507	1			T11	1		T165	1		T66	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T163	14		T156	6		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T151	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T260	1		T197	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	1		T7	12		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T161	11		T67	22		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T5	1		T9	21		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	9		T64	1		T49	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T79	17		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T11	5		T81	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T165	1		T254	6		T170	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T168	14		T164	10		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T2	1		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T7	14		T55	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T51	16		T166	3		T158	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T6	14		T151	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T237	1		T236	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	11		T151	11		T80	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T238	9		T152	1		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T176	1		T45	8		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T63	17		T166	12		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	13		T55	14		T51	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16505	1			T8	20		T54	10		T11	47
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T237	2		T40	4		T182	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T163	15		T156	4		T259	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	13		T163	12		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T67	12		T163	16		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T5	5		T65	14		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T51	9		T64	12		T49	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T79	11		T179	4		T245	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T212	14		T240	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T170	11		T258	3		T231	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T168	10		T36	4		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	12		T59	8		T64	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T7	10		T199	2		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	12		T40	11		T169	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	13		T64	12		T154	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T237	15		T236	12		T67	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T80	18		T75	7		T181	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T238	12		T50	3		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T176	3		T240	13		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T63	19		T154	20		T38	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T2	11		T51	9		T65	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21705

1

T1

3

T2

14

T3

3

auto[1]

auto[0]

4181

1

T2

11

T4

25

T5

5