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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.09


Total test records in report: 918
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T791 /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2277911615 Aug 07 05:16:35 PM PDT 24 Aug 07 05:18:19 PM PDT 24 164475389974 ps
T792 /workspace/coverage/default/3.adc_ctrl_stress_all.2827684852 Aug 07 05:13:07 PM PDT 24 Aug 07 05:13:10 PM PDT 24 1214277251 ps
T285 /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2512405242 Aug 07 05:14:52 PM PDT 24 Aug 07 05:20:37 PM PDT 24 569930133050 ps
T82 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1356453159 Aug 07 06:24:38 PM PDT 24 Aug 07 06:24:44 PM PDT 24 9121845314 ps
T793 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2369087854 Aug 07 06:24:46 PM PDT 24 Aug 07 06:24:47 PM PDT 24 416540595 ps
T76 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1567281691 Aug 07 06:24:46 PM PDT 24 Aug 07 06:24:50 PM PDT 24 5071457971 ps
T110 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.628973272 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:49 PM PDT 24 590626937 ps
T85 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2040782098 Aug 07 06:24:32 PM PDT 24 Aug 07 06:24:35 PM PDT 24 2656337208 ps
T86 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.215476789 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:56 PM PDT 24 608374712 ps
T794 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.877918743 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 414242794 ps
T77 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.211125205 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:52 PM PDT 24 4597823731 ps
T795 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.182586489 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:51 PM PDT 24 350258426 ps
T91 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3683285428 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:53 PM PDT 24 338139487 ps
T92 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1189015497 Aug 07 06:24:30 PM PDT 24 Aug 07 06:24:32 PM PDT 24 551710072 ps
T796 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2083718547 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:53 PM PDT 24 403389803 ps
T83 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4005344748 Aug 07 06:24:45 PM PDT 24 Aug 07 06:24:49 PM PDT 24 4668398474 ps
T84 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2019303603 Aug 07 06:24:52 PM PDT 24 Aug 07 06:25:04 PM PDT 24 4304489445 ps
T87 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.757359361 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:43 PM PDT 24 4096317747 ps
T96 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3498251913 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:55 PM PDT 24 544966274 ps
T93 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2110928070 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:59 PM PDT 24 486482109 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2922699702 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:48 PM PDT 24 398573758 ps
T797 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3614769083 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:58 PM PDT 24 366054394 ps
T78 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.902283103 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:40 PM PDT 24 2708901872 ps
T798 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1661166753 Aug 07 06:24:39 PM PDT 24 Aug 07 06:24:41 PM PDT 24 367979820 ps
T799 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1526650279 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 321111892 ps
T148 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.586122448 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:48 PM PDT 24 1025842685 ps
T97 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.675719620 Aug 07 06:24:44 PM PDT 24 Aug 07 06:25:06 PM PDT 24 8233760946 ps
T100 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.209322842 Aug 07 06:24:55 PM PDT 24 Aug 07 06:25:02 PM PDT 24 7682998284 ps
T144 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1977887085 Aug 07 06:24:46 PM PDT 24 Aug 07 06:24:49 PM PDT 24 2718166156 ps
T800 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.748860067 Aug 07 06:24:45 PM PDT 24 Aug 07 06:24:47 PM PDT 24 473060390 ps
T145 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3886226858 Aug 07 06:24:40 PM PDT 24 Aug 07 06:24:42 PM PDT 24 2127669125 ps
T801 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4175512862 Aug 07 06:24:58 PM PDT 24 Aug 07 06:25:00 PM PDT 24 412493284 ps
T802 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2323931030 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:42 PM PDT 24 350425142 ps
T98 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2162938323 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:58 PM PDT 24 375393895 ps
T146 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2737365521 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:47 PM PDT 24 4398152689 ps
T803 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2167286755 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 463923499 ps
T132 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4215016814 Aug 07 06:24:40 PM PDT 24 Aug 07 06:24:41 PM PDT 24 494509719 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2603732548 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:52 PM PDT 24 365004839 ps
T804 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1882710053 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:53 PM PDT 24 285752096 ps
T805 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1381686276 Aug 07 06:24:45 PM PDT 24 Aug 07 06:24:49 PM PDT 24 4667710469 ps
T134 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1872939273 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:49 PM PDT 24 464658897 ps
T99 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2194999302 Aug 07 06:24:40 PM PDT 24 Aug 07 06:24:42 PM PDT 24 359873929 ps
T806 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3084849817 Aug 07 06:24:42 PM PDT 24 Aug 07 06:24:44 PM PDT 24 690197499 ps
T147 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1432581493 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:56 PM PDT 24 2223823611 ps
T807 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3380167858 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:57 PM PDT 24 4389014624 ps
T135 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3662681227 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 509058307 ps
T808 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.389545032 Aug 07 06:25:00 PM PDT 24 Aug 07 06:25:01 PM PDT 24 359630590 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1887572198 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:55 PM PDT 24 513859956 ps
T136 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2234615206 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:48 PM PDT 24 370995858 ps
T810 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4242793873 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 478820082 ps
T811 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.564478585 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 412633244 ps
T137 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.143752309 Aug 07 06:24:43 PM PDT 24 Aug 07 06:24:46 PM PDT 24 375804044 ps
T95 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2492201023 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:51 PM PDT 24 392390590 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1118015204 Aug 07 06:24:34 PM PDT 24 Aug 07 06:24:36 PM PDT 24 513048285 ps
T813 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1072101162 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:49 PM PDT 24 554053426 ps
T138 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.913017862 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:54 PM PDT 24 443036942 ps
T814 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2728506212 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:50 PM PDT 24 503400456 ps
T815 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.498445265 Aug 07 06:24:42 PM PDT 24 Aug 07 06:24:43 PM PDT 24 278099735 ps
T816 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3609719200 Aug 07 06:24:53 PM PDT 24 Aug 07 06:25:03 PM PDT 24 4596385990 ps
T139 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.968234677 Aug 07 06:24:48 PM PDT 24 Aug 07 06:25:19 PM PDT 24 34551871875 ps
T817 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4027380678 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 436669170 ps
T101 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.755005548 Aug 07 06:24:53 PM PDT 24 Aug 07 06:25:05 PM PDT 24 8041007495 ps
T818 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.345128493 Aug 07 06:24:57 PM PDT 24 Aug 07 06:24:58 PM PDT 24 426353869 ps
T819 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2145052685 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:50 PM PDT 24 461133520 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1343791883 Aug 07 06:24:46 PM PDT 24 Aug 07 06:24:48 PM PDT 24 396847538 ps
T820 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.178549452 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 388706505 ps
T821 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3144312023 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:50 PM PDT 24 368398589 ps
T822 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2892419816 Aug 07 06:24:57 PM PDT 24 Aug 07 06:25:00 PM PDT 24 2732569148 ps
T823 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.584908444 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:53 PM PDT 24 548819616 ps
T824 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2974525135 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 444289031 ps
T825 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2431854805 Aug 07 06:25:15 PM PDT 24 Aug 07 06:25:16 PM PDT 24 426374236 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2807997936 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:52 PM PDT 24 2544017299 ps
T827 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1945580284 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:55 PM PDT 24 430050073 ps
T828 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2439900168 Aug 07 06:25:05 PM PDT 24 Aug 07 06:25:07 PM PDT 24 376406594 ps
T346 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.829060346 Aug 07 06:24:43 PM PDT 24 Aug 07 06:24:51 PM PDT 24 8358552256 ps
T829 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4051902590 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:42 PM PDT 24 324323837 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2589407399 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:57 PM PDT 24 4098332247 ps
T831 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.52985 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:50 PM PDT 24 521339531 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1423715672 Aug 07 06:24:54 PM PDT 24 Aug 07 06:25:06 PM PDT 24 4810173126 ps
T833 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3153178894 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:56 PM PDT 24 378946020 ps
T834 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3235483514 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:54 PM PDT 24 489656225 ps
T835 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.282744217 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:47 PM PDT 24 474161163 ps
T836 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2004440044 Aug 07 06:24:47 PM PDT 24 Aug 07 06:25:11 PM PDT 24 8897033955 ps
T837 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.400761644 Aug 07 06:24:37 PM PDT 24 Aug 07 06:24:43 PM PDT 24 4630331292 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1221138653 Aug 07 06:24:35 PM PDT 24 Aug 07 06:24:36 PM PDT 24 633273336 ps
T839 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2085596089 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:50 PM PDT 24 383746279 ps
T840 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2787737519 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:54 PM PDT 24 494846107 ps
T141 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.38696861 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:43 PM PDT 24 603218570 ps
T841 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.354438806 Aug 07 06:24:34 PM PDT 24 Aug 07 06:24:36 PM PDT 24 613847308 ps
T842 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2038663924 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:57 PM PDT 24 2119379079 ps
T142 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.181803242 Aug 07 06:24:58 PM PDT 24 Aug 07 06:24:59 PM PDT 24 360468235 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.416686578 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:50 PM PDT 24 935480818 ps
T844 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.215739868 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:57 PM PDT 24 4240223028 ps
T845 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3280335224 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:54 PM PDT 24 4601604325 ps
T846 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2621900940 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:52 PM PDT 24 2584317807 ps
T143 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1523597041 Aug 07 06:24:38 PM PDT 24 Aug 07 06:24:39 PM PDT 24 495721941 ps
T847 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3996905988 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:57 PM PDT 24 444162643 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.761536616 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:53 PM PDT 24 838995188 ps
T849 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2695799569 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:46 PM PDT 24 466290979 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1100595810 Aug 07 06:24:48 PM PDT 24 Aug 07 06:25:43 PM PDT 24 25812059102 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3758073649 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:52 PM PDT 24 460915005 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3730848693 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:57 PM PDT 24 552268010 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4261001698 Aug 07 06:24:35 PM PDT 24 Aug 07 06:24:37 PM PDT 24 917425204 ps
T854 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2605719622 Aug 07 06:24:58 PM PDT 24 Aug 07 06:25:00 PM PDT 24 552618824 ps
T855 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3974515315 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:49 PM PDT 24 596492897 ps
T856 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3382125602 Aug 07 06:24:42 PM PDT 24 Aug 07 06:26:30 PM PDT 24 52683644225 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2047863733 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:54 PM PDT 24 419187793 ps
T858 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3363507921 Aug 07 06:24:43 PM PDT 24 Aug 07 06:24:44 PM PDT 24 288879085 ps
T859 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1480804951 Aug 07 06:25:03 PM PDT 24 Aug 07 06:25:04 PM PDT 24 463914179 ps
T860 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.806999542 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:53 PM PDT 24 628015377 ps
T861 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2449583101 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 536120662 ps
T862 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3158723482 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:57 PM PDT 24 384494893 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.113201509 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:46 PM PDT 24 486479421 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.401874075 Aug 07 06:24:47 PM PDT 24 Aug 07 06:25:00 PM PDT 24 4166463392 ps
T865 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4173496703 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:53 PM PDT 24 4548403654 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3731538293 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:58 PM PDT 24 674946202 ps
T867 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2256446398 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:58 PM PDT 24 599971500 ps
T868 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.536671175 Aug 07 06:24:39 PM PDT 24 Aug 07 06:24:50 PM PDT 24 4023680986 ps
T869 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1496582093 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:58 PM PDT 24 8664137789 ps
T870 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2082102024 Aug 07 06:24:56 PM PDT 24 Aug 07 06:25:17 PM PDT 24 7875174985 ps
T871 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.871452931 Aug 07 06:24:38 PM PDT 24 Aug 07 06:24:39 PM PDT 24 352072944 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1618258791 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:56 PM PDT 24 462980307 ps
T873 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2636789479 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:57 PM PDT 24 362578427 ps
T874 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3178764963 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:50 PM PDT 24 379897105 ps
T875 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3602399314 Aug 07 06:24:41 PM PDT 24 Aug 07 06:24:43 PM PDT 24 643823821 ps
T876 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3651329146 Aug 07 06:24:57 PM PDT 24 Aug 07 06:24:58 PM PDT 24 344576027 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.151518610 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:52 PM PDT 24 904886032 ps
T878 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1609150608 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:57 PM PDT 24 365260779 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1121676405 Aug 07 06:24:36 PM PDT 24 Aug 07 06:24:40 PM PDT 24 1438716703 ps
T880 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2387639456 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:50 PM PDT 24 330102976 ps
T881 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1991694164 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:54 PM PDT 24 477208509 ps
T882 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3636186318 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:56 PM PDT 24 428772201 ps
T883 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.538414844 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:54 PM PDT 24 525597681 ps
T884 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1799643961 Aug 07 06:24:45 PM PDT 24 Aug 07 06:24:46 PM PDT 24 470205508 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3284148068 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:54 PM PDT 24 508347900 ps
T886 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3698084300 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:58 PM PDT 24 431048387 ps
T887 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4273216358 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:56 PM PDT 24 333960777 ps
T888 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2775809898 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:53 PM PDT 24 614137118 ps
T889 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1215528445 Aug 07 06:24:52 PM PDT 24 Aug 07 06:24:53 PM PDT 24 399703721 ps
T890 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3111738992 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:52 PM PDT 24 344828862 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3799137032 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:50 PM PDT 24 4763195184 ps
T892 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2727571733 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:46 PM PDT 24 874161843 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2092731917 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:46 PM PDT 24 1314467111 ps
T894 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3210359289 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:55 PM PDT 24 632396560 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4254876207 Aug 07 06:24:48 PM PDT 24 Aug 07 06:24:49 PM PDT 24 486136312 ps
T896 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3477908405 Aug 07 06:24:46 PM PDT 24 Aug 07 06:24:49 PM PDT 24 434197957 ps
T897 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2847374591 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:57 PM PDT 24 4491232980 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2726284346 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:45 PM PDT 24 329189503 ps
T899 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1438440371 Aug 07 06:24:51 PM PDT 24 Aug 07 06:24:57 PM PDT 24 524227697 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1435840043 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:59 PM PDT 24 4481799500 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.192073027 Aug 07 06:24:53 PM PDT 24 Aug 07 06:25:01 PM PDT 24 9184583630 ps
T902 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.28782923 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:55 PM PDT 24 417441378 ps
T903 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3113320694 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:54 PM PDT 24 429838214 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3221986860 Aug 07 06:24:44 PM PDT 24 Aug 07 06:24:46 PM PDT 24 364768014 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1762261459 Aug 07 06:24:38 PM PDT 24 Aug 07 06:25:35 PM PDT 24 26206702532 ps
T906 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4133244649 Aug 07 06:24:55 PM PDT 24 Aug 07 06:24:56 PM PDT 24 604616270 ps
T907 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2754086638 Aug 07 06:24:56 PM PDT 24 Aug 07 06:24:58 PM PDT 24 539154615 ps
T908 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1727242426 Aug 07 06:24:39 PM PDT 24 Aug 07 06:25:55 PM PDT 24 29300002169 ps
T909 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1874122507 Aug 07 06:24:58 PM PDT 24 Aug 07 06:24:59 PM PDT 24 517256984 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4262668768 Aug 07 06:24:54 PM PDT 24 Aug 07 06:24:57 PM PDT 24 2583246584 ps
T911 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1088632315 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:55 PM PDT 24 371398268 ps
T912 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2597076114 Aug 07 06:24:50 PM PDT 24 Aug 07 06:24:52 PM PDT 24 489798255 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1967837677 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:51 PM PDT 24 4657815477 ps
T914 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.14886206 Aug 07 06:24:47 PM PDT 24 Aug 07 06:24:51 PM PDT 24 5304392520 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2750249438 Aug 07 06:24:43 PM PDT 24 Aug 07 06:24:44 PM PDT 24 492162789 ps
T916 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.698353121 Aug 07 06:24:49 PM PDT 24 Aug 07 06:24:50 PM PDT 24 360461680 ps
T917 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2384647275 Aug 07 06:24:53 PM PDT 24 Aug 07 06:24:56 PM PDT 24 635078968 ps
T918 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3177184389 Aug 07 06:24:43 PM PDT 24 Aug 07 06:24:46 PM PDT 24 753996304 ps

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1893144948
Short name T7
Test name
Test status
Simulation time 340124473413 ps
CPU time 834.31 seconds
Started Aug 07 05:24:09 PM PDT 24
Finished Aug 07 05:38:03 PM PDT 24
Peak memory 201356 kb
Host smart-a8a986e5-da94-4179-a7b4-729199e35f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893144948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1893144948
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3550642194
Short name T66
Test name
Test status
Simulation time 108171399412 ps
CPU time 565.26 seconds
Started Aug 07 05:17:56 PM PDT 24
Finished Aug 07 05:27:21 PM PDT 24
Peak memory 201780 kb
Host smart-9877d069-a313-4ab9-9945-dc4c47f3ce97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550642194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3550642194
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2439838850
Short name T70
Test name
Test status
Simulation time 623252447938 ps
CPU time 1554.5 seconds
Started Aug 07 05:20:33 PM PDT 24
Finished Aug 07 05:46:28 PM PDT 24
Peak memory 210088 kb
Host smart-0f9d45d1-dc7d-47c9-8a42-9296a9d0fe65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439838850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2439838850
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2168318206
Short name T51
Test name
Test status
Simulation time 535113317808 ps
CPU time 262.17 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:17:39 PM PDT 24
Peak memory 201404 kb
Host smart-5fe65b45-0d28-4c3a-8547-9b797dcf4848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168318206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2168318206
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2122072426
Short name T12
Test name
Test status
Simulation time 21102330443 ps
CPU time 75.81 seconds
Started Aug 07 05:22:18 PM PDT 24
Finished Aug 07 05:23:34 PM PDT 24
Peak memory 210160 kb
Host smart-a8f12ff5-42af-4dfc-9f0a-b76851475968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122072426 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2122072426
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1559111821
Short name T170
Test name
Test status
Simulation time 783361629230 ps
CPU time 1730.51 seconds
Started Aug 07 05:22:48 PM PDT 24
Finished Aug 07 05:51:39 PM PDT 24
Peak memory 201480 kb
Host smart-1b37886e-3fa9-428a-99df-4408c47cd3d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559111821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1559111821
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.935667075
Short name T245
Test name
Test status
Simulation time 554456542260 ps
CPU time 237.93 seconds
Started Aug 07 05:24:35 PM PDT 24
Finished Aug 07 05:28:33 PM PDT 24
Peak memory 201424 kb
Host smart-247200d5-e4ec-49d6-9e06-53277a988801
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935667075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.935667075
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1657209991
Short name T67
Test name
Test status
Simulation time 438260723412 ps
CPU time 380.05 seconds
Started Aug 07 05:19:52 PM PDT 24
Finished Aug 07 05:26:13 PM PDT 24
Peak memory 209964 kb
Host smart-d187727e-f149-445d-861c-7bc6fd03b537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657209991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1657209991
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3576649595
Short name T3
Test name
Test status
Simulation time 489693281945 ps
CPU time 257.89 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:17:19 PM PDT 24
Peak memory 201392 kb
Host smart-e76fe504-2b7b-40d1-8d9a-9ad9f61422b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576649595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3576649595
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1836337043
Short name T64
Test name
Test status
Simulation time 585996254718 ps
CPU time 220.2 seconds
Started Aug 07 05:12:50 PM PDT 24
Finished Aug 07 05:16:30 PM PDT 24
Peak memory 201352 kb
Host smart-4780f182-3fb5-4761-8b0b-1a53dbff4128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836337043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1836337043
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2040782098
Short name T85
Test name
Test status
Simulation time 2656337208 ps
CPU time 2.7 seconds
Started Aug 07 06:24:32 PM PDT 24
Finished Aug 07 06:24:35 PM PDT 24
Peak memory 217708 kb
Host smart-170f17b6-a490-4826-b6d0-10d70f6cfcf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040782098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2040782098
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4196526039
Short name T240
Test name
Test status
Simulation time 498458398220 ps
CPU time 1009.31 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:29:44 PM PDT 24
Peak memory 201352 kb
Host smart-232ee03d-ddc0-44cc-bff0-69940176fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196526039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4196526039
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2745872000
Short name T163
Test name
Test status
Simulation time 542257294711 ps
CPU time 382.34 seconds
Started Aug 07 05:21:57 PM PDT 24
Finished Aug 07 05:28:19 PM PDT 24
Peak memory 201480 kb
Host smart-ce87aee4-f02c-4667-85ff-4ab082821d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745872000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2745872000
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4135662682
Short name T88
Test name
Test status
Simulation time 7809048667 ps
CPU time 17.69 seconds
Started Aug 07 05:13:04 PM PDT 24
Finished Aug 07 05:13:22 PM PDT 24
Peak memory 217152 kb
Host smart-1918e957-aec0-4f79-8a9b-225387f5fe9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135662682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4135662682
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2649519621
Short name T26
Test name
Test status
Simulation time 404964740393 ps
CPU time 456.57 seconds
Started Aug 07 05:19:28 PM PDT 24
Finished Aug 07 05:27:05 PM PDT 24
Peak memory 201416 kb
Host smart-72a0fdec-bc3b-4463-8105-e46bf272e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649519621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2649519621
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.892637080
Short name T65
Test name
Test status
Simulation time 355525759284 ps
CPU time 811.52 seconds
Started Aug 07 05:19:27 PM PDT 24
Finished Aug 07 05:32:59 PM PDT 24
Peak memory 201384 kb
Host smart-7c864a27-ae08-4054-944a-803372c6f6f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892637080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.892637080
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1013106647
Short name T154
Test name
Test status
Simulation time 643620854264 ps
CPU time 250.81 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:17:17 PM PDT 24
Peak memory 201460 kb
Host smart-906ac412-d11f-426b-8dcd-479d78192c9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013106647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1013106647
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1545619074
Short name T80
Test name
Test status
Simulation time 524728815156 ps
CPU time 831.8 seconds
Started Aug 07 05:14:38 PM PDT 24
Finished Aug 07 05:28:30 PM PDT 24
Peak memory 201384 kb
Host smart-2dd01a49-7d77-453b-9b2e-fd6cf7ea1706
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545619074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1545619074
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.968234677
Short name T139
Test name
Test status
Simulation time 34551871875 ps
CPU time 30.58 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:25:19 PM PDT 24
Peak memory 201548 kb
Host smart-fffbe975-1bd2-4c74-aab6-4c71d4319b89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968234677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.968234677
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.651148903
Short name T185
Test name
Test status
Simulation time 781218415539 ps
CPU time 1230.17 seconds
Started Aug 07 05:18:46 PM PDT 24
Finished Aug 07 05:39:16 PM PDT 24
Peak memory 201768 kb
Host smart-8b8e8856-6bc4-46ab-8eb2-fbf863d84686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651148903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
651148903
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2816095710
Short name T270
Test name
Test status
Simulation time 165261691272 ps
CPU time 195.28 seconds
Started Aug 07 05:14:50 PM PDT 24
Finished Aug 07 05:18:06 PM PDT 24
Peak memory 201472 kb
Host smart-a2fdb302-09be-4e3a-8dea-a4c76a128d75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816095710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2816095710
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.670644348
Short name T167
Test name
Test status
Simulation time 392636190923 ps
CPU time 815.77 seconds
Started Aug 07 05:17:00 PM PDT 24
Finished Aug 07 05:30:36 PM PDT 24
Peak memory 201392 kb
Host smart-f93294e1-ae89-469e-9338-aac5b5de7b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670644348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.670644348
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.22798835
Short name T256
Test name
Test status
Simulation time 502762400824 ps
CPU time 956.82 seconds
Started Aug 07 05:20:08 PM PDT 24
Finished Aug 07 05:36:05 PM PDT 24
Peak memory 201404 kb
Host smart-6a188869-118b-41f3-bc82-03e3b912d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22798835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.22798835
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1123788373
Short name T236
Test name
Test status
Simulation time 371167547639 ps
CPU time 213.52 seconds
Started Aug 07 05:16:15 PM PDT 24
Finished Aug 07 05:19:49 PM PDT 24
Peak memory 201368 kb
Host smart-e05ceb11-ac30-4667-8842-143d7b30cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123788373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1123788373
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1120106072
Short name T2
Test name
Test status
Simulation time 338791943436 ps
CPU time 124.69 seconds
Started Aug 07 05:24:08 PM PDT 24
Finished Aug 07 05:26:13 PM PDT 24
Peak memory 201372 kb
Host smart-14234a3c-d039-4b79-b88e-138b4e2d78ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120106072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1120106072
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3005832442
Short name T14
Test name
Test status
Simulation time 280921075987 ps
CPU time 276.33 seconds
Started Aug 07 05:22:02 PM PDT 24
Finished Aug 07 05:26:38 PM PDT 24
Peak memory 210168 kb
Host smart-7578cddd-01aa-43bc-a9b9-f30217e86d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005832442 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3005832442
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3823886859
Short name T279
Test name
Test status
Simulation time 572772891494 ps
CPU time 1267.5 seconds
Started Aug 07 05:19:12 PM PDT 24
Finished Aug 07 05:40:20 PM PDT 24
Peak memory 201468 kb
Host smart-5174d184-a966-4112-af48-31ed95d0e95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823886859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3823886859
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.308089659
Short name T174
Test name
Test status
Simulation time 529422716205 ps
CPU time 1136.63 seconds
Started Aug 07 05:13:00 PM PDT 24
Finished Aug 07 05:31:57 PM PDT 24
Peak memory 201376 kb
Host smart-a2f76d34-2a87-4333-9eca-c01a8933cf56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308089659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.308089659
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4015437680
Short name T57
Test name
Test status
Simulation time 426310568 ps
CPU time 0.67 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:13:01 PM PDT 24
Peak memory 201208 kb
Host smart-ec37b181-2f04-473d-b42f-6384d724bc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015437680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4015437680
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1001758365
Short name T259
Test name
Test status
Simulation time 666741063833 ps
CPU time 1406.39 seconds
Started Aug 07 05:24:04 PM PDT 24
Finished Aug 07 05:47:30 PM PDT 24
Peak memory 201308 kb
Host smart-957fe86b-25de-414f-9106-696e61a7ccd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001758365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1001758365
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2873099496
Short name T11
Test name
Test status
Simulation time 46161360855 ps
CPU time 116.83 seconds
Started Aug 07 05:15:28 PM PDT 24
Finished Aug 07 05:17:25 PM PDT 24
Peak memory 210136 kb
Host smart-c375ec1c-4ddd-4ec9-a00c-3cb53ca27ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873099496 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2873099496
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.209322842
Short name T100
Test name
Test status
Simulation time 7682998284 ps
CPU time 6.24 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:25:02 PM PDT 24
Peak memory 201616 kb
Host smart-02379596-5fce-401f-83d7-8bcd4c867f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209322842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.209322842
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1623375999
Short name T231
Test name
Test status
Simulation time 518594374809 ps
CPU time 178.4 seconds
Started Aug 07 05:23:33 PM PDT 24
Finished Aug 07 05:26:31 PM PDT 24
Peak memory 201396 kb
Host smart-246a9f1a-992d-4415-bb55-69bad5fe569d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623375999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1623375999
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.438342230
Short name T197
Test name
Test status
Simulation time 330643833016 ps
CPU time 184.15 seconds
Started Aug 07 05:13:24 PM PDT 24
Finished Aug 07 05:16:28 PM PDT 24
Peak memory 201396 kb
Host smart-0c1449a7-8070-40bf-9f9c-6f0dc5cbfa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438342230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.438342230
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3637776214
Short name T178
Test name
Test status
Simulation time 491861808007 ps
CPU time 306.03 seconds
Started Aug 07 05:15:38 PM PDT 24
Finished Aug 07 05:20:45 PM PDT 24
Peak memory 201368 kb
Host smart-1e6f8751-c3e0-4319-879a-689a6a124448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637776214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3637776214
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2152849080
Short name T234
Test name
Test status
Simulation time 375542964824 ps
CPU time 782.28 seconds
Started Aug 07 05:19:23 PM PDT 24
Finished Aug 07 05:32:26 PM PDT 24
Peak memory 201396 kb
Host smart-65e5ae3f-98fe-43b1-9a55-0d7745c81545
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152849080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2152849080
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.902283103
Short name T78
Test name
Test status
Simulation time 2708901872 ps
CPU time 3.33 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:40 PM PDT 24
Peak memory 201440 kb
Host smart-f161a963-63c4-47b0-8981-35090aa2a5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902283103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.902283103
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3552915180
Short name T242
Test name
Test status
Simulation time 338162138140 ps
CPU time 125.87 seconds
Started Aug 07 05:21:27 PM PDT 24
Finished Aug 07 05:23:33 PM PDT 24
Peak memory 201360 kb
Host smart-8b93fb2e-699a-4bb3-9ad9-d816035cfd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552915180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3552915180
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3123169040
Short name T63
Test name
Test status
Simulation time 330771480386 ps
CPU time 193.5 seconds
Started Aug 07 05:18:27 PM PDT 24
Finished Aug 07 05:21:41 PM PDT 24
Peak memory 201416 kb
Host smart-a0d80b68-4f92-4622-af16-7701b8dfda8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123169040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3123169040
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1795860889
Short name T308
Test name
Test status
Simulation time 543768859947 ps
CPU time 614.59 seconds
Started Aug 07 05:15:40 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 201460 kb
Host smart-05949fa7-579b-4af3-b836-d1c3a53f460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795860889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1795860889
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.737092277
Short name T151
Test name
Test status
Simulation time 489803665018 ps
CPU time 273.86 seconds
Started Aug 07 05:17:05 PM PDT 24
Finished Aug 07 05:21:39 PM PDT 24
Peak memory 201304 kb
Host smart-d67ea1e5-b1b5-4adf-af9a-387db6e263ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737092277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.737092277
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3701412155
Short name T168
Test name
Test status
Simulation time 374980917937 ps
CPU time 920.43 seconds
Started Aug 07 05:21:40 PM PDT 24
Finished Aug 07 05:37:01 PM PDT 24
Peak memory 201428 kb
Host smart-a220fec0-6f8a-4539-b592-3e80a62d5840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701412155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3701412155
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.320933270
Short name T318
Test name
Test status
Simulation time 323395041104 ps
CPU time 720.96 seconds
Started Aug 07 05:14:40 PM PDT 24
Finished Aug 07 05:26:41 PM PDT 24
Peak memory 201388 kb
Host smart-2c20db97-7ba2-424e-8ef0-73620695dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320933270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.320933270
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3134895506
Short name T30
Test name
Test status
Simulation time 61841793726 ps
CPU time 147.64 seconds
Started Aug 07 05:15:48 PM PDT 24
Finished Aug 07 05:18:15 PM PDT 24
Peak memory 210080 kb
Host smart-3df89f79-37f6-4221-be5c-26f9f06a0333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134895506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3134895506
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2941132467
Short name T269
Test name
Test status
Simulation time 458147736557 ps
CPU time 747.5 seconds
Started Aug 07 05:13:41 PM PDT 24
Finished Aug 07 05:26:09 PM PDT 24
Peak memory 209972 kb
Host smart-e3150f04-653d-4c4f-a929-f848ae30faa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941132467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2941132467
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3155156168
Short name T287
Test name
Test status
Simulation time 487479693012 ps
CPU time 1126.99 seconds
Started Aug 07 05:12:53 PM PDT 24
Finished Aug 07 05:31:40 PM PDT 24
Peak memory 201404 kb
Host smart-20aa67f2-cc5f-4e8c-98ab-c2d95c79b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155156168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3155156168
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.755787118
Short name T5
Test name
Test status
Simulation time 198467236693 ps
CPU time 438.77 seconds
Started Aug 07 05:14:40 PM PDT 24
Finished Aug 07 05:21:59 PM PDT 24
Peak memory 201400 kb
Host smart-0ceeb210-a986-420d-980d-87413e6050cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755787118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.755787118
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1046471785
Short name T266
Test name
Test status
Simulation time 502939075545 ps
CPU time 558.02 seconds
Started Aug 07 05:14:51 PM PDT 24
Finished Aug 07 05:24:09 PM PDT 24
Peak memory 201392 kb
Host smart-8a39063c-c131-437b-9324-fcaa92b49155
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046471785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1046471785
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.683928965
Short name T339
Test name
Test status
Simulation time 387534081614 ps
CPU time 334.8 seconds
Started Aug 07 05:18:47 PM PDT 24
Finished Aug 07 05:24:22 PM PDT 24
Peak memory 217656 kb
Host smart-29b3acb8-e7a6-4308-9ede-1522324db660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683928965 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.683928965
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3002136280
Short name T257
Test name
Test status
Simulation time 486908466967 ps
CPU time 1024.94 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:30:11 PM PDT 24
Peak memory 201452 kb
Host smart-5108a07c-f1b3-4313-ab9f-3437c213c0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002136280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3002136280
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3694661692
Short name T300
Test name
Test status
Simulation time 495354365001 ps
CPU time 303.09 seconds
Started Aug 07 05:14:16 PM PDT 24
Finished Aug 07 05:19:19 PM PDT 24
Peak memory 201396 kb
Host smart-2bee0a3d-05c8-4269-878f-81269a865bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694661692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3694661692
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3005170158
Short name T261
Test name
Test status
Simulation time 347264499694 ps
CPU time 801.97 seconds
Started Aug 07 05:17:34 PM PDT 24
Finished Aug 07 05:30:56 PM PDT 24
Peak memory 201416 kb
Host smart-547cc823-6f58-4c7b-af22-857b64fa8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005170158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3005170158
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3656928573
Short name T295
Test name
Test status
Simulation time 552242952952 ps
CPU time 263.45 seconds
Started Aug 07 05:22:15 PM PDT 24
Finished Aug 07 05:26:39 PM PDT 24
Peak memory 201396 kb
Host smart-4c5182c0-77f0-4316-a340-cdaffe468d42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656928573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3656928573
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.586368227
Short name T196
Test name
Test status
Simulation time 534829544222 ps
CPU time 73.34 seconds
Started Aug 07 05:13:35 PM PDT 24
Finished Aug 07 05:14:49 PM PDT 24
Peak memory 201360 kb
Host smart-bef11833-20bc-4444-b5cd-534d72da8445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586368227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.586368227
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2110928070
Short name T93
Test name
Test status
Simulation time 486482109 ps
CPU time 2.84 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:59 PM PDT 24
Peak memory 218208 kb
Host smart-9402778e-61cf-4932-85e3-f45314c8c531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110928070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2110928070
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.734273217
Short name T317
Test name
Test status
Simulation time 162869874515 ps
CPU time 350.23 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:18:45 PM PDT 24
Peak memory 201380 kb
Host smart-13124276-e4ba-433d-a18c-125829e68fab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734273217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.734273217
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.849505128
Short name T214
Test name
Test status
Simulation time 497870363881 ps
CPU time 95.1 seconds
Started Aug 07 05:12:54 PM PDT 24
Finished Aug 07 05:14:29 PM PDT 24
Peak memory 201440 kb
Host smart-8f26b99b-01cf-4c1d-8f57-be4684f843de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849505128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.849505128
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3413946796
Short name T294
Test name
Test status
Simulation time 328252133107 ps
CPU time 529.94 seconds
Started Aug 07 05:14:16 PM PDT 24
Finished Aug 07 05:23:06 PM PDT 24
Peak memory 201372 kb
Host smart-c05d42b3-890f-4e61-8a65-e82b7f450f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413946796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3413946796
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2064111354
Short name T176
Test name
Test status
Simulation time 338911615451 ps
CPU time 399.72 seconds
Started Aug 07 05:14:33 PM PDT 24
Finished Aug 07 05:21:13 PM PDT 24
Peak memory 201400 kb
Host smart-5f74a107-1cb8-4e53-a866-f642c07949b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064111354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2064111354
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4260117164
Short name T156
Test name
Test status
Simulation time 489813157097 ps
CPU time 306.3 seconds
Started Aug 07 05:13:05 PM PDT 24
Finished Aug 07 05:18:12 PM PDT 24
Peak memory 201460 kb
Host smart-142ac3ff-88f6-4c6b-a97d-49b61a9f664d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260117164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4260117164
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1744758935
Short name T260
Test name
Test status
Simulation time 489210661159 ps
CPU time 981.87 seconds
Started Aug 07 05:23:17 PM PDT 24
Finished Aug 07 05:39:39 PM PDT 24
Peak memory 201452 kb
Host smart-5118ab97-8645-47ec-9070-17ce91a9c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744758935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1744758935
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2702372303
Short name T120
Test name
Test status
Simulation time 81865201219 ps
CPU time 161.42 seconds
Started Aug 07 05:23:54 PM PDT 24
Finished Aug 07 05:26:35 PM PDT 24
Peak memory 209748 kb
Host smart-d587fc5d-b50f-4743-8c3d-1a6fd8aaabd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702372303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2702372303
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3248392414
Short name T183
Test name
Test status
Simulation time 492466657859 ps
CPU time 594.32 seconds
Started Aug 07 05:24:54 PM PDT 24
Finished Aug 07 05:34:49 PM PDT 24
Peak memory 201416 kb
Host smart-bf2d5668-2747-465b-8a5f-7eacf18028a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248392414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3248392414
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4019464639
Short name T299
Test name
Test status
Simulation time 165525037029 ps
CPU time 391.81 seconds
Started Aug 07 05:19:23 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 201412 kb
Host smart-617fe9d2-9d74-493b-ade7-d7c8fea67b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019464639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4019464639
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2365066738
Short name T251
Test name
Test status
Simulation time 485767808333 ps
CPU time 1178.43 seconds
Started Aug 07 05:20:53 PM PDT 24
Finished Aug 07 05:40:32 PM PDT 24
Peak memory 201324 kb
Host smart-5f37b6fd-1992-4ba8-b7ce-3e52cf3e9831
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365066738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2365066738
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1381044621
Short name T314
Test name
Test status
Simulation time 257514807185 ps
CPU time 272.2 seconds
Started Aug 07 05:21:25 PM PDT 24
Finished Aug 07 05:25:58 PM PDT 24
Peak memory 209936 kb
Host smart-c359434b-d37e-46e2-ac8c-117690ec7901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381044621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1381044621
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3881769869
Short name T283
Test name
Test status
Simulation time 160008054173 ps
CPU time 342 seconds
Started Aug 07 05:13:14 PM PDT 24
Finished Aug 07 05:18:56 PM PDT 24
Peak memory 201428 kb
Host smart-b5a3c032-913e-4f66-b0d6-263da55f261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881769869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3881769869
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3445260299
Short name T105
Test name
Test status
Simulation time 165905675792 ps
CPU time 98.39 seconds
Started Aug 07 05:23:59 PM PDT 24
Finished Aug 07 05:25:38 PM PDT 24
Peak memory 201412 kb
Host smart-f75616c5-e09b-46b2-86cf-9920bcbdfbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445260299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3445260299
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1573621130
Short name T75
Test name
Test status
Simulation time 716456190070 ps
CPU time 1022.65 seconds
Started Aug 07 05:15:54 PM PDT 24
Finished Aug 07 05:32:57 PM PDT 24
Peak memory 209916 kb
Host smart-7819385c-502c-4b85-8c5e-d19a4785ec5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573621130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1573621130
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3210474244
Short name T112
Test name
Test status
Simulation time 182627199185 ps
CPU time 104.77 seconds
Started Aug 07 05:16:00 PM PDT 24
Finished Aug 07 05:17:45 PM PDT 24
Peak memory 201372 kb
Host smart-2206bc9f-cf4c-416b-a0a2-4dd6bfb343c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210474244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3210474244
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1829187098
Short name T272
Test name
Test status
Simulation time 507521198334 ps
CPU time 400.35 seconds
Started Aug 07 05:19:47 PM PDT 24
Finished Aug 07 05:26:27 PM PDT 24
Peak memory 201352 kb
Host smart-5b6aec0e-ee19-458f-9607-5515cc519712
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829187098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1829187098
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2878876107
Short name T73
Test name
Test status
Simulation time 89288295955 ps
CPU time 316.71 seconds
Started Aug 07 05:22:10 PM PDT 24
Finished Aug 07 05:27:26 PM PDT 24
Peak memory 201868 kb
Host smart-7767b4d9-dc10-46b6-8761-ba09ac72a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878876107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2878876107
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2987328882
Short name T286
Test name
Test status
Simulation time 495646834068 ps
CPU time 269.6 seconds
Started Aug 07 05:22:07 PM PDT 24
Finished Aug 07 05:26:36 PM PDT 24
Peak memory 201324 kb
Host smart-9ecc9c46-85ae-452b-a74c-40418fbaf253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987328882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2987328882
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2342894919
Short name T165
Test name
Test status
Simulation time 331490713157 ps
CPU time 394.04 seconds
Started Aug 07 05:24:53 PM PDT 24
Finished Aug 07 05:31:28 PM PDT 24
Peak memory 201408 kb
Host smart-7b367a46-204c-419d-9d05-064db866ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342894919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2342894919
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2818308036
Short name T130
Test name
Test status
Simulation time 619010399904 ps
CPU time 368.52 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:19:25 PM PDT 24
Peak memory 211736 kb
Host smart-26ce1376-46fc-4af4-9e0f-28339118af4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818308036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2818308036
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4160510730
Short name T4
Test name
Test status
Simulation time 362038270422 ps
CPU time 799.17 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:26:43 PM PDT 24
Peak memory 201324 kb
Host smart-f9a38c87-cbdb-4d85-a18d-252cf8f0eb8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160510730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4160510730
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.675719620
Short name T97
Test name
Test status
Simulation time 8233760946 ps
CPU time 21.65 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:25:06 PM PDT 24
Peak memory 201712 kb
Host smart-d8954201-3abb-45ab-b7f8-66cdd82f54e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675719620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.675719620
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.737101601
Short name T267
Test name
Test status
Simulation time 363946426295 ps
CPU time 210.59 seconds
Started Aug 07 05:13:56 PM PDT 24
Finished Aug 07 05:17:27 PM PDT 24
Peak memory 201440 kb
Host smart-807b7ba3-d545-4f62-8011-87175b392f39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737101601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.737101601
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3985937711
Short name T730
Test name
Test status
Simulation time 517526524053 ps
CPU time 1199.14 seconds
Started Aug 07 05:14:21 PM PDT 24
Finished Aug 07 05:34:21 PM PDT 24
Peak memory 201448 kb
Host smart-2e48d79f-42b3-44fd-ae2d-83f25e3891e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985937711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3985937711
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3813680412
Short name T297
Test name
Test status
Simulation time 576702395535 ps
CPU time 1396.57 seconds
Started Aug 07 05:15:24 PM PDT 24
Finished Aug 07 05:38:41 PM PDT 24
Peak memory 201368 kb
Host smart-d7e05f1a-d88c-4b41-87b8-822a8b6b8a8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813680412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3813680412
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1785219843
Short name T227
Test name
Test status
Simulation time 111244093761 ps
CPU time 555.52 seconds
Started Aug 07 05:16:02 PM PDT 24
Finished Aug 07 05:25:18 PM PDT 24
Peak memory 201836 kb
Host smart-fcdce452-f6c0-4d8a-b368-92db8d10df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785219843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1785219843
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3756165711
Short name T268
Test name
Test status
Simulation time 390842967494 ps
CPU time 854.75 seconds
Started Aug 07 05:16:16 PM PDT 24
Finished Aug 07 05:30:31 PM PDT 24
Peak memory 201416 kb
Host smart-c110661a-05f7-4c40-b53d-51f2e18c6ed5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756165711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3756165711
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3598382645
Short name T348
Test name
Test status
Simulation time 102185048422 ps
CPU time 361.5 seconds
Started Aug 07 05:16:44 PM PDT 24
Finished Aug 07 05:22:45 PM PDT 24
Peak memory 201792 kb
Host smart-d0acc6e7-5c31-4dba-bd83-038c9116e198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598382645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3598382645
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2162547175
Short name T265
Test name
Test status
Simulation time 578404811534 ps
CPU time 1361.62 seconds
Started Aug 07 05:16:54 PM PDT 24
Finished Aug 07 05:39:36 PM PDT 24
Peak memory 201324 kb
Host smart-8491bfce-72aa-4d6e-9610-0216d470e198
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162547175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2162547175
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2002704943
Short name T333
Test name
Test status
Simulation time 188826572466 ps
CPU time 120.72 seconds
Started Aug 07 05:17:17 PM PDT 24
Finished Aug 07 05:19:18 PM PDT 24
Peak memory 201368 kb
Host smart-0c43c7f5-e0d8-457c-8d0d-d388912f3acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002704943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2002704943
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.716184647
Short name T182
Test name
Test status
Simulation time 684053214139 ps
CPU time 814.16 seconds
Started Aug 07 05:18:17 PM PDT 24
Finished Aug 07 05:31:51 PM PDT 24
Peak memory 201384 kb
Host smart-34c14a23-3fcc-4917-85ef-6a96ec7840fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716184647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
716184647
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.935388963
Short name T341
Test name
Test status
Simulation time 134523047217 ps
CPU time 149.23 seconds
Started Aug 07 05:19:12 PM PDT 24
Finished Aug 07 05:21:41 PM PDT 24
Peak memory 210644 kb
Host smart-6cdbefa6-744f-4c7a-a6ea-01ba5d4d87b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935388963 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.935388963
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.789039872
Short name T224
Test name
Test status
Simulation time 108481931172 ps
CPU time 569.96 seconds
Started Aug 07 05:13:08 PM PDT 24
Finished Aug 07 05:22:38 PM PDT 24
Peak memory 201780 kb
Host smart-68b67a55-052e-4d33-959d-a9aaf3d503d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789039872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.789039872
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1409037896
Short name T293
Test name
Test status
Simulation time 195136500253 ps
CPU time 140.15 seconds
Started Aug 07 05:20:28 PM PDT 24
Finished Aug 07 05:22:48 PM PDT 24
Peak memory 210092 kb
Host smart-efee5269-5542-4afb-bc45-b5ff7d5f4c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409037896 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1409037896
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3523924977
Short name T123
Test name
Test status
Simulation time 91523795025 ps
CPU time 301.55 seconds
Started Aug 07 05:22:19 PM PDT 24
Finished Aug 07 05:27:21 PM PDT 24
Peak memory 201760 kb
Host smart-571bee65-70a6-4ab6-83f2-b7503dbac06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523924977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3523924977
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1610866976
Short name T158
Test name
Test status
Simulation time 489184619049 ps
CPU time 288.95 seconds
Started Aug 07 05:22:16 PM PDT 24
Finished Aug 07 05:27:05 PM PDT 24
Peak memory 201424 kb
Host smart-fd58ccf3-93a8-4d92-9771-aa741e6723ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610866976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1610866976
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.692736164
Short name T302
Test name
Test status
Simulation time 190571500078 ps
CPU time 331.18 seconds
Started Aug 07 05:24:30 PM PDT 24
Finished Aug 07 05:30:02 PM PDT 24
Peak memory 201392 kb
Host smart-d80428d5-2150-46e3-9a38-d35c33839f6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692736164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.692736164
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.841568699
Short name T233
Test name
Test status
Simulation time 158360250812 ps
CPU time 325.04 seconds
Started Aug 07 05:13:44 PM PDT 24
Finished Aug 07 05:19:09 PM PDT 24
Peak memory 201340 kb
Host smart-4d5ce68f-a2f1-4e59-9665-889ae797b080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841568699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.841568699
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1121676405
Short name T879
Test name
Test status
Simulation time 1438716703 ps
CPU time 3.99 seconds
Started Aug 07 06:24:36 PM PDT 24
Finished Aug 07 06:24:40 PM PDT 24
Peak memory 201576 kb
Host smart-68eaacf4-a1e3-43b3-abe9-8e9ead013730
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121676405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1121676405
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.586122448
Short name T148
Test name
Test status
Simulation time 1025842685 ps
CPU time 0.89 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 201372 kb
Host smart-e3d4b8a4-fbe8-4c44-9369-6599272d59d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586122448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.586122448
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2726284346
Short name T898
Test name
Test status
Simulation time 329189503 ps
CPU time 1.45 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:45 PM PDT 24
Peak memory 201512 kb
Host smart-f59005fd-99b9-49e8-aa75-036c7cb76daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726284346 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2726284346
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2603732548
Short name T133
Test name
Test status
Simulation time 365004839 ps
CPU time 0.88 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201400 kb
Host smart-dc03612d-c0b0-4a57-afec-b865179f0c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603732548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2603732548
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1118015204
Short name T812
Test name
Test status
Simulation time 513048285 ps
CPU time 1.86 seconds
Started Aug 07 06:24:34 PM PDT 24
Finished Aug 07 06:24:36 PM PDT 24
Peak memory 201360 kb
Host smart-9c8b622e-3802-49eb-9b10-ecaf2acd2099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118015204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1118015204
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3974515315
Short name T855
Test name
Test status
Simulation time 596492897 ps
CPU time 1.86 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201660 kb
Host smart-c7440e9e-076f-4038-b563-626da376a9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974515315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3974515315
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.757359361
Short name T87
Test name
Test status
Simulation time 4096317747 ps
CPU time 6.25 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 201616 kb
Host smart-3486da1d-c8a1-4f6a-9567-bab863d32c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757359361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.757359361
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.38696861
Short name T141
Test name
Test status
Simulation time 603218570 ps
CPU time 1.93 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 201552 kb
Host smart-cc736bf1-4a42-4ed9-8701-38ea398e3741
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasi
ng.38696861
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1100595810
Short name T850
Test name
Test status
Simulation time 25812059102 ps
CPU time 55.74 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:25:43 PM PDT 24
Peak memory 201636 kb
Host smart-f88785fa-ebf6-4885-bd99-3eb620bc6b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100595810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1100595810
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3177184389
Short name T918
Test name
Test status
Simulation time 753996304 ps
CPU time 2.55 seconds
Started Aug 07 06:24:43 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201388 kb
Host smart-1b3f937b-1971-4994-a53e-bc2f1a672254
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177184389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3177184389
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3477908405
Short name T896
Test name
Test status
Simulation time 434197957 ps
CPU time 1.96 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201500 kb
Host smart-2f661de4-b2f6-4218-9ded-e37b98c006ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477908405 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3477908405
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4215016814
Short name T132
Test name
Test status
Simulation time 494509719 ps
CPU time 1.35 seconds
Started Aug 07 06:24:40 PM PDT 24
Finished Aug 07 06:24:41 PM PDT 24
Peak memory 201360 kb
Host smart-7aed86f8-0f97-4a91-bb7e-f98d4297f83d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215016814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4215016814
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.498445265
Short name T815
Test name
Test status
Simulation time 278099735 ps
CPU time 1.24 seconds
Started Aug 07 06:24:42 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 201368 kb
Host smart-97f09f63-3b6f-40f1-a761-2297a3a1460a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498445265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.498445265
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1977887085
Short name T144
Test name
Test status
Simulation time 2718166156 ps
CPU time 3.57 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201440 kb
Host smart-0cd1b218-25cc-4678-aa65-f4ac69d6bb2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977887085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1977887085
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1189015497
Short name T92
Test name
Test status
Simulation time 551710072 ps
CPU time 1.92 seconds
Started Aug 07 06:24:30 PM PDT 24
Finished Aug 07 06:24:32 PM PDT 24
Peak memory 201676 kb
Host smart-bdad124e-735d-407d-87a4-bd72da222115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189015497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1189015497
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1967837677
Short name T913
Test name
Test status
Simulation time 4657815477 ps
CPU time 4.18 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:51 PM PDT 24
Peak memory 201564 kb
Host smart-b4a9a1b6-5fb4-4b5f-8d48-64aee268ce90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967837677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1967837677
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2256446398
Short name T867
Test name
Test status
Simulation time 599971500 ps
CPU time 1.57 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201516 kb
Host smart-66ba4fed-ddad-4e69-a810-bacb3e354870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256446398 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2256446398
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.584908444
Short name T823
Test name
Test status
Simulation time 548819616 ps
CPU time 1.09 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201388 kb
Host smart-a2233afc-8150-4981-b9c6-beeee2e122eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584908444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.584908444
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.748860067
Short name T800
Test name
Test status
Simulation time 473060390 ps
CPU time 1.7 seconds
Started Aug 07 06:24:45 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 201380 kb
Host smart-105b1a71-6660-41d7-bdf6-67b8808645f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748860067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.748860067
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1423715672
Short name T832
Test name
Test status
Simulation time 4810173126 ps
CPU time 12.02 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:25:06 PM PDT 24
Peak memory 201576 kb
Host smart-f9c62bb8-8476-45aa-ac3e-7a913b43095e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423715672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1423715672
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2384647275
Short name T917
Test name
Test status
Simulation time 635078968 ps
CPU time 2.17 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201664 kb
Host smart-8ce351d5-4223-4e90-8c97-f1ecbfb34851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384647275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2384647275
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2019303603
Short name T84
Test name
Test status
Simulation time 4304489445 ps
CPU time 11.38 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:25:04 PM PDT 24
Peak memory 201684 kb
Host smart-c33731cb-73e8-448c-88a9-0f6f361a66f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019303603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2019303603
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2605719622
Short name T854
Test name
Test status
Simulation time 552618824 ps
CPU time 1.91 seconds
Started Aug 07 06:24:58 PM PDT 24
Finished Aug 07 06:25:00 PM PDT 24
Peak memory 201516 kb
Host smart-3055c2be-5cd0-4f9d-9e07-ef662913e5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605719622 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2605719622
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3662681227
Short name T135
Test name
Test status
Simulation time 509058307 ps
CPU time 1.24 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201388 kb
Host smart-e392d586-8eca-432e-ad2a-0a357cbdf116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662681227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3662681227
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1882710053
Short name T804
Test name
Test status
Simulation time 285752096 ps
CPU time 1.32 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201360 kb
Host smart-d7948513-4e99-4f88-9490-eb04ffbcca0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882710053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1882710053
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.400761644
Short name T837
Test name
Test status
Simulation time 4630331292 ps
CPU time 5.39 seconds
Started Aug 07 06:24:37 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 201608 kb
Host smart-48f30dae-7d6a-422a-baad-fd73a48b0699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400761644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.400761644
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2085596089
Short name T839
Test name
Test status
Simulation time 383746279 ps
CPU time 2.13 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201604 kb
Host smart-fba9ca0a-43a5-4965-8c6f-1e54952e22ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085596089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2085596089
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.755005548
Short name T101
Test name
Test status
Simulation time 8041007495 ps
CPU time 12.21 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:25:05 PM PDT 24
Peak memory 201700 kb
Host smart-780ad509-cb9e-44db-a127-d312928ded8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755005548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.755005548
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2695799569
Short name T849
Test name
Test status
Simulation time 466290979 ps
CPU time 1.84 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201496 kb
Host smart-be09dc9d-78dd-4db1-b15f-5db7413cbf97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695799569 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2695799569
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4254876207
Short name T895
Test name
Test status
Simulation time 486136312 ps
CPU time 1.05 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201364 kb
Host smart-fef70e2c-07e1-429b-85d8-df34261faee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254876207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4254876207
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3363507921
Short name T858
Test name
Test status
Simulation time 288879085 ps
CPU time 1.15 seconds
Started Aug 07 06:24:43 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 201340 kb
Host smart-d76b744d-8cde-4518-b2cd-f8b999326377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363507921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3363507921
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.401874075
Short name T864
Test name
Test status
Simulation time 4166463392 ps
CPU time 13.21 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:25:00 PM PDT 24
Peak memory 201564 kb
Host smart-aeebd0ce-79a5-4a23-b309-3cd616061316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401874075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.401874075
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.761536616
Short name T848
Test name
Test status
Simulation time 838995188 ps
CPU time 2.8 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201592 kb
Host smart-0c778861-5993-43b4-b518-49127ce992bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761536616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.761536616
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4005344748
Short name T83
Test name
Test status
Simulation time 4668398474 ps
CPU time 3.43 seconds
Started Aug 07 06:24:45 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201660 kb
Host smart-900f3707-6c30-4c49-9afe-89a0f8ee1930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005344748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4005344748
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3498251913
Short name T96
Test name
Test status
Simulation time 544966274 ps
CPU time 1.31 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201520 kb
Host smart-3ccbad54-5775-4eb4-94e1-e227d22abc17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498251913 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3498251913
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.113201509
Short name T863
Test name
Test status
Simulation time 486479421 ps
CPU time 1.83 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201384 kb
Host smart-4ab7db07-f83e-4e1a-b2b4-ba1ac8be7830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113201509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.113201509
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3221986860
Short name T904
Test name
Test status
Simulation time 364768014 ps
CPU time 1.41 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201328 kb
Host smart-31beab58-3a49-4707-90f6-e75265b08c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221986860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3221986860
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1435840043
Short name T900
Test name
Test status
Simulation time 4481799500 ps
CPU time 5.21 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:59 PM PDT 24
Peak memory 201504 kb
Host smart-bd861cad-8100-42e2-a465-968c5c88939d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435840043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1435840043
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1088632315
Short name T911
Test name
Test status
Simulation time 371398268 ps
CPU time 1.97 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201632 kb
Host smart-59fc5043-3273-44a3-8460-a7cdeb3f2a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088632315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1088632315
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1496582093
Short name T869
Test name
Test status
Simulation time 8664137789 ps
CPU time 4.24 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201632 kb
Host smart-2a045012-07e3-4709-ab95-7e111812ee5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496582093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1496582093
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2167286755
Short name T803
Test name
Test status
Simulation time 463923499 ps
CPU time 1.27 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201504 kb
Host smart-f6b802f3-09c2-46d1-8b35-9b81e655c313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167286755 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2167286755
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2234615206
Short name T136
Test name
Test status
Simulation time 370995858 ps
CPU time 0.95 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 201356 kb
Host smart-fc5efc4d-2358-41d1-b778-2336097dc46d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234615206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2234615206
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2047863733
Short name T857
Test name
Test status
Simulation time 419187793 ps
CPU time 0.78 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201340 kb
Host smart-f146d4aa-1064-414f-8e21-e73da9552489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047863733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2047863733
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2038663924
Short name T842
Test name
Test status
Simulation time 2119379079 ps
CPU time 3.94 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201376 kb
Host smart-e95c2f45-dc5c-4cfa-8ee4-00de4821d4ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038663924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2038663924
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3235483514
Short name T834
Test name
Test status
Simulation time 489656225 ps
CPU time 2.6 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201712 kb
Host smart-92a26686-7484-474a-a708-b0f131ea7a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235483514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3235483514
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.215739868
Short name T844
Test name
Test status
Simulation time 4240223028 ps
CPU time 3.72 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201684 kb
Host smart-294c96ad-7730-4db9-9ef7-bdc00e531b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215739868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.215739868
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1618258791
Short name T872
Test name
Test status
Simulation time 462980307 ps
CPU time 1.95 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201528 kb
Host smart-84eacc14-fe69-4150-8b3b-7a6ab5852e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618258791 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1618258791
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.913017862
Short name T138
Test name
Test status
Simulation time 443036942 ps
CPU time 1.25 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201356 kb
Host smart-ada6aacd-c32e-4a09-a76e-5f030c2f5819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913017862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.913017862
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4242793873
Short name T810
Test name
Test status
Simulation time 478820082 ps
CPU time 0.9 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201352 kb
Host smart-c82a1453-8763-4b4f-abcf-df33bc588409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242793873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4242793873
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2847374591
Short name T897
Test name
Test status
Simulation time 4491232980 ps
CPU time 3.68 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201604 kb
Host smart-0b2bf956-1712-4b19-abd5-b06bf50e318a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847374591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2847374591
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.215476789
Short name T86
Test name
Test status
Simulation time 608374712 ps
CPU time 1.31 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201672 kb
Host smart-ee643dd8-f989-45e3-9191-21493b61cdce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215476789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.215476789
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3280335224
Short name T845
Test name
Test status
Simulation time 4601604325 ps
CPU time 2.69 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201696 kb
Host smart-e383c97d-96b2-4a6f-98a0-c090a8dae3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280335224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3280335224
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1438440371
Short name T899
Test name
Test status
Simulation time 524227697 ps
CPU time 1.18 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 209720 kb
Host smart-53a2240c-8223-492f-8d78-4fc5e19abcc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438440371 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1438440371
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.4133244649
Short name T906
Test name
Test status
Simulation time 604616270 ps
CPU time 1.12 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201332 kb
Host smart-e3d7c475-65bf-4831-a865-f488b6f3ca1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133244649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.4133244649
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1887572198
Short name T809
Test name
Test status
Simulation time 513859956 ps
CPU time 1.85 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201376 kb
Host smart-b33b5d68-8d08-470b-a221-5e544e2f2f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887572198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1887572198
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1432581493
Short name T147
Test name
Test status
Simulation time 2223823611 ps
CPU time 5.27 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201416 kb
Host smart-3809b41c-9e42-465a-92c6-8c3e07192a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432581493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1432581493
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.806999542
Short name T860
Test name
Test status
Simulation time 628015377 ps
CPU time 2.89 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 218000 kb
Host smart-21c2161b-931b-4f22-a8bc-99b659653eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806999542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.806999542
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3380167858
Short name T807
Test name
Test status
Simulation time 4389014624 ps
CPU time 5.16 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201664 kb
Host smart-a7c39c3c-89f0-4753-b7d4-f03cf92a47e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380167858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3380167858
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3683285428
Short name T91
Test name
Test status
Simulation time 338139487 ps
CPU time 1.55 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201496 kb
Host smart-a84bba6f-a228-4507-9254-9e6fba124a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683285428 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3683285428
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.28782923
Short name T902
Test name
Test status
Simulation time 417441378 ps
CPU time 1.65 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201376 kb
Host smart-c784e2f2-9d25-4635-b574-6f0a59028379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28782923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.28782923
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3284148068
Short name T885
Test name
Test status
Simulation time 508347900 ps
CPU time 1.18 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201344 kb
Host smart-ad53e9cd-2bdb-419e-98c7-8d27e5fe520d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284148068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3284148068
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2621900940
Short name T846
Test name
Test status
Simulation time 2584317807 ps
CPU time 2.21 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201440 kb
Host smart-757ed70b-cc21-4c63-be4d-c65db126edb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621900940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2621900940
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3614769083
Short name T797
Test name
Test status
Simulation time 366054394 ps
CPU time 1.86 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201504 kb
Host smart-a9c8f33b-9e7a-44cf-b469-bd82041b9d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614769083 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3614769083
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3996905988
Short name T847
Test name
Test status
Simulation time 444162643 ps
CPU time 0.84 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201376 kb
Host smart-68179af6-b4c4-4000-910c-c9c9565ab30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996905988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3996905988
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4027380678
Short name T817
Test name
Test status
Simulation time 436669170 ps
CPU time 1.13 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201336 kb
Host smart-710318b0-147f-4775-ac8b-d8bf4398b0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027380678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4027380678
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4262668768
Short name T910
Test name
Test status
Simulation time 2583246584 ps
CPU time 2.8 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201432 kb
Host smart-ad2e1f16-5434-44b8-9770-eed11a560628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262668768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4262668768
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3730848693
Short name T852
Test name
Test status
Simulation time 552268010 ps
CPU time 3.32 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 210840 kb
Host smart-c5f843d1-28bf-4981-b568-e26fe2b7a9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730848693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3730848693
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3609719200
Short name T816
Test name
Test status
Simulation time 4596385990 ps
CPU time 10.09 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:25:03 PM PDT 24
Peak memory 201708 kb
Host smart-cdf4cff9-b099-400c-b7d1-78c64e637f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609719200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3609719200
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3210359289
Short name T894
Test name
Test status
Simulation time 632396560 ps
CPU time 1.52 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 209804 kb
Host smart-e876ac62-4265-4b27-9fc1-e4dfead12159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210359289 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3210359289
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2597076114
Short name T912
Test name
Test status
Simulation time 489798255 ps
CPU time 1.52 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201388 kb
Host smart-973f3fc3-340e-4912-98f3-cc759d35db56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597076114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2597076114
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.564478585
Short name T811
Test name
Test status
Simulation time 412633244 ps
CPU time 1.08 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201368 kb
Host smart-07e02548-1386-4cd6-8e41-061be41f5787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564478585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.564478585
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2892419816
Short name T822
Test name
Test status
Simulation time 2732569148 ps
CPU time 2.5 seconds
Started Aug 07 06:24:57 PM PDT 24
Finished Aug 07 06:25:00 PM PDT 24
Peak memory 201404 kb
Host smart-fbeab7f3-838f-4ce9-a355-305b27b08fc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892419816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2892419816
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2162938323
Short name T98
Test name
Test status
Simulation time 375393895 ps
CPU time 2.43 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201672 kb
Host smart-1a3f139e-847c-4004-ab40-ea08a23db9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162938323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2162938323
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2082102024
Short name T870
Test name
Test status
Simulation time 7875174985 ps
CPU time 20.5 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:25:17 PM PDT 24
Peak memory 201652 kb
Host smart-9003f328-e885-45c4-97ef-14b0f0b25f0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082102024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2082102024
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.143752309
Short name T137
Test name
Test status
Simulation time 375804044 ps
CPU time 2.24 seconds
Started Aug 07 06:24:43 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201560 kb
Host smart-a79a30e4-3594-4157-9453-7795fdb91b05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143752309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.143752309
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1727242426
Short name T908
Test name
Test status
Simulation time 29300002169 ps
CPU time 75.63 seconds
Started Aug 07 06:24:39 PM PDT 24
Finished Aug 07 06:25:55 PM PDT 24
Peak memory 201500 kb
Host smart-88b2f11f-df04-44a5-8156-5aeee3c323cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727242426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1727242426
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.354438806
Short name T841
Test name
Test status
Simulation time 613847308 ps
CPU time 1.37 seconds
Started Aug 07 06:24:34 PM PDT 24
Finished Aug 07 06:24:36 PM PDT 24
Peak memory 201412 kb
Host smart-3694fba7-89fe-4311-84c3-61bb3cf93891
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354438806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.354438806
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3084849817
Short name T806
Test name
Test status
Simulation time 690197499 ps
CPU time 1.41 seconds
Started Aug 07 06:24:42 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 209924 kb
Host smart-668d79d0-84c1-44a4-9325-395a1014323b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084849817 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3084849817
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1343791883
Short name T140
Test name
Test status
Simulation time 396847538 ps
CPU time 1.72 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 201392 kb
Host smart-e8045b62-7dda-43dc-b8ab-b0343f55c125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343791883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1343791883
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1072101162
Short name T813
Test name
Test status
Simulation time 554053426 ps
CPU time 0.97 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201372 kb
Host smart-cdb93345-7c04-4ba8-8a4d-e521cf793d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072101162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1072101162
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1567281691
Short name T76
Test name
Test status
Simulation time 5071457971 ps
CPU time 4.27 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201628 kb
Host smart-a9c76782-9b95-4fad-9335-07e0080e6870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567281691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1567281691
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1221138653
Short name T838
Test name
Test status
Simulation time 633273336 ps
CPU time 1.59 seconds
Started Aug 07 06:24:35 PM PDT 24
Finished Aug 07 06:24:36 PM PDT 24
Peak memory 201696 kb
Host smart-8fd63c9c-870d-4f64-a745-ce42ca0a873c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221138653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1221138653
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1356453159
Short name T82
Test name
Test status
Simulation time 9121845314 ps
CPU time 5.31 seconds
Started Aug 07 06:24:38 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 201652 kb
Host smart-dd6416f6-8753-4847-99ea-47061e5b3693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356453159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1356453159
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.345128493
Short name T818
Test name
Test status
Simulation time 426353869 ps
CPU time 1.58 seconds
Started Aug 07 06:24:57 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201372 kb
Host smart-c5b34a49-2dfc-4bba-9ed2-1cf9fd03897d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345128493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.345128493
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3113320694
Short name T903
Test name
Test status
Simulation time 429838214 ps
CPU time 0.87 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201336 kb
Host smart-945b383b-ec52-47da-8a36-96187761f2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113320694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3113320694
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2974525135
Short name T824
Test name
Test status
Simulation time 444289031 ps
CPU time 0.84 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201384 kb
Host smart-21be93cb-6c10-4144-8b80-2916baaa6a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974525135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2974525135
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.877918743
Short name T794
Test name
Test status
Simulation time 414242794 ps
CPU time 1.58 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201384 kb
Host smart-3dbecab6-7769-44c6-ab57-aa6ab57e6c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877918743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.877918743
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3178764963
Short name T874
Test name
Test status
Simulation time 379897105 ps
CPU time 1.61 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201376 kb
Host smart-bf175908-df74-4059-9aae-48c07104ca98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178764963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3178764963
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1609150608
Short name T878
Test name
Test status
Simulation time 365260779 ps
CPU time 1.05 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201384 kb
Host smart-0dc2b26b-ac1b-42c1-9a9b-c4597c67c66c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609150608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1609150608
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.182586489
Short name T795
Test name
Test status
Simulation time 350258426 ps
CPU time 0.84 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:51 PM PDT 24
Peak memory 201340 kb
Host smart-989c99bc-a6b7-4fc6-91ec-f5373e1d777b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182586489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.182586489
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2449583101
Short name T861
Test name
Test status
Simulation time 536120662 ps
CPU time 0.82 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201352 kb
Host smart-0473c559-c530-4f9f-91b1-adbfa7785535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449583101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2449583101
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3153178894
Short name T833
Test name
Test status
Simulation time 378946020 ps
CPU time 1.44 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201392 kb
Host smart-104e8fea-1299-4470-97a9-cd5c75f106aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153178894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3153178894
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2636789479
Short name T873
Test name
Test status
Simulation time 362578427 ps
CPU time 0.78 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201360 kb
Host smart-fb92ae5a-4335-47f3-a20d-b0a0cde052c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636789479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2636789479
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4261001698
Short name T853
Test name
Test status
Simulation time 917425204 ps
CPU time 2.46 seconds
Started Aug 07 06:24:35 PM PDT 24
Finished Aug 07 06:24:37 PM PDT 24
Peak memory 201488 kb
Host smart-7adceb29-639e-43e3-becd-f7612dcb3ba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261001698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4261001698
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1762261459
Short name T905
Test name
Test status
Simulation time 26206702532 ps
CPU time 56.95 seconds
Started Aug 07 06:24:38 PM PDT 24
Finished Aug 07 06:25:35 PM PDT 24
Peak memory 201640 kb
Host smart-68273039-f526-4dde-8427-0a3993b0c187
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762261459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1762261459
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2092731917
Short name T893
Test name
Test status
Simulation time 1314467111 ps
CPU time 1.48 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201392 kb
Host smart-2e289b4f-c8fc-4d61-9be0-c30c477f596b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092731917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2092731917
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1661166753
Short name T798
Test name
Test status
Simulation time 367979820 ps
CPU time 1.88 seconds
Started Aug 07 06:24:39 PM PDT 24
Finished Aug 07 06:24:41 PM PDT 24
Peak memory 201516 kb
Host smart-218aea89-4c74-42e8-a7d0-927792d56905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661166753 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1661166753
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2922699702
Short name T131
Test name
Test status
Simulation time 398573758 ps
CPU time 1.27 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:48 PM PDT 24
Peak memory 201380 kb
Host smart-eafcd766-1933-4824-8ba1-b5d1972ec19c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922699702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2922699702
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.871452931
Short name T871
Test name
Test status
Simulation time 352072944 ps
CPU time 0.79 seconds
Started Aug 07 06:24:38 PM PDT 24
Finished Aug 07 06:24:39 PM PDT 24
Peak memory 201236 kb
Host smart-6a173c5f-4f20-45c4-8eb0-a234c7a57ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871452931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.871452931
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2589407399
Short name T830
Test name
Test status
Simulation time 4098332247 ps
CPU time 12.72 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201648 kb
Host smart-f86f724b-a8aa-4bb8-b4bf-6cceef76a988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589407399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2589407399
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1799643961
Short name T884
Test name
Test status
Simulation time 470205508 ps
CPU time 1.74 seconds
Started Aug 07 06:24:45 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201636 kb
Host smart-a63b0b29-75ce-4f72-b7e8-1292ea7e5176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799643961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1799643961
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1215528445
Short name T889
Test name
Test status
Simulation time 399703721 ps
CPU time 0.9 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201360 kb
Host smart-d7e41dab-1eac-4dc7-931f-243ca0ec9e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215528445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1215528445
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3111738992
Short name T890
Test name
Test status
Simulation time 344828862 ps
CPU time 1.35 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201348 kb
Host smart-91f2b047-5201-4707-b5d0-aed6f40b331d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111738992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3111738992
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.178549452
Short name T820
Test name
Test status
Simulation time 388706505 ps
CPU time 1.54 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201380 kb
Host smart-5544547d-0e8f-4227-8067-6b51b68a0423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178549452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.178549452
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3158723482
Short name T862
Test name
Test status
Simulation time 384494893 ps
CPU time 1.04 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:57 PM PDT 24
Peak memory 201360 kb
Host smart-cc87f1a3-d256-4d20-990d-eb50d9b58c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158723482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3158723482
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3636186318
Short name T882
Test name
Test status
Simulation time 428772201 ps
CPU time 0.86 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201320 kb
Host smart-399931b1-f444-42fd-9e17-a73b1d676999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636186318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3636186318
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1526650279
Short name T799
Test name
Test status
Simulation time 321111892 ps
CPU time 0.81 seconds
Started Aug 07 06:24:54 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201376 kb
Host smart-969a10a9-1c70-4b77-92d5-807800074fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526650279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1526650279
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1945580284
Short name T827
Test name
Test status
Simulation time 430050073 ps
CPU time 1.66 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:55 PM PDT 24
Peak memory 201360 kb
Host smart-cba27b2c-75f2-47f4-8a87-b2768808b0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945580284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1945580284
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.538414844
Short name T883
Test name
Test status
Simulation time 525597681 ps
CPU time 0.74 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201348 kb
Host smart-d995c4fc-07f0-4b33-a1af-8d7af07ac271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538414844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.538414844
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3651329146
Short name T876
Test name
Test status
Simulation time 344576027 ps
CPU time 1.05 seconds
Started Aug 07 06:24:57 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201376 kb
Host smart-f3023df2-93cb-46a2-b4a2-0a77505e5e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651329146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3651329146
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2431854805
Short name T825
Test name
Test status
Simulation time 426374236 ps
CPU time 0.8 seconds
Started Aug 07 06:25:15 PM PDT 24
Finished Aug 07 06:25:16 PM PDT 24
Peak memory 201348 kb
Host smart-cf745720-1200-4286-a44e-83e84aa12a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431854805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2431854805
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.151518610
Short name T877
Test name
Test status
Simulation time 904886032 ps
CPU time 3.58 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201572 kb
Host smart-d20f4144-fa76-433a-bf46-add7dcaec79a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151518610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.151518610
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3382125602
Short name T856
Test name
Test status
Simulation time 52683644225 ps
CPU time 107.34 seconds
Started Aug 07 06:24:42 PM PDT 24
Finished Aug 07 06:26:30 PM PDT 24
Peak memory 201644 kb
Host smart-c4466821-ba4e-4ef6-be54-d16e270f5266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382125602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3382125602
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2727571733
Short name T892
Test name
Test status
Simulation time 874161843 ps
CPU time 1.16 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:46 PM PDT 24
Peak memory 201384 kb
Host smart-959988e6-8f09-44ab-aff3-8ecaf5beff31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727571733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2727571733
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2750249438
Short name T915
Test name
Test status
Simulation time 492162789 ps
CPU time 1.09 seconds
Started Aug 07 06:24:43 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 201516 kb
Host smart-5dd4d887-9659-4f55-a0ec-97c4e2398645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750249438 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2750249438
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1523597041
Short name T143
Test name
Test status
Simulation time 495721941 ps
CPU time 1.15 seconds
Started Aug 07 06:24:38 PM PDT 24
Finished Aug 07 06:24:39 PM PDT 24
Peak memory 201384 kb
Host smart-d5f93c02-33ee-4994-9394-97977fa41e82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523597041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1523597041
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3758073649
Short name T851
Test name
Test status
Simulation time 460915005 ps
CPU time 0.87 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201356 kb
Host smart-8ab3de05-c5f7-4e83-9c9b-2e3ede48364e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758073649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3758073649
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.14886206
Short name T914
Test name
Test status
Simulation time 5304392520 ps
CPU time 4.29 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:51 PM PDT 24
Peak memory 201600 kb
Host smart-3b561abc-aa79-4f1c-91bc-6dd42463d3e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14886206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctr
l_same_csr_outstanding.14886206
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2492201023
Short name T95
Test name
Test status
Simulation time 392390590 ps
CPU time 1.82 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:51 PM PDT 24
Peak memory 201680 kb
Host smart-29f54149-9e45-470e-9b90-bd175b09f88f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492201023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2492201023
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.536671175
Short name T868
Test name
Test status
Simulation time 4023680986 ps
CPU time 10.89 seconds
Started Aug 07 06:24:39 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201684 kb
Host smart-c447b720-92db-4a25-a3f0-8aa7eff0ed28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536671175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.536671175
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4273216358
Short name T887
Test name
Test status
Simulation time 333960777 ps
CPU time 0.84 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:56 PM PDT 24
Peak memory 201384 kb
Host smart-0b4403c5-f355-4f62-9d91-f5e08b96fa91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273216358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4273216358
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2387639456
Short name T880
Test name
Test status
Simulation time 330102976 ps
CPU time 1.08 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201348 kb
Host smart-a4f61a71-97ad-4ff3-91ae-9ceb3c520a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387639456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2387639456
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1874122507
Short name T909
Test name
Test status
Simulation time 517256984 ps
CPU time 0.92 seconds
Started Aug 07 06:24:58 PM PDT 24
Finished Aug 07 06:24:59 PM PDT 24
Peak memory 201376 kb
Host smart-14f11224-b1ab-4ce1-a5b7-ae18d0626d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874122507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1874122507
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2083718547
Short name T796
Test name
Test status
Simulation time 403389803 ps
CPU time 0.77 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201348 kb
Host smart-057aa1f4-2e21-4ddd-8961-ee525f8ef367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083718547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2083718547
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2787737519
Short name T840
Test name
Test status
Simulation time 494846107 ps
CPU time 0.89 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201340 kb
Host smart-6ac15fe8-cae6-4239-8cfb-76abf22d9210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787737519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2787737519
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.389545032
Short name T808
Test name
Test status
Simulation time 359630590 ps
CPU time 0.85 seconds
Started Aug 07 06:25:00 PM PDT 24
Finished Aug 07 06:25:01 PM PDT 24
Peak memory 201332 kb
Host smart-773f4ad4-7387-4f71-a673-2492e93ad56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389545032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.389545032
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4175512862
Short name T801
Test name
Test status
Simulation time 412493284 ps
CPU time 1.6 seconds
Started Aug 07 06:24:58 PM PDT 24
Finished Aug 07 06:25:00 PM PDT 24
Peak memory 201320 kb
Host smart-6413b022-81fa-413a-95c2-f6393e0e04c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175512862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4175512862
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3144312023
Short name T821
Test name
Test status
Simulation time 368398589 ps
CPU time 1.02 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201376 kb
Host smart-d841a1dd-09fc-4727-ba54-6ef5e6671dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144312023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3144312023
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3698084300
Short name T886
Test name
Test status
Simulation time 431048387 ps
CPU time 1.56 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201340 kb
Host smart-873c0c18-25d0-4d2d-8d6b-8cf9cf783f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698084300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3698084300
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2439900168
Short name T828
Test name
Test status
Simulation time 376406594 ps
CPU time 1.55 seconds
Started Aug 07 06:25:05 PM PDT 24
Finished Aug 07 06:25:07 PM PDT 24
Peak memory 201332 kb
Host smart-20ec3a84-85a3-4e98-968a-e719a08be532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439900168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2439900168
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3602399314
Short name T875
Test name
Test status
Simulation time 643823821 ps
CPU time 1.24 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 201512 kb
Host smart-064da5f7-3fe6-4c11-8201-327e4aaeb83e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602399314 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3602399314
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.698353121
Short name T916
Test name
Test status
Simulation time 360461680 ps
CPU time 1.47 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201280 kb
Host smart-bd1cbeed-e344-4983-b4be-3abf52207a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698353121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.698353121
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2323931030
Short name T802
Test name
Test status
Simulation time 350425142 ps
CPU time 1.06 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 201384 kb
Host smart-b9e863ca-5263-4f82-aa10-18becf24a4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323931030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2323931030
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3886226858
Short name T145
Test name
Test status
Simulation time 2127669125 ps
CPU time 1.88 seconds
Started Aug 07 06:24:40 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 201396 kb
Host smart-cba92ed9-1739-4049-850b-60427b75b3d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886226858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3886226858
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3799137032
Short name T891
Test name
Test status
Simulation time 4763195184 ps
CPU time 2.55 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201688 kb
Host smart-6ddebb8c-ea4c-4332-b083-10103fc596bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799137032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3799137032
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2754086638
Short name T907
Test name
Test status
Simulation time 539154615 ps
CPU time 1.99 seconds
Started Aug 07 06:24:56 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201516 kb
Host smart-07fb38f9-cce9-4576-9f14-13df9af15ead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754086638 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2754086638
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2775809898
Short name T888
Test name
Test status
Simulation time 614137118 ps
CPU time 1.13 seconds
Started Aug 07 06:24:52 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201380 kb
Host smart-0b4a40d9-b029-44cd-bee5-b0f641b3186c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775809898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2775809898
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2369087854
Short name T793
Test name
Test status
Simulation time 416540595 ps
CPU time 0.86 seconds
Started Aug 07 06:24:46 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 201368 kb
Host smart-e8990e50-f352-42c5-afa5-1c1c0edf0a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369087854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2369087854
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2807997936
Short name T826
Test name
Test status
Simulation time 2544017299 ps
CPU time 2.45 seconds
Started Aug 07 06:24:50 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201440 kb
Host smart-2c0d844c-5c00-412e-975d-8b51e217ef84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807997936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2807997936
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2194999302
Short name T99
Test name
Test status
Simulation time 359873929 ps
CPU time 1.66 seconds
Started Aug 07 06:24:40 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 201664 kb
Host smart-47e65574-8742-4d6b-b87d-7e70cd0376b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194999302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2194999302
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.829060346
Short name T346
Test name
Test status
Simulation time 8358552256 ps
CPU time 7.82 seconds
Started Aug 07 06:24:43 PM PDT 24
Finished Aug 07 06:24:51 PM PDT 24
Peak memory 201676 kb
Host smart-e4e8947b-2192-4593-bc66-75f540f848cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829060346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.829060346
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.52985
Short name T831
Test name
Test status
Simulation time 521339531 ps
CPU time 1.29 seconds
Started Aug 07 06:24:49 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201544 kb
Host smart-d4898e3c-9ad0-404b-9113-e4648fcefb29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52985 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.52985
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.181803242
Short name T142
Test name
Test status
Simulation time 360468235 ps
CPU time 0.93 seconds
Started Aug 07 06:24:58 PM PDT 24
Finished Aug 07 06:24:59 PM PDT 24
Peak memory 201368 kb
Host smart-b55bb6ba-5cd8-4516-ad63-1677117cf0ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181803242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.181803242
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2728506212
Short name T814
Test name
Test status
Simulation time 503400456 ps
CPU time 1.78 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201384 kb
Host smart-7a479122-6c51-4da7-9e63-93df8b52dd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728506212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2728506212
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4173496703
Short name T865
Test name
Test status
Simulation time 4548403654 ps
CPU time 2.25 seconds
Started Aug 07 06:24:51 PM PDT 24
Finished Aug 07 06:24:53 PM PDT 24
Peak memory 201636 kb
Host smart-eb3c81e2-2808-4df7-af58-42694ed95550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173496703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4173496703
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.416686578
Short name T843
Test name
Test status
Simulation time 935480818 ps
CPU time 2.93 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 209872 kb
Host smart-776c28e2-69d7-49e3-9b56-126d2457b5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416686578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.416686578
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2004440044
Short name T836
Test name
Test status
Simulation time 8897033955 ps
CPU time 23.58 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:25:11 PM PDT 24
Peak memory 201708 kb
Host smart-85f11ec4-332d-4af5-8175-79fb629f804a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004440044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2004440044
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.628973272
Short name T110
Test name
Test status
Simulation time 590626937 ps
CPU time 2.25 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201512 kb
Host smart-5ffea45a-69f2-4956-8eb5-cf9d230e95d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628973272 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.628973272
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2145052685
Short name T819
Test name
Test status
Simulation time 461133520 ps
CPU time 1.68 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:50 PM PDT 24
Peak memory 201196 kb
Host smart-b329882d-b029-4419-ab32-7f9b96a3e9f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145052685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2145052685
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1991694164
Short name T881
Test name
Test status
Simulation time 477208509 ps
CPU time 0.92 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:24:54 PM PDT 24
Peak memory 201384 kb
Host smart-1a8b07c0-90e7-4df7-af2e-f29fc2cd817d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991694164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1991694164
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2737365521
Short name T146
Test name
Test status
Simulation time 4398152689 ps
CPU time 5.57 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 201620 kb
Host smart-9980540f-221f-47a7-bc17-d7051fa52aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737365521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2737365521
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.282744217
Short name T835
Test name
Test status
Simulation time 474161163 ps
CPU time 2.19 seconds
Started Aug 07 06:24:44 PM PDT 24
Finished Aug 07 06:24:47 PM PDT 24
Peak memory 201700 kb
Host smart-ab6429a7-3dc8-4dea-a530-11854e0a1edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282744217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.282744217
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.192073027
Short name T901
Test name
Test status
Simulation time 9184583630 ps
CPU time 7.97 seconds
Started Aug 07 06:24:53 PM PDT 24
Finished Aug 07 06:25:01 PM PDT 24
Peak memory 201704 kb
Host smart-edc7db91-e123-421b-a92c-fbc6bbe832e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192073027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.192073027
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1480804951
Short name T859
Test name
Test status
Simulation time 463914179 ps
CPU time 1.19 seconds
Started Aug 07 06:25:03 PM PDT 24
Finished Aug 07 06:25:04 PM PDT 24
Peak memory 201516 kb
Host smart-8ae5ecf1-23e7-4960-8a4d-2ff3362303b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480804951 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1480804951
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1872939273
Short name T134
Test name
Test status
Simulation time 464658897 ps
CPU time 1.84 seconds
Started Aug 07 06:24:47 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201384 kb
Host smart-dc7c462c-af63-47ac-ab60-d1f01785bb55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872939273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1872939273
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4051902590
Short name T829
Test name
Test status
Simulation time 324323837 ps
CPU time 1.32 seconds
Started Aug 07 06:24:41 PM PDT 24
Finished Aug 07 06:24:42 PM PDT 24
Peak memory 201356 kb
Host smart-51b72ac3-32f9-4710-9fce-98de4eeb1791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051902590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4051902590
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.211125205
Short name T77
Test name
Test status
Simulation time 4597823731 ps
CPU time 3.89 seconds
Started Aug 07 06:24:48 PM PDT 24
Finished Aug 07 06:24:52 PM PDT 24
Peak memory 201608 kb
Host smart-b926df4a-431e-4960-945b-7f87e672e44e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211125205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.211125205
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3731538293
Short name T866
Test name
Test status
Simulation time 674946202 ps
CPU time 3.35 seconds
Started Aug 07 06:24:55 PM PDT 24
Finished Aug 07 06:24:58 PM PDT 24
Peak memory 201664 kb
Host smart-e70bb40d-3b2f-459a-9023-d434f20525c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731538293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3731538293
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1381686276
Short name T805
Test name
Test status
Simulation time 4667710469 ps
CPU time 3.8 seconds
Started Aug 07 06:24:45 PM PDT 24
Finished Aug 07 06:24:49 PM PDT 24
Peak memory 201656 kb
Host smart-3d9ed0be-f6e9-44b5-99c3-a34d53d1708c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381686276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1381686276
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3301617175
Short name T736
Test name
Test status
Simulation time 399996709 ps
CPU time 1.52 seconds
Started Aug 07 05:12:54 PM PDT 24
Finished Aug 07 05:12:56 PM PDT 24
Peak memory 201188 kb
Host smart-a56da6c5-c7ad-4715-ba85-397d3845c639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301617175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3301617175
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1098513947
Short name T340
Test name
Test status
Simulation time 369689961702 ps
CPU time 217.59 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:16:33 PM PDT 24
Peak memory 201436 kb
Host smart-e0f500fa-7e1d-474f-872f-39b0ab042411
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098513947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1098513947
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.351293167
Short name T238
Test name
Test status
Simulation time 184071954754 ps
CPU time 425.1 seconds
Started Aug 07 05:12:47 PM PDT 24
Finished Aug 07 05:19:52 PM PDT 24
Peak memory 201352 kb
Host smart-a90356ab-eb5b-4ab5-b369-4ee4b469d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351293167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.351293167
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1914965566
Short name T724
Test name
Test status
Simulation time 166795901003 ps
CPU time 105.97 seconds
Started Aug 07 05:12:50 PM PDT 24
Finished Aug 07 05:14:36 PM PDT 24
Peak memory 201476 kb
Host smart-43697065-7fc6-417f-b869-e2308cdef16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914965566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1914965566
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1183045987
Short name T516
Test name
Test status
Simulation time 161459144042 ps
CPU time 183.99 seconds
Started Aug 07 05:12:48 PM PDT 24
Finished Aug 07 05:15:52 PM PDT 24
Peak memory 201368 kb
Host smart-448c559e-44e6-49ad-a62f-5349fedd6618
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183045987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1183045987
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3172985110
Short name T190
Test name
Test status
Simulation time 484352147064 ps
CPU time 132.8 seconds
Started Aug 07 05:12:48 PM PDT 24
Finished Aug 07 05:15:01 PM PDT 24
Peak memory 201404 kb
Host smart-ae01a72e-3fcc-44a6-98f8-b0ad812d9ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172985110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3172985110
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1738617546
Short name T549
Test name
Test status
Simulation time 320019746795 ps
CPU time 98.23 seconds
Started Aug 07 05:12:51 PM PDT 24
Finished Aug 07 05:14:30 PM PDT 24
Peak memory 201340 kb
Host smart-6ed58184-931b-446a-b9ae-b5fb1543e16b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738617546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1738617546
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.345308504
Short name T501
Test name
Test status
Simulation time 391080030945 ps
CPU time 487.46 seconds
Started Aug 07 05:12:53 PM PDT 24
Finished Aug 07 05:21:01 PM PDT 24
Peak memory 200480 kb
Host smart-ed719a64-3ed8-47b9-9ba6-35bf31745098
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345308504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.345308504
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.629122334
Short name T427
Test name
Test status
Simulation time 127874296041 ps
CPU time 642.5 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:23:38 PM PDT 24
Peak memory 201752 kb
Host smart-9310c671-45a7-49e6-8e01-6de6cc0a9635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629122334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.629122334
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1728102513
Short name T455
Test name
Test status
Simulation time 24573355380 ps
CPU time 9.71 seconds
Started Aug 07 05:12:54 PM PDT 24
Finished Aug 07 05:13:04 PM PDT 24
Peak memory 201344 kb
Host smart-378176ad-6401-41f7-82c3-e430ad916600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728102513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1728102513
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1012540130
Short name T201
Test name
Test status
Simulation time 3071311590 ps
CPU time 1.54 seconds
Started Aug 07 05:12:51 PM PDT 24
Finished Aug 07 05:12:53 PM PDT 24
Peak memory 200368 kb
Host smart-4c066136-e422-4220-ba9d-e52591ff5092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012540130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1012540130
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2532949836
Short name T103
Test name
Test status
Simulation time 8235309616 ps
CPU time 5.5 seconds
Started Aug 07 05:12:56 PM PDT 24
Finished Aug 07 05:13:01 PM PDT 24
Peak memory 218184 kb
Host smart-88aec86e-f936-49b7-895c-2252f9bae359
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532949836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2532949836
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4167727629
Short name T558
Test name
Test status
Simulation time 5699864545 ps
CPU time 14.49 seconds
Started Aug 07 05:12:48 PM PDT 24
Finished Aug 07 05:13:03 PM PDT 24
Peak memory 201308 kb
Host smart-20101b22-cbf1-4a17-a24f-406fbd80763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167727629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4167727629
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1682742396
Short name T313
Test name
Test status
Simulation time 370276240891 ps
CPU time 863.07 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:27:18 PM PDT 24
Peak memory 201328 kb
Host smart-ff35d6d0-8b8a-4f24-82b9-9f737645b234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682742396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1682742396
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.409789460
Short name T332
Test name
Test status
Simulation time 222621561873 ps
CPU time 141.45 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:15:17 PM PDT 24
Peak memory 210004 kb
Host smart-2e8ecc95-98ba-479e-85cb-5b785262fbd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409789460 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.409789460
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2995529058
Short name T588
Test name
Test status
Simulation time 489518099909 ps
CPU time 616.45 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:23:11 PM PDT 24
Peak memory 201368 kb
Host smart-76e19a58-2a52-4166-a483-c2eb44caec6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995529058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2995529058
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2879656777
Short name T353
Test name
Test status
Simulation time 491304256447 ps
CPU time 430.01 seconds
Started Aug 07 05:12:55 PM PDT 24
Finished Aug 07 05:20:05 PM PDT 24
Peak memory 201384 kb
Host smart-c0f26d48-7591-4da0-ba21-c17e0f2d4e8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879656777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2879656777
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.383269094
Short name T284
Test name
Test status
Simulation time 257430133859 ps
CPU time 585.61 seconds
Started Aug 07 05:12:54 PM PDT 24
Finished Aug 07 05:22:40 PM PDT 24
Peak memory 201360 kb
Host smart-0c6ba6e2-6e2b-44aa-b998-8dc01dc511f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383269094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.383269094
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2118546543
Short name T402
Test name
Test status
Simulation time 614190827971 ps
CPU time 295.99 seconds
Started Aug 07 05:12:56 PM PDT 24
Finished Aug 07 05:17:52 PM PDT 24
Peak memory 201388 kb
Host smart-773f4552-5427-47f2-82f6-4fb9eb7a42d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118546543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2118546543
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2234549857
Short name T74
Test name
Test status
Simulation time 65554166813 ps
CPU time 302.68 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:18:03 PM PDT 24
Peak memory 201852 kb
Host smart-5a850dd8-1548-4ef0-ac30-1cde17304055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234549857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2234549857
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2059805750
Short name T631
Test name
Test status
Simulation time 30643220878 ps
CPU time 22.7 seconds
Started Aug 07 05:13:03 PM PDT 24
Finished Aug 07 05:13:25 PM PDT 24
Peak memory 201312 kb
Host smart-6950a743-b2ff-41e1-8676-a8769f2f9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059805750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2059805750
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.178007471
Short name T62
Test name
Test status
Simulation time 3853592577 ps
CPU time 9.84 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:13:11 PM PDT 24
Peak memory 201544 kb
Host smart-f81ce780-c0b6-4cbb-9cb5-aec47c34a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178007471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.178007471
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1656867709
Short name T149
Test name
Test status
Simulation time 6246270568 ps
CPU time 2.4 seconds
Started Aug 07 05:12:54 PM PDT 24
Finished Aug 07 05:12:57 PM PDT 24
Peak memory 201312 kb
Host smart-82d7240b-e59a-447f-b8dc-a9b869197ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656867709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1656867709
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3133262673
Short name T760
Test name
Test status
Simulation time 339036771541 ps
CPU time 423.34 seconds
Started Aug 07 05:13:00 PM PDT 24
Finished Aug 07 05:20:03 PM PDT 24
Peak memory 201364 kb
Host smart-08951f4b-a30e-4ca7-a8c5-388e1b64b6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133262673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3133262673
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2893629727
Short name T17
Test name
Test status
Simulation time 32849266313 ps
CPU time 84.18 seconds
Started Aug 07 05:13:00 PM PDT 24
Finished Aug 07 05:14:25 PM PDT 24
Peak memory 210092 kb
Host smart-967c2a15-f2d6-4a67-905f-ed23c6bf7d3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893629727 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2893629727
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3554544630
Short name T574
Test name
Test status
Simulation time 350788792 ps
CPU time 1.47 seconds
Started Aug 07 05:14:00 PM PDT 24
Finished Aug 07 05:14:02 PM PDT 24
Peak memory 201140 kb
Host smart-cadd63b2-002a-48e1-9935-0e26b3e228cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554544630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3554544630
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3271619229
Short name T732
Test name
Test status
Simulation time 159920328307 ps
CPU time 255.21 seconds
Started Aug 07 05:13:53 PM PDT 24
Finished Aug 07 05:18:09 PM PDT 24
Peak memory 201408 kb
Host smart-5d064352-fa89-4b09-ba6d-9bd4801710b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271619229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3271619229
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3793597068
Short name T735
Test name
Test status
Simulation time 492120979435 ps
CPU time 1175.91 seconds
Started Aug 07 05:13:59 PM PDT 24
Finished Aug 07 05:33:35 PM PDT 24
Peak memory 201620 kb
Host smart-ba860a1c-a89c-4d67-a4de-ebf5f42f1c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793597068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3793597068
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2815900792
Short name T207
Test name
Test status
Simulation time 321392859325 ps
CPU time 174.51 seconds
Started Aug 07 05:13:53 PM PDT 24
Finished Aug 07 05:16:48 PM PDT 24
Peak memory 201456 kb
Host smart-13c424f5-3724-4729-91ee-c50d1dc79ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815900792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2815900792
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3519647707
Short name T422
Test name
Test status
Simulation time 165232448990 ps
CPU time 159.73 seconds
Started Aug 07 05:13:52 PM PDT 24
Finished Aug 07 05:16:32 PM PDT 24
Peak memory 201444 kb
Host smart-bc86d1de-84e9-46bd-89ae-c21ad9291105
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519647707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3519647707
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2581505344
Short name T479
Test name
Test status
Simulation time 332308987899 ps
CPU time 391.66 seconds
Started Aug 07 05:13:52 PM PDT 24
Finished Aug 07 05:20:24 PM PDT 24
Peak memory 201408 kb
Host smart-911b78a7-15c6-431e-9a6a-6950dfba8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581505344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2581505344
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4060456047
Short name T771
Test name
Test status
Simulation time 333965843825 ps
CPU time 182.42 seconds
Started Aug 07 05:13:54 PM PDT 24
Finished Aug 07 05:16:57 PM PDT 24
Peak memory 201412 kb
Host smart-38156a9d-1c08-48c7-ba3d-93313f2bcd45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060456047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4060456047
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2298421187
Short name T116
Test name
Test status
Simulation time 607626732497 ps
CPU time 319.39 seconds
Started Aug 07 05:13:53 PM PDT 24
Finished Aug 07 05:19:13 PM PDT 24
Peak memory 201396 kb
Host smart-1ae643d9-4332-4703-9ea9-157b3ab75f70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298421187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2298421187
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1234854535
Short name T535
Test name
Test status
Simulation time 105231774025 ps
CPU time 376.33 seconds
Started Aug 07 05:14:00 PM PDT 24
Finished Aug 07 05:20:17 PM PDT 24
Peak memory 201796 kb
Host smart-8a07eee8-ff0e-4705-a579-d109a6777197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234854535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1234854535
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3771285218
Short name T528
Test name
Test status
Simulation time 22670710088 ps
CPU time 48.89 seconds
Started Aug 07 05:13:59 PM PDT 24
Finished Aug 07 05:14:48 PM PDT 24
Peak memory 201276 kb
Host smart-d9c8be01-a41a-43c4-bc63-e2dfdee3966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771285218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3771285218
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3995488751
Short name T119
Test name
Test status
Simulation time 2958697281 ps
CPU time 7.58 seconds
Started Aug 07 05:13:59 PM PDT 24
Finished Aug 07 05:14:07 PM PDT 24
Peak memory 201292 kb
Host smart-ebc2b968-f536-48b6-94b8-ad016f9cd3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995488751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3995488751
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2281057730
Short name T731
Test name
Test status
Simulation time 6052014654 ps
CPU time 15.3 seconds
Started Aug 07 05:13:53 PM PDT 24
Finished Aug 07 05:14:09 PM PDT 24
Peak memory 201280 kb
Host smart-ac048b90-38b1-4064-bf72-12973d689a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281057730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2281057730
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2371184132
Short name T668
Test name
Test status
Simulation time 1720270554556 ps
CPU time 2227.48 seconds
Started Aug 07 05:14:00 PM PDT 24
Finished Aug 07 05:51:08 PM PDT 24
Peak memory 209968 kb
Host smart-b44a85ed-de1f-47eb-b754-1b37a1d4846f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371184132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2371184132
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2321047992
Short name T775
Test name
Test status
Simulation time 208756833850 ps
CPU time 82.93 seconds
Started Aug 07 05:13:58 PM PDT 24
Finished Aug 07 05:15:21 PM PDT 24
Peak memory 210112 kb
Host smart-39a1a32e-58a3-4843-b5dd-dd819bc59c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321047992 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2321047992
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1105869461
Short name T476
Test name
Test status
Simulation time 415480913 ps
CPU time 1.57 seconds
Started Aug 07 05:14:16 PM PDT 24
Finished Aug 07 05:14:18 PM PDT 24
Peak memory 201208 kb
Host smart-d5dbe263-dcff-47df-90cd-9f66c0732471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105869461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1105869461
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3690408832
Short name T216
Test name
Test status
Simulation time 335328578119 ps
CPU time 119.53 seconds
Started Aug 07 05:14:13 PM PDT 24
Finished Aug 07 05:16:12 PM PDT 24
Peak memory 201328 kb
Host smart-06567655-406f-431f-86bb-cca7dc619458
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690408832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3690408832
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2848228629
Short name T652
Test name
Test status
Simulation time 566791834531 ps
CPU time 1203.6 seconds
Started Aug 07 05:14:09 PM PDT 24
Finished Aug 07 05:34:13 PM PDT 24
Peak memory 201476 kb
Host smart-bbb9848f-a6c4-42b3-9a79-eb2ea9e256e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848228629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2848228629
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3417297772
Short name T6
Test name
Test status
Simulation time 337592904464 ps
CPU time 755.44 seconds
Started Aug 07 05:14:05 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 201396 kb
Host smart-7dfc7ced-d8ad-442c-9883-3670676c4a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417297772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3417297772
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1683747065
Short name T531
Test name
Test status
Simulation time 326815247423 ps
CPU time 695.35 seconds
Started Aug 07 05:14:05 PM PDT 24
Finished Aug 07 05:25:41 PM PDT 24
Peak memory 201476 kb
Host smart-f8a3b143-551e-4096-81fc-74debc08f0e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683747065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1683747065
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1282393075
Short name T663
Test name
Test status
Simulation time 165667979437 ps
CPU time 383.55 seconds
Started Aug 07 05:14:00 PM PDT 24
Finished Aug 07 05:20:24 PM PDT 24
Peak memory 201412 kb
Host smart-9fc9de1f-51fb-42f4-9651-6cdb0021031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282393075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1282393075
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.83735808
Short name T635
Test name
Test status
Simulation time 323739537956 ps
CPU time 719.79 seconds
Started Aug 07 05:14:05 PM PDT 24
Finished Aug 07 05:26:05 PM PDT 24
Peak memory 201400 kb
Host smart-90b967e0-2c45-4347-9bc9-aab466d1181b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=83735808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed
.83735808
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3892891779
Short name T319
Test name
Test status
Simulation time 171877588809 ps
CPU time 238.02 seconds
Started Aug 07 05:14:04 PM PDT 24
Finished Aug 07 05:18:02 PM PDT 24
Peak memory 201372 kb
Host smart-c5aad142-f883-479a-b1a3-ff8a7b042a21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892891779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3892891779
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2706169963
Short name T789
Test name
Test status
Simulation time 621189353709 ps
CPU time 1437.17 seconds
Started Aug 07 05:14:09 PM PDT 24
Finished Aug 07 05:38:07 PM PDT 24
Peak memory 201404 kb
Host smart-2b8cb736-24fb-4eb1-9001-42b70f357184
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706169963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2706169963
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.912698182
Short name T657
Test name
Test status
Simulation time 128299175018 ps
CPU time 439.87 seconds
Started Aug 07 05:14:10 PM PDT 24
Finished Aug 07 05:21:30 PM PDT 24
Peak memory 201788 kb
Host smart-70017fe7-8af4-45f9-874f-9259c725fbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912698182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.912698182
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3115977515
Short name T527
Test name
Test status
Simulation time 40334497768 ps
CPU time 23.64 seconds
Started Aug 07 05:14:09 PM PDT 24
Finished Aug 07 05:14:32 PM PDT 24
Peak memory 201312 kb
Host smart-1e05d03a-3149-4bfa-8516-8b81a40a69ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115977515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3115977515
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.702056806
Short name T440
Test name
Test status
Simulation time 4485312250 ps
CPU time 3.2 seconds
Started Aug 07 05:14:09 PM PDT 24
Finished Aug 07 05:14:13 PM PDT 24
Peak memory 201252 kb
Host smart-c959193d-45dd-4a66-aed7-7908237d874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702056806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.702056806
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3255656661
Short name T618
Test name
Test status
Simulation time 5855814410 ps
CPU time 13.27 seconds
Started Aug 07 05:14:00 PM PDT 24
Finished Aug 07 05:14:13 PM PDT 24
Peak memory 201312 kb
Host smart-fab256eb-05a2-47b2-9d95-a964fa9a7e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255656661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3255656661
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1836746803
Short name T81
Test name
Test status
Simulation time 249881236828 ps
CPU time 184.37 seconds
Started Aug 07 05:14:10 PM PDT 24
Finished Aug 07 05:17:14 PM PDT 24
Peak memory 201384 kb
Host smart-e5bd9f17-c5b5-4c41-a0ec-81ffeac291cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836746803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1836746803
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1020793515
Short name T320
Test name
Test status
Simulation time 11448713310 ps
CPU time 37.09 seconds
Started Aug 07 05:14:12 PM PDT 24
Finished Aug 07 05:14:50 PM PDT 24
Peak memory 210056 kb
Host smart-9f734f26-78d8-4169-b842-6cd45c53e0d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020793515 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1020793515
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3256730291
Short name T685
Test name
Test status
Simulation time 338555765 ps
CPU time 0.81 seconds
Started Aug 07 05:14:35 PM PDT 24
Finished Aug 07 05:14:36 PM PDT 24
Peak memory 201416 kb
Host smart-f60aea93-ae0c-46bd-aa6c-af51f0833151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256730291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3256730291
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1772271445
Short name T258
Test name
Test status
Simulation time 322494670678 ps
CPU time 609.6 seconds
Started Aug 07 05:14:20 PM PDT 24
Finished Aug 07 05:24:30 PM PDT 24
Peak memory 201432 kb
Host smart-03394626-0711-4daa-a996-43651382e3a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772271445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1772271445
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4070115320
Short name T552
Test name
Test status
Simulation time 325874303777 ps
CPU time 202.07 seconds
Started Aug 07 05:14:21 PM PDT 24
Finished Aug 07 05:17:43 PM PDT 24
Peak memory 201456 kb
Host smart-267f650f-1d82-4bdc-8bdf-cf3b7d241333
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070115320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4070115320
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1202938067
Short name T687
Test name
Test status
Simulation time 487853169221 ps
CPU time 247.39 seconds
Started Aug 07 05:14:17 PM PDT 24
Finished Aug 07 05:18:24 PM PDT 24
Peak memory 201412 kb
Host smart-daf70a78-57df-406e-a011-70e2dbbc7b36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202938067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1202938067
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.881704034
Short name T725
Test name
Test status
Simulation time 530435202654 ps
CPU time 1177.24 seconds
Started Aug 07 05:14:21 PM PDT 24
Finished Aug 07 05:33:58 PM PDT 24
Peak memory 201392 kb
Host smart-8e9e991c-17f4-463d-b67a-04c9953c997e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881704034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.881704034
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2951272430
Short name T673
Test name
Test status
Simulation time 397153462249 ps
CPU time 487.29 seconds
Started Aug 07 05:14:22 PM PDT 24
Finished Aug 07 05:22:30 PM PDT 24
Peak memory 201372 kb
Host smart-432125ab-a5dd-4d44-a16e-d9096b2640d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951272430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2951272430
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3618715530
Short name T394
Test name
Test status
Simulation time 68152927827 ps
CPU time 256.36 seconds
Started Aug 07 05:14:32 PM PDT 24
Finished Aug 07 05:18:48 PM PDT 24
Peak memory 201840 kb
Host smart-864d323e-d63d-48e3-b98f-eeb4e2f2ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618715530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3618715530
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.552509781
Short name T381
Test name
Test status
Simulation time 46457820643 ps
CPU time 98.26 seconds
Started Aug 07 05:14:33 PM PDT 24
Finished Aug 07 05:16:11 PM PDT 24
Peak memory 201352 kb
Host smart-aa218c37-4be3-4e3c-af4f-75dfc010063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552509781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.552509781
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3912891370
Short name T781
Test name
Test status
Simulation time 5269051946 ps
CPU time 7.1 seconds
Started Aug 07 05:15:37 PM PDT 24
Finished Aug 07 05:15:44 PM PDT 24
Peak memory 201304 kb
Host smart-b51372b9-e754-4c45-b971-5ab80809bd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912891370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3912891370
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2590783186
Short name T364
Test name
Test status
Simulation time 5512495392 ps
CPU time 13.91 seconds
Started Aug 07 05:14:15 PM PDT 24
Finished Aug 07 05:14:29 PM PDT 24
Peak memory 201364 kb
Host smart-f9ddc2e5-0b68-45b9-bad7-5c4d196630a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590783186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2590783186
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1867635865
Short name T648
Test name
Test status
Simulation time 43744962957 ps
CPU time 104.18 seconds
Started Aug 07 05:14:32 PM PDT 24
Finished Aug 07 05:16:16 PM PDT 24
Peak memory 210884 kb
Host smart-2b91cfdd-9691-4bdc-8d68-56769d134a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867635865 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1867635865
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1655611712
Short name T171
Test name
Test status
Simulation time 438153956 ps
CPU time 0.85 seconds
Started Aug 07 05:14:45 PM PDT 24
Finished Aug 07 05:14:45 PM PDT 24
Peak memory 201184 kb
Host smart-c22670e2-3afc-466a-bc3a-4f9305355aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655611712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1655611712
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3444446040
Short name T249
Test name
Test status
Simulation time 169773554638 ps
CPU time 370.61 seconds
Started Aug 07 05:14:39 PM PDT 24
Finished Aug 07 05:20:50 PM PDT 24
Peak memory 201344 kb
Host smart-b4f971f5-def2-4dc5-acbb-75b3a04298d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444446040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3444446040
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.904634606
Short name T375
Test name
Test status
Simulation time 330420150444 ps
CPU time 272.08 seconds
Started Aug 07 05:14:38 PM PDT 24
Finished Aug 07 05:19:11 PM PDT 24
Peak memory 201384 kb
Host smart-06b0ab42-deb8-4eca-88b3-9c5a9c59b164
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=904634606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.904634606
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3223032186
Short name T632
Test name
Test status
Simulation time 163962029001 ps
CPU time 93.79 seconds
Started Aug 07 05:14:31 PM PDT 24
Finished Aug 07 05:16:05 PM PDT 24
Peak memory 201396 kb
Host smart-cd79eef7-5327-42f0-a67c-f74a4a0ecab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223032186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3223032186
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2237041054
Short name T379
Test name
Test status
Simulation time 169586504898 ps
CPU time 201.56 seconds
Started Aug 07 05:14:32 PM PDT 24
Finished Aug 07 05:17:54 PM PDT 24
Peak memory 201404 kb
Host smart-a65c0cb0-2316-442b-b3c0-22299f2166c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237041054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2237041054
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1457380625
Short name T310
Test name
Test status
Simulation time 353281621291 ps
CPU time 822.65 seconds
Started Aug 07 05:14:38 PM PDT 24
Finished Aug 07 05:28:21 PM PDT 24
Peak memory 201316 kb
Host smart-fd429d1e-7597-4233-b0b3-9a976dd74c51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457380625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1457380625
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1570016401
Short name T738
Test name
Test status
Simulation time 88929765562 ps
CPU time 457.91 seconds
Started Aug 07 05:14:46 PM PDT 24
Finished Aug 07 05:22:24 PM PDT 24
Peak memory 201692 kb
Host smart-bd6c7732-36d1-4aea-ae5b-8ad8ba7520cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570016401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1570016401
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3384620382
Short name T418
Test name
Test status
Simulation time 32174801962 ps
CPU time 38.09 seconds
Started Aug 07 05:14:43 PM PDT 24
Finished Aug 07 05:15:21 PM PDT 24
Peak memory 201280 kb
Host smart-d444432e-16cc-47dd-89a3-63520749cc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384620382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3384620382
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2258428413
Short name T651
Test name
Test status
Simulation time 3027590695 ps
CPU time 7.68 seconds
Started Aug 07 05:14:38 PM PDT 24
Finished Aug 07 05:14:46 PM PDT 24
Peak memory 201340 kb
Host smart-699baee8-0b6f-42ce-8d54-5f32d013e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258428413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2258428413
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.907535522
Short name T510
Test name
Test status
Simulation time 5923359675 ps
CPU time 7.5 seconds
Started Aug 07 05:14:33 PM PDT 24
Finished Aug 07 05:14:41 PM PDT 24
Peak memory 201296 kb
Host smart-b45e43f0-1eed-4751-bb75-52521de3c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907535522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.907535522
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3009791480
Short name T678
Test name
Test status
Simulation time 515103408101 ps
CPU time 801.03 seconds
Started Aug 07 05:14:44 PM PDT 24
Finished Aug 07 05:28:05 PM PDT 24
Peak memory 201396 kb
Host smart-37bc167e-91af-43ba-88ee-0da6d7ee2aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009791480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3009791480
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2343986374
Short name T643
Test name
Test status
Simulation time 21202942023 ps
CPU time 73.79 seconds
Started Aug 07 05:14:45 PM PDT 24
Finished Aug 07 05:15:59 PM PDT 24
Peak memory 210092 kb
Host smart-357e0688-62f5-4692-a3e0-2c6432712dd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343986374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2343986374
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1198118230
Short name T94
Test name
Test status
Simulation time 314582500 ps
CPU time 1.3 seconds
Started Aug 07 05:15:05 PM PDT 24
Finished Aug 07 05:15:07 PM PDT 24
Peak memory 201164 kb
Host smart-a0b8343f-7bef-4fda-8ea9-59534b5b271f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198118230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1198118230
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3295375751
Short name T773
Test name
Test status
Simulation time 164508535726 ps
CPU time 100.6 seconds
Started Aug 07 05:14:58 PM PDT 24
Finished Aug 07 05:16:39 PM PDT 24
Peak memory 201404 kb
Host smart-ccbe7ba9-2242-4a13-ab13-bbbb159c7879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295375751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3295375751
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.568038403
Short name T604
Test name
Test status
Simulation time 491137435490 ps
CPU time 994.12 seconds
Started Aug 07 05:14:51 PM PDT 24
Finished Aug 07 05:31:26 PM PDT 24
Peak memory 201452 kb
Host smart-b7bbcbcb-b762-4bca-9199-606fb26ccaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568038403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.568038403
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3020657759
Short name T504
Test name
Test status
Simulation time 323642935100 ps
CPU time 378.01 seconds
Started Aug 07 05:14:51 PM PDT 24
Finished Aug 07 05:21:09 PM PDT 24
Peak memory 201396 kb
Host smart-ac8e81c3-e5a9-4daf-b524-50d454e2a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020657759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3020657759
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.304705265
Short name T458
Test name
Test status
Simulation time 332610096886 ps
CPU time 372.34 seconds
Started Aug 07 05:14:52 PM PDT 24
Finished Aug 07 05:21:05 PM PDT 24
Peak memory 201448 kb
Host smart-c7ccb7ec-757c-4a9b-bbb0-9f8d25898975
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=304705265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.304705265
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2512405242
Short name T285
Test name
Test status
Simulation time 569930133050 ps
CPU time 344.88 seconds
Started Aug 07 05:14:52 PM PDT 24
Finished Aug 07 05:20:37 PM PDT 24
Peak memory 201400 kb
Host smart-e83b580d-8e54-4b0b-8fab-8df301e73370
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512405242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2512405242
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2729017845
Short name T770
Test name
Test status
Simulation time 411406173130 ps
CPU time 91.27 seconds
Started Aug 07 05:14:50 PM PDT 24
Finished Aug 07 05:16:22 PM PDT 24
Peak memory 201356 kb
Host smart-5b4cc939-2f95-42b9-8c93-d4d9ea230b6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729017845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2729017845
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.4289795470
Short name T603
Test name
Test status
Simulation time 123261066792 ps
CPU time 513.48 seconds
Started Aug 07 05:14:59 PM PDT 24
Finished Aug 07 05:23:33 PM PDT 24
Peak memory 201836 kb
Host smart-bfca996c-583c-4746-ab25-70465204fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289795470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.4289795470
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.928954348
Short name T439
Test name
Test status
Simulation time 42569327361 ps
CPU time 90.55 seconds
Started Aug 07 05:14:59 PM PDT 24
Finished Aug 07 05:16:30 PM PDT 24
Peak memory 201316 kb
Host smart-d57cd2ea-6cf8-493b-9d54-71c4f0fbf0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928954348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.928954348
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1673278161
Short name T198
Test name
Test status
Simulation time 5426971120 ps
CPU time 6.4 seconds
Started Aug 07 05:14:58 PM PDT 24
Finished Aug 07 05:15:04 PM PDT 24
Peak memory 201280 kb
Host smart-0e29adcc-dff6-40ee-a68c-04259aadadf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673278161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1673278161
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1385197336
Short name T554
Test name
Test status
Simulation time 6060116031 ps
CPU time 4.29 seconds
Started Aug 07 05:15:36 PM PDT 24
Finished Aug 07 05:15:41 PM PDT 24
Peak memory 201276 kb
Host smart-0a4a018c-0c4c-47d6-995a-dd8d617091f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385197336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1385197336
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.4088481217
Short name T453
Test name
Test status
Simulation time 56651191672 ps
CPU time 25.43 seconds
Started Aug 07 05:15:05 PM PDT 24
Finished Aug 07 05:15:30 PM PDT 24
Peak memory 201284 kb
Host smart-91cc1697-1715-4944-b3d4-347f726199f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088481217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.4088481217
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2800859408
Short name T696
Test name
Test status
Simulation time 197025807158 ps
CPU time 490.6 seconds
Started Aug 07 05:14:58 PM PDT 24
Finished Aug 07 05:23:09 PM PDT 24
Peak memory 210120 kb
Host smart-04f15a8d-043f-40a8-aa38-b7e2ca2437ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800859408 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2800859408
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2750746767
Short name T203
Test name
Test status
Simulation time 438448199 ps
CPU time 1.14 seconds
Started Aug 07 05:15:18 PM PDT 24
Finished Aug 07 05:15:19 PM PDT 24
Peak memory 201160 kb
Host smart-592b7ae4-6b32-4c61-a4cd-14d390cf9c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750746767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2750746767
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.419261515
Short name T212
Test name
Test status
Simulation time 178042987153 ps
CPU time 114.61 seconds
Started Aug 07 05:15:15 PM PDT 24
Finished Aug 07 05:17:10 PM PDT 24
Peak memory 201348 kb
Host smart-11dbf7ab-c95f-4d9b-b5ca-4ee3a212adba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419261515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.419261515
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2946102364
Short name T656
Test name
Test status
Simulation time 430246514675 ps
CPU time 60.3 seconds
Started Aug 07 05:15:13 PM PDT 24
Finished Aug 07 05:16:14 PM PDT 24
Peak memory 201384 kb
Host smart-8d084781-6822-4f79-adaa-04d650e5923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946102364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2946102364
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2581712548
Short name T575
Test name
Test status
Simulation time 164651402530 ps
CPU time 124.66 seconds
Started Aug 07 05:15:07 PM PDT 24
Finished Aug 07 05:17:11 PM PDT 24
Peak memory 201404 kb
Host smart-6798172c-8d46-4458-8f6d-fc03d22c3751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581712548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2581712548
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2413463635
Short name T532
Test name
Test status
Simulation time 492348739956 ps
CPU time 311.05 seconds
Started Aug 07 05:15:07 PM PDT 24
Finished Aug 07 05:20:18 PM PDT 24
Peak memory 201384 kb
Host smart-95c91775-aba7-400c-937f-9b977279f472
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413463635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2413463635
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1414555411
Short name T208
Test name
Test status
Simulation time 334593275259 ps
CPU time 141.86 seconds
Started Aug 07 05:15:06 PM PDT 24
Finished Aug 07 05:17:28 PM PDT 24
Peak memory 201388 kb
Host smart-4751b6d7-e7e2-4e2d-8ddb-ab6198cd2639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414555411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1414555411
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3864775052
Short name T705
Test name
Test status
Simulation time 499604438475 ps
CPU time 1143.2 seconds
Started Aug 07 05:15:06 PM PDT 24
Finished Aug 07 05:34:10 PM PDT 24
Peak memory 201456 kb
Host smart-b96d5516-f21c-462f-ad33-93533a09671c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864775052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3864775052
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3056444866
Short name T782
Test name
Test status
Simulation time 197917704670 ps
CPU time 113.82 seconds
Started Aug 07 05:15:10 PM PDT 24
Finished Aug 07 05:17:04 PM PDT 24
Peak memory 201396 kb
Host smart-063a41b4-c832-4973-8e17-bdfe548ce259
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056444866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3056444866
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1127945343
Short name T471
Test name
Test status
Simulation time 600125826570 ps
CPU time 1253.06 seconds
Started Aug 07 05:15:12 PM PDT 24
Finished Aug 07 05:36:05 PM PDT 24
Peak memory 201412 kb
Host smart-e8f276f9-2a84-467e-9e1e-b1fa14ac163c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127945343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1127945343
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.574316985
Short name T69
Test name
Test status
Simulation time 79310529786 ps
CPU time 288.13 seconds
Started Aug 07 05:15:18 PM PDT 24
Finished Aug 07 05:20:06 PM PDT 24
Peak memory 201800 kb
Host smart-277afced-79ab-4e2c-b03a-6be50b034b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574316985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.574316985
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1526414101
Short name T765
Test name
Test status
Simulation time 40555938624 ps
CPU time 13.46 seconds
Started Aug 07 05:15:13 PM PDT 24
Finished Aug 07 05:15:27 PM PDT 24
Peak memory 201284 kb
Host smart-a9ddd6ff-593b-4104-a623-e664cf76e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526414101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1526414101
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3195520591
Short name T56
Test name
Test status
Simulation time 3807936329 ps
CPU time 2.01 seconds
Started Aug 07 05:15:13 PM PDT 24
Finished Aug 07 05:15:15 PM PDT 24
Peak memory 201208 kb
Host smart-2d4c252d-9f9a-44c6-99d2-26fd5ef18ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195520591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3195520591
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1218244283
Short name T779
Test name
Test status
Simulation time 5733205416 ps
CPU time 14.42 seconds
Started Aug 07 05:15:06 PM PDT 24
Finished Aug 07 05:15:20 PM PDT 24
Peak memory 201276 kb
Host smart-cbff04da-9d79-46e0-918e-1c854d9eff14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218244283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1218244283
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2709142642
Short name T281
Test name
Test status
Simulation time 336209300884 ps
CPU time 208.11 seconds
Started Aug 07 05:15:18 PM PDT 24
Finished Aug 07 05:18:46 PM PDT 24
Peak memory 201364 kb
Host smart-15c3e64f-e9d5-4a58-afb6-3e295f950d58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709142642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2709142642
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2300035728
Short name T774
Test name
Test status
Simulation time 49168668902 ps
CPU time 103.07 seconds
Started Aug 07 05:15:17 PM PDT 24
Finished Aug 07 05:17:00 PM PDT 24
Peak memory 209808 kb
Host smart-3e3f3b83-5296-4a93-ae1d-faf0b84d3a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300035728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2300035728
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3820212272
Short name T619
Test name
Test status
Simulation time 348383004 ps
CPU time 0.8 seconds
Started Aug 07 05:15:36 PM PDT 24
Finished Aug 07 05:15:36 PM PDT 24
Peak memory 201192 kb
Host smart-4e7f8e32-9472-430f-a041-76a021a22a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820212272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3820212272
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2914762193
Short name T344
Test name
Test status
Simulation time 164639225964 ps
CPU time 239.55 seconds
Started Aug 07 05:15:25 PM PDT 24
Finished Aug 07 05:19:25 PM PDT 24
Peak memory 201356 kb
Host smart-e343ca9a-348c-4da4-976e-fc2b32a79c38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914762193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2914762193
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3978719298
Short name T524
Test name
Test status
Simulation time 408418743424 ps
CPU time 905.51 seconds
Started Aug 07 05:15:22 PM PDT 24
Finished Aug 07 05:30:28 PM PDT 24
Peak memory 201508 kb
Host smart-c07efc13-57f3-42a2-a53e-34943a888145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978719298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3978719298
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3541394234
Short name T327
Test name
Test status
Simulation time 489732002597 ps
CPU time 531.81 seconds
Started Aug 07 05:15:17 PM PDT 24
Finished Aug 07 05:24:09 PM PDT 24
Peak memory 201676 kb
Host smart-616e5deb-524e-4fc2-bac7-1597301200f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541394234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3541394234
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2095610403
Short name T768
Test name
Test status
Simulation time 492610028856 ps
CPU time 599.43 seconds
Started Aug 07 05:15:18 PM PDT 24
Finished Aug 07 05:25:17 PM PDT 24
Peak memory 201380 kb
Host smart-fc97fdc6-bd27-43bf-8f68-a6620ed8fbbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095610403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2095610403
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2833995026
Short name T58
Test name
Test status
Simulation time 166412390363 ps
CPU time 98.47 seconds
Started Aug 07 05:15:20 PM PDT 24
Finished Aug 07 05:16:59 PM PDT 24
Peak memory 201408 kb
Host smart-ad524b03-7598-4735-9d0d-e8f235a76452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833995026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2833995026
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2916251479
Short name T355
Test name
Test status
Simulation time 495113754556 ps
CPU time 1125.82 seconds
Started Aug 07 05:15:19 PM PDT 24
Finished Aug 07 05:34:06 PM PDT 24
Peak memory 201396 kb
Host smart-261afe1a-918c-45a2-866f-2f4a101f158d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916251479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2916251479
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3420039493
Short name T484
Test name
Test status
Simulation time 187490739013 ps
CPU time 115.97 seconds
Started Aug 07 05:15:25 PM PDT 24
Finished Aug 07 05:17:21 PM PDT 24
Peak memory 201424 kb
Host smart-e5cf56a2-2ceb-4a36-8f18-3e88bb7b03b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420039493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3420039493
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1754703545
Short name T721
Test name
Test status
Simulation time 95814908196 ps
CPU time 317.3 seconds
Started Aug 07 05:15:22 PM PDT 24
Finished Aug 07 05:20:40 PM PDT 24
Peak memory 201756 kb
Host smart-cee91f07-a439-4b7d-98b5-fbe2d80dad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754703545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1754703545
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.330205297
Short name T688
Test name
Test status
Simulation time 45603642475 ps
CPU time 26.38 seconds
Started Aug 07 05:15:25 PM PDT 24
Finished Aug 07 05:15:52 PM PDT 24
Peak memory 201316 kb
Host smart-8bdaf549-a06f-4392-bcf5-52e59c2d83ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330205297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.330205297
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.564196646
Short name T33
Test name
Test status
Simulation time 4597810960 ps
CPU time 2.9 seconds
Started Aug 07 05:15:23 PM PDT 24
Finished Aug 07 05:15:26 PM PDT 24
Peak memory 201316 kb
Host smart-665d2b3c-cc50-4893-9e42-5251af0a7c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564196646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.564196646
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3754739789
Short name T689
Test name
Test status
Simulation time 5770612627 ps
CPU time 14.58 seconds
Started Aug 07 05:15:19 PM PDT 24
Finished Aug 07 05:15:34 PM PDT 24
Peak memory 201276 kb
Host smart-9ac3468a-8545-4b7e-8dbb-70408f2140d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754739789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3754739789
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1270323763
Short name T669
Test name
Test status
Simulation time 170617718107 ps
CPU time 380.66 seconds
Started Aug 07 05:15:34 PM PDT 24
Finished Aug 07 05:21:54 PM PDT 24
Peak memory 201788 kb
Host smart-1299eb7e-92f0-4d73-adcf-2dd8842e8565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270323763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1270323763
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.32388135
Short name T581
Test name
Test status
Simulation time 382285914 ps
CPU time 0.85 seconds
Started Aug 07 05:15:56 PM PDT 24
Finished Aug 07 05:15:57 PM PDT 24
Peak memory 201196 kb
Host smart-07f16490-46fa-4312-9003-81205791a95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32388135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.32388135
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.661874620
Short name T252
Test name
Test status
Simulation time 342658567591 ps
CPU time 821.29 seconds
Started Aug 07 05:15:45 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 201372 kb
Host smart-1b9d65dc-9bdc-464f-bc54-5f34381df9b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661874620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.661874620
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3379673564
Short name T410
Test name
Test status
Simulation time 489351091932 ps
CPU time 1156 seconds
Started Aug 07 05:15:36 PM PDT 24
Finished Aug 07 05:34:52 PM PDT 24
Peak memory 201476 kb
Host smart-b0dd4486-8773-4ef3-a121-4e69964d7d4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379673564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3379673564
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2601327390
Short name T215
Test name
Test status
Simulation time 331882465036 ps
CPU time 710.54 seconds
Started Aug 07 05:15:43 PM PDT 24
Finished Aug 07 05:27:34 PM PDT 24
Peak memory 201424 kb
Host smart-392b157a-ecfa-47dd-99a4-d13a47676984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601327390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2601327390
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3988812761
Short name T44
Test name
Test status
Simulation time 332580549667 ps
CPU time 363.04 seconds
Started Aug 07 05:15:36 PM PDT 24
Finished Aug 07 05:21:39 PM PDT 24
Peak memory 201416 kb
Host smart-09c6a246-2d9e-4b04-944c-5a8a1979fe60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988812761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3988812761
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3415631810
Short name T296
Test name
Test status
Simulation time 516318208858 ps
CPU time 1080.5 seconds
Started Aug 07 05:15:34 PM PDT 24
Finished Aug 07 05:33:35 PM PDT 24
Peak memory 201324 kb
Host smart-d8bf1294-c707-4c9d-adf9-c25d108cd8a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415631810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3415631810
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1247306296
Short name T485
Test name
Test status
Simulation time 190577267876 ps
CPU time 404.16 seconds
Started Aug 07 05:15:45 PM PDT 24
Finished Aug 07 05:22:29 PM PDT 24
Peak memory 201364 kb
Host smart-163e2b23-e466-41a8-9ea2-b995d5940180
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247306296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1247306296
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2003203800
Short name T591
Test name
Test status
Simulation time 141555097562 ps
CPU time 567.05 seconds
Started Aug 07 05:15:48 PM PDT 24
Finished Aug 07 05:25:15 PM PDT 24
Peak memory 201800 kb
Host smart-582a10bf-36f9-4686-8a17-5cc2905f3d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003203800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2003203800
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4000196888
Short name T595
Test name
Test status
Simulation time 29693974657 ps
CPU time 69.24 seconds
Started Aug 07 05:15:41 PM PDT 24
Finished Aug 07 05:16:50 PM PDT 24
Peak memory 201280 kb
Host smart-57e2e2e9-0d66-4bee-a472-1bc403815b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000196888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4000196888
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2632274129
Short name T200
Test name
Test status
Simulation time 2764687941 ps
CPU time 7.52 seconds
Started Aug 07 05:15:41 PM PDT 24
Finished Aug 07 05:15:49 PM PDT 24
Peak memory 201316 kb
Host smart-36090a9a-f6b6-4b38-9430-2f9c3d60c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632274129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2632274129
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.593261366
Short name T413
Test name
Test status
Simulation time 5873770098 ps
CPU time 13.63 seconds
Started Aug 07 05:15:39 PM PDT 24
Finished Aug 07 05:15:53 PM PDT 24
Peak memory 201344 kb
Host smart-ad67ee70-2db2-4593-a09d-11eec1e0652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593261366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.593261366
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2794790851
Short name T533
Test name
Test status
Simulation time 279945783 ps
CPU time 1.19 seconds
Started Aug 07 05:16:00 PM PDT 24
Finished Aug 07 05:16:01 PM PDT 24
Peak memory 201180 kb
Host smart-9f49e29f-0640-4805-bba6-980ccd19da91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794790851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2794790851
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3548511310
Short name T271
Test name
Test status
Simulation time 297355587114 ps
CPU time 517.14 seconds
Started Aug 07 05:16:00 PM PDT 24
Finished Aug 07 05:24:38 PM PDT 24
Peak memory 201424 kb
Host smart-729b7a21-cbd1-4a1d-b25f-8c903258ea90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548511310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3548511310
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3964619494
Short name T55
Test name
Test status
Simulation time 328622541299 ps
CPU time 244.17 seconds
Started Aug 07 05:15:57 PM PDT 24
Finished Aug 07 05:20:01 PM PDT 24
Peak memory 201416 kb
Host smart-7a4990a2-18be-43f0-b81d-5d6ae99056cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964619494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3964619494
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2234776585
Short name T435
Test name
Test status
Simulation time 164540617168 ps
CPU time 378.03 seconds
Started Aug 07 05:15:58 PM PDT 24
Finished Aug 07 05:22:16 PM PDT 24
Peak memory 201432 kb
Host smart-09e667f7-faac-479e-9167-14429bb2b369
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234776585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2234776585
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2089918281
Short name T599
Test name
Test status
Simulation time 492620999764 ps
CPU time 1086.19 seconds
Started Aug 07 05:15:54 PM PDT 24
Finished Aug 07 05:34:00 PM PDT 24
Peak memory 201300 kb
Host smart-f89508b6-be68-4510-8db5-d9eeb93a7457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089918281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2089918281
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1716201965
Short name T204
Test name
Test status
Simulation time 161726550336 ps
CPU time 317.45 seconds
Started Aug 07 05:15:54 PM PDT 24
Finished Aug 07 05:21:12 PM PDT 24
Peak memory 201328 kb
Host smart-9e93cc95-30fa-414b-9781-c21b532cdff1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716201965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1716201965
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2138712972
Short name T169
Test name
Test status
Simulation time 453587359846 ps
CPU time 285.48 seconds
Started Aug 07 05:15:57 PM PDT 24
Finished Aug 07 05:20:43 PM PDT 24
Peak memory 201360 kb
Host smart-bd07076d-e2bd-493d-ae02-66f69e8b9823
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138712972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2138712972
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1763481213
Short name T747
Test name
Test status
Simulation time 210437065155 ps
CPU time 97.53 seconds
Started Aug 07 05:16:01 PM PDT 24
Finished Aug 07 05:17:39 PM PDT 24
Peak memory 201472 kb
Host smart-6d6842cd-edfc-498f-becd-008ade1d2f9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763481213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1763481213
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3265744681
Short name T667
Test name
Test status
Simulation time 36268638861 ps
CPU time 68.9 seconds
Started Aug 07 05:16:00 PM PDT 24
Finished Aug 07 05:17:09 PM PDT 24
Peak memory 201276 kb
Host smart-dfa6c49d-8d4d-4e30-8762-1053b426145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265744681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3265744681
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1779900901
Short name T525
Test name
Test status
Simulation time 4231638118 ps
CPU time 10.39 seconds
Started Aug 07 05:16:00 PM PDT 24
Finished Aug 07 05:16:10 PM PDT 24
Peak memory 201252 kb
Host smart-f8c842a9-24ab-4757-8a90-29cd02db644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779900901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1779900901
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3744218054
Short name T570
Test name
Test status
Simulation time 5657576791 ps
CPU time 13.38 seconds
Started Aug 07 05:15:54 PM PDT 24
Finished Aug 07 05:16:08 PM PDT 24
Peak memory 201320 kb
Host smart-23ade567-6c32-44e2-84c2-64843031655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744218054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3744218054
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4221582704
Short name T742
Test name
Test status
Simulation time 1131364468997 ps
CPU time 1299.48 seconds
Started Aug 07 05:16:02 PM PDT 24
Finished Aug 07 05:37:42 PM PDT 24
Peak memory 209932 kb
Host smart-283cdb50-2cfe-4fa9-8763-6f1bc34d8b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221582704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4221582704
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2063810711
Short name T49
Test name
Test status
Simulation time 82502224277 ps
CPU time 91.94 seconds
Started Aug 07 05:15:59 PM PDT 24
Finished Aug 07 05:17:31 PM PDT 24
Peak memory 217808 kb
Host smart-a4d85a95-35cf-4848-9789-1bdf3195cbb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063810711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2063810711
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3102114351
Short name T566
Test name
Test status
Simulation time 542641326 ps
CPU time 0.95 seconds
Started Aug 07 05:16:30 PM PDT 24
Finished Aug 07 05:16:31 PM PDT 24
Peak memory 201180 kb
Host smart-06cb41f8-4437-4fcd-bbf9-bceb93796d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102114351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3102114351
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.930036247
Short name T246
Test name
Test status
Simulation time 498752442992 ps
CPU time 616.89 seconds
Started Aug 07 05:16:07 PM PDT 24
Finished Aug 07 05:26:24 PM PDT 24
Peak memory 201424 kb
Host smart-d1ba7e9e-7e27-4d59-ba98-456298c1c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930036247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.930036247
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1809552617
Short name T159
Test name
Test status
Simulation time 482886016693 ps
CPU time 89.8 seconds
Started Aug 07 05:16:07 PM PDT 24
Finished Aug 07 05:17:37 PM PDT 24
Peak memory 201416 kb
Host smart-d1d0588e-c6d4-4f37-a06c-fbd7e69f8d96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809552617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1809552617
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3839805182
Short name T764
Test name
Test status
Simulation time 163293104263 ps
CPU time 390 seconds
Started Aug 07 05:16:09 PM PDT 24
Finished Aug 07 05:22:39 PM PDT 24
Peak memory 201412 kb
Host smart-e057d368-b99a-4945-9651-ef850a0cb1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839805182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3839805182
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1380263197
Short name T126
Test name
Test status
Simulation time 492586393457 ps
CPU time 1134.52 seconds
Started Aug 07 05:16:09 PM PDT 24
Finished Aug 07 05:35:04 PM PDT 24
Peak memory 201312 kb
Host smart-3fabf011-e60c-478c-993d-f4e852a79a4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380263197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1380263197
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.148642543
Short name T184
Test name
Test status
Simulation time 363129144223 ps
CPU time 133.1 seconds
Started Aug 07 05:16:07 PM PDT 24
Finished Aug 07 05:18:21 PM PDT 24
Peak memory 201452 kb
Host smart-1d152f71-5007-48be-9d72-46d3c7dedb7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148642543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.148642543
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.598816757
Short name T714
Test name
Test status
Simulation time 383262611282 ps
CPU time 816.24 seconds
Started Aug 07 05:16:15 PM PDT 24
Finished Aug 07 05:29:51 PM PDT 24
Peak memory 201392 kb
Host smart-4cd25ad3-8f20-46e5-aa12-16f87f2de105
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598816757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.598816757
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1509505156
Short name T582
Test name
Test status
Simulation time 93074055913 ps
CPU time 395.53 seconds
Started Aug 07 05:16:25 PM PDT 24
Finished Aug 07 05:23:00 PM PDT 24
Peak memory 201780 kb
Host smart-67398d57-fc51-40f9-8e12-2851d318ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509505156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1509505156
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1103173023
Short name T571
Test name
Test status
Simulation time 31997697693 ps
CPU time 19.72 seconds
Started Aug 07 05:16:26 PM PDT 24
Finished Aug 07 05:16:45 PM PDT 24
Peak memory 201284 kb
Host smart-80e85428-d48d-40ae-a4f4-26da63398481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103173023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1103173023
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2721484419
Short name T430
Test name
Test status
Simulation time 5352277893 ps
CPU time 3.51 seconds
Started Aug 07 05:16:23 PM PDT 24
Finished Aug 07 05:16:26 PM PDT 24
Peak memory 201272 kb
Host smart-7dbcf31e-d370-4268-aa1f-7b2e9a27de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721484419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2721484419
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4227128301
Short name T523
Test name
Test status
Simulation time 5870786357 ps
CPU time 15.22 seconds
Started Aug 07 05:16:06 PM PDT 24
Finished Aug 07 05:16:21 PM PDT 24
Peak memory 201276 kb
Host smart-71879a67-d1b0-402e-bd3b-be29cbaccd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227128301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4227128301
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2520952713
Short name T697
Test name
Test status
Simulation time 171292792738 ps
CPU time 280.08 seconds
Started Aug 07 05:16:29 PM PDT 24
Finished Aug 07 05:21:09 PM PDT 24
Peak memory 201420 kb
Host smart-d452167f-a2e6-4165-8725-190901c1162d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520952713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2520952713
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.794240965
Short name T546
Test name
Test status
Simulation time 16490457552 ps
CPU time 31.78 seconds
Started Aug 07 05:16:23 PM PDT 24
Finished Aug 07 05:16:54 PM PDT 24
Peak memory 209820 kb
Host smart-4926dcdb-fb27-4ef5-a177-c9db22bb95a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794240965 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.794240965
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4246721925
Short name T41
Test name
Test status
Simulation time 333299822 ps
CPU time 0.8 seconds
Started Aug 07 05:13:31 PM PDT 24
Finished Aug 07 05:13:32 PM PDT 24
Peak memory 201200 kb
Host smart-1b091888-91d9-448e-a4b4-9f67449a1c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246721925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4246721925
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2445724563
Short name T633
Test name
Test status
Simulation time 166271662519 ps
CPU time 203.98 seconds
Started Aug 07 05:13:03 PM PDT 24
Finished Aug 07 05:16:27 PM PDT 24
Peak memory 201320 kb
Host smart-f70935fd-5124-43ac-9ade-6d7e3110de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445724563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2445724563
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2164023666
Short name T164
Test name
Test status
Simulation time 323130869622 ps
CPU time 756.24 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:25:37 PM PDT 24
Peak memory 201352 kb
Host smart-a7e0d81d-5db7-43a5-a837-e7d08d2ff0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164023666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2164023666
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1937076826
Short name T472
Test name
Test status
Simulation time 161654836016 ps
CPU time 26.45 seconds
Started Aug 07 05:13:04 PM PDT 24
Finished Aug 07 05:13:31 PM PDT 24
Peak memory 201412 kb
Host smart-289e307a-c479-4172-8ddf-e20162d6d741
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937076826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1937076826
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1234145617
Short name T205
Test name
Test status
Simulation time 160155435347 ps
CPU time 99.02 seconds
Started Aug 07 05:13:02 PM PDT 24
Finished Aug 07 05:14:42 PM PDT 24
Peak memory 201364 kb
Host smart-214db7c8-b50a-4a83-9eb0-5885e01ff873
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234145617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1234145617
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3423511831
Short name T264
Test name
Test status
Simulation time 179524865140 ps
CPU time 415.66 seconds
Started Aug 07 05:13:01 PM PDT 24
Finished Aug 07 05:19:57 PM PDT 24
Peak memory 201368 kb
Host smart-f17284fa-cabc-48ab-a832-58381f28d063
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423511831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3423511831
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3882291213
Short name T371
Test name
Test status
Simulation time 595308645580 ps
CPU time 1225.69 seconds
Started Aug 07 05:13:02 PM PDT 24
Finished Aug 07 05:33:27 PM PDT 24
Peak memory 200464 kb
Host smart-71c232d0-4a85-4b91-a025-5240019825ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882291213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3882291213
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.144404162
Short name T223
Test name
Test status
Simulation time 133285482521 ps
CPU time 560.43 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:22:26 PM PDT 24
Peak memory 201852 kb
Host smart-c958b198-4f31-4a92-b161-ec46d0b555df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144404162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.144404162
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2726326078
Short name T646
Test name
Test status
Simulation time 41657454737 ps
CPU time 51.52 seconds
Started Aug 07 05:13:08 PM PDT 24
Finished Aug 07 05:14:00 PM PDT 24
Peak memory 201300 kb
Host smart-78fb2adf-338e-45bc-b3b3-116dca12cdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726326078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2726326078
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3743028462
Short name T467
Test name
Test status
Simulation time 5205309845 ps
CPU time 13.38 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:13:20 PM PDT 24
Peak memory 201296 kb
Host smart-49f3b7bb-31b4-42be-82a8-3191153eb15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743028462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3743028462
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3122676392
Short name T102
Test name
Test status
Simulation time 4593116148 ps
CPU time 3.36 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:13:11 PM PDT 24
Peak memory 217048 kb
Host smart-f259c680-599c-4859-9dc5-c74cd4acc284
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122676392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3122676392
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1821446533
Short name T660
Test name
Test status
Simulation time 5810813520 ps
CPU time 12.96 seconds
Started Aug 07 05:13:00 PM PDT 24
Finished Aug 07 05:13:14 PM PDT 24
Peak memory 201296 kb
Host smart-f7c1376c-3cfe-4d87-bca3-a564d278bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821446533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1821446533
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2925832045
Short name T188
Test name
Test status
Simulation time 363808672807 ps
CPU time 1460.24 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:37:27 PM PDT 24
Peak memory 209932 kb
Host smart-4761156d-b70d-4227-afe0-f15efb5767f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925832045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2925832045
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2929361873
Short name T334
Test name
Test status
Simulation time 70491624202 ps
CPU time 35.84 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:13:43 PM PDT 24
Peak memory 209724 kb
Host smart-e3f50e55-f8aa-4514-8754-a53abd7e61f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929361873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2929361873
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3388619906
Short name T655
Test name
Test status
Simulation time 575139814 ps
CPU time 0.69 seconds
Started Aug 07 05:16:51 PM PDT 24
Finished Aug 07 05:16:51 PM PDT 24
Peak memory 201208 kb
Host smart-1064a568-4e62-4c94-b28b-89538e8bfdd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388619906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3388619906
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3875647354
Short name T753
Test name
Test status
Simulation time 192365207709 ps
CPU time 353.05 seconds
Started Aug 07 05:16:46 PM PDT 24
Finished Aug 07 05:22:39 PM PDT 24
Peak memory 201372 kb
Host smart-002c71db-20d1-464c-97ce-cc00b02ab5fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875647354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3875647354
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1652306114
Short name T661
Test name
Test status
Simulation time 529756231399 ps
CPU time 626.94 seconds
Started Aug 07 05:16:45 PM PDT 24
Finished Aug 07 05:27:12 PM PDT 24
Peak memory 201404 kb
Host smart-ce38fc74-aed2-48eb-8275-e33a7aa3cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652306114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1652306114
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2277911615
Short name T791
Test name
Test status
Simulation time 164475389974 ps
CPU time 104.31 seconds
Started Aug 07 05:16:35 PM PDT 24
Finished Aug 07 05:18:19 PM PDT 24
Peak memory 201412 kb
Host smart-c240426a-0f61-451a-921a-72698315a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277911615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2277911615
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3835705078
Short name T626
Test name
Test status
Simulation time 325823391026 ps
CPU time 751.83 seconds
Started Aug 07 05:16:32 PM PDT 24
Finished Aug 07 05:29:04 PM PDT 24
Peak memory 201368 kb
Host smart-d96fa77b-f705-4562-a8b1-152466605e9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835705078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3835705078
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3110473452
Short name T693
Test name
Test status
Simulation time 166326189210 ps
CPU time 96.27 seconds
Started Aug 07 05:16:28 PM PDT 24
Finished Aug 07 05:18:04 PM PDT 24
Peak memory 201408 kb
Host smart-52f460be-4f53-41f2-9cbb-d96b16dd93ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110473452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3110473452
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.307478800
Short name T356
Test name
Test status
Simulation time 328193620700 ps
CPU time 203.38 seconds
Started Aug 07 05:16:28 PM PDT 24
Finished Aug 07 05:19:52 PM PDT 24
Peak memory 201340 kb
Host smart-4e3c00df-3ea9-47b7-b0c6-dba4aa2efce7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=307478800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.307478800
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.344067547
Short name T273
Test name
Test status
Simulation time 388678079646 ps
CPU time 941.23 seconds
Started Aug 07 05:16:39 PM PDT 24
Finished Aug 07 05:32:21 PM PDT 24
Peak memory 201356 kb
Host smart-f10f77dd-adad-4b06-81a3-7f69e41b6d10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344067547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.344067547
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2504246386
Short name T424
Test name
Test status
Simulation time 606930290134 ps
CPU time 660.49 seconds
Started Aug 07 05:16:37 PM PDT 24
Finished Aug 07 05:27:37 PM PDT 24
Peak memory 201352 kb
Host smart-7a32efdd-5d1a-4b8b-8ffa-8b87d7e70c10
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504246386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2504246386
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.471462734
Short name T514
Test name
Test status
Simulation time 36508578458 ps
CPU time 22.81 seconds
Started Aug 07 05:16:48 PM PDT 24
Finished Aug 07 05:17:11 PM PDT 24
Peak memory 201304 kb
Host smart-297430fc-7f83-4b39-a5bc-ffa1097469d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471462734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.471462734
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3272822388
Short name T450
Test name
Test status
Simulation time 5140251448 ps
CPU time 11.65 seconds
Started Aug 07 05:16:44 PM PDT 24
Finished Aug 07 05:16:56 PM PDT 24
Peak memory 201320 kb
Host smart-03e5c9f4-6aaf-4458-8252-e191c1b5ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272822388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3272822388
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.783262335
Short name T393
Test name
Test status
Simulation time 5753366430 ps
CPU time 4.03 seconds
Started Aug 07 05:16:27 PM PDT 24
Finished Aug 07 05:16:31 PM PDT 24
Peak memory 201304 kb
Host smart-fc1f0257-b850-4759-bf83-218311ac0af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783262335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.783262335
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1938009505
Short name T304
Test name
Test status
Simulation time 201424018688 ps
CPU time 32.13 seconds
Started Aug 07 05:16:51 PM PDT 24
Finished Aug 07 05:17:23 PM PDT 24
Peak memory 201380 kb
Host smart-e8aa27b8-b82b-49e3-9aad-a6cef7e6e546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938009505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1938009505
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.18007862
Short name T109
Test name
Test status
Simulation time 166541813858 ps
CPU time 162.55 seconds
Started Aug 07 05:16:48 PM PDT 24
Finished Aug 07 05:19:30 PM PDT 24
Peak memory 210108 kb
Host smart-d97d0b01-145a-4979-802f-7a5fd0cd17cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18007862 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.18007862
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2122214293
Short name T380
Test name
Test status
Simulation time 492862015 ps
CPU time 0.84 seconds
Started Aug 07 05:17:05 PM PDT 24
Finished Aug 07 05:17:06 PM PDT 24
Peak memory 201204 kb
Host smart-3d6f36f4-4e34-4869-8218-9384ffc80e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122214293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2122214293
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1098507710
Short name T544
Test name
Test status
Simulation time 165905686275 ps
CPU time 197.32 seconds
Started Aug 07 05:16:56 PM PDT 24
Finished Aug 07 05:20:13 PM PDT 24
Peak memory 201440 kb
Host smart-ea65ca52-15bc-4e32-83b4-4964d0dff7b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098507710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1098507710
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1583730753
Short name T115
Test name
Test status
Simulation time 491766916221 ps
CPU time 298.26 seconds
Started Aug 07 05:16:55 PM PDT 24
Finished Aug 07 05:21:53 PM PDT 24
Peak memory 201464 kb
Host smart-f4d79470-6dfd-4ed0-90fd-ac7d27e85803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583730753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1583730753
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3298458213
Short name T642
Test name
Test status
Simulation time 165166810622 ps
CPU time 97.6 seconds
Started Aug 07 05:16:58 PM PDT 24
Finished Aug 07 05:18:36 PM PDT 24
Peak memory 201380 kb
Host smart-cf16ee89-58df-4bc4-9d2e-e79c3b496a34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298458213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3298458213
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3441291183
Short name T629
Test name
Test status
Simulation time 491962629687 ps
CPU time 274.56 seconds
Started Aug 07 05:16:50 PM PDT 24
Finished Aug 07 05:21:25 PM PDT 24
Peak memory 201352 kb
Host smart-e111e6e4-9825-4157-a519-2b1bb3358a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441291183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3441291183
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.468919841
Short name T449
Test name
Test status
Simulation time 165778753852 ps
CPU time 99.59 seconds
Started Aug 07 05:16:51 PM PDT 24
Finished Aug 07 05:18:30 PM PDT 24
Peak memory 201392 kb
Host smart-983b5876-f019-4001-9a36-17492bd06e4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=468919841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.468919841
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.242387970
Short name T386
Test name
Test status
Simulation time 586056870914 ps
CPU time 696.13 seconds
Started Aug 07 05:16:55 PM PDT 24
Finished Aug 07 05:28:31 PM PDT 24
Peak memory 201404 kb
Host smart-126b8251-0b7f-481c-872e-f9ad977d6f77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242387970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.242387970
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.357515717
Short name T649
Test name
Test status
Simulation time 88307030894 ps
CPU time 439.67 seconds
Started Aug 07 05:16:59 PM PDT 24
Finished Aug 07 05:24:19 PM PDT 24
Peak memory 201800 kb
Host smart-3aca4f65-853f-42d3-893c-2c1cc09de699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357515717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.357515717
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2669456002
Short name T616
Test name
Test status
Simulation time 46106781004 ps
CPU time 49.42 seconds
Started Aug 07 05:16:58 PM PDT 24
Finished Aug 07 05:17:48 PM PDT 24
Peak memory 201280 kb
Host smart-32975f20-027e-416c-bd29-df77d979aa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669456002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2669456002
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2898136890
Short name T475
Test name
Test status
Simulation time 3381419760 ps
CPU time 2.69 seconds
Started Aug 07 05:17:03 PM PDT 24
Finished Aug 07 05:17:06 PM PDT 24
Peak memory 201304 kb
Host smart-8e142e75-e67a-4e00-a1e0-9167a67a91ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898136890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2898136890
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3431036112
Short name T202
Test name
Test status
Simulation time 5839681886 ps
CPU time 3.94 seconds
Started Aug 07 05:16:51 PM PDT 24
Finished Aug 07 05:16:55 PM PDT 24
Peak memory 201304 kb
Host smart-36b9c96e-be04-4265-88b5-a30cfaf18a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431036112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3431036112
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3979675730
Short name T480
Test name
Test status
Simulation time 165317061412 ps
CPU time 364.45 seconds
Started Aug 07 05:17:06 PM PDT 24
Finished Aug 07 05:23:11 PM PDT 24
Peak memory 201424 kb
Host smart-583257b9-ceef-43db-ab46-81f81bb5db08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979675730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3979675730
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3356645758
Short name T488
Test name
Test status
Simulation time 177814723456 ps
CPU time 72.34 seconds
Started Aug 07 05:17:06 PM PDT 24
Finished Aug 07 05:18:18 PM PDT 24
Peak memory 209760 kb
Host smart-76b30b28-a19d-4628-bbdb-3faa0d790413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356645758 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3356645758
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3744833784
Short name T671
Test name
Test status
Simulation time 322854419 ps
CPU time 0.77 seconds
Started Aug 07 05:17:22 PM PDT 24
Finished Aug 07 05:17:23 PM PDT 24
Peak memory 201180 kb
Host smart-e57a7737-f1a3-4df4-a52a-a5e0b757f00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744833784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3744833784
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1730277125
Short name T311
Test name
Test status
Simulation time 326606002975 ps
CPU time 357.33 seconds
Started Aug 07 05:17:23 PM PDT 24
Finished Aug 07 05:23:20 PM PDT 24
Peak memory 201400 kb
Host smart-e1971d55-70e2-4f98-81c7-715a16088ceb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730277125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1730277125
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.442162870
Short name T438
Test name
Test status
Simulation time 326825163914 ps
CPU time 390.68 seconds
Started Aug 07 05:17:13 PM PDT 24
Finished Aug 07 05:23:44 PM PDT 24
Peak memory 201392 kb
Host smart-13b13973-0ba9-4927-aaf2-c91e38958cce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=442162870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.442162870
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4185315856
Short name T589
Test name
Test status
Simulation time 163643553208 ps
CPU time 38.17 seconds
Started Aug 07 05:17:03 PM PDT 24
Finished Aug 07 05:17:42 PM PDT 24
Peak memory 201368 kb
Host smart-ea25715a-b9a5-4150-bed5-35b9348ad226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185315856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4185315856
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2187930335
Short name T452
Test name
Test status
Simulation time 325530600869 ps
CPU time 201.97 seconds
Started Aug 07 05:17:05 PM PDT 24
Finished Aug 07 05:20:28 PM PDT 24
Peak memory 201396 kb
Host smart-a623439b-509a-4b0f-b46c-f859c0b6ce4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187930335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2187930335
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2271965085
Short name T692
Test name
Test status
Simulation time 181497762324 ps
CPU time 213.02 seconds
Started Aug 07 05:17:16 PM PDT 24
Finished Aug 07 05:20:49 PM PDT 24
Peak memory 201396 kb
Host smart-1fb867ee-9101-48f2-8c5b-dcbb9817b430
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271965085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2271965085
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2676685773
Short name T521
Test name
Test status
Simulation time 405527599669 ps
CPU time 189.53 seconds
Started Aug 07 05:17:12 PM PDT 24
Finished Aug 07 05:20:22 PM PDT 24
Peak memory 201412 kb
Host smart-e918f32a-0ba7-4574-a37f-eddf0f95d70f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676685773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2676685773
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1867626717
Short name T515
Test name
Test status
Simulation time 111802585724 ps
CPU time 456.45 seconds
Started Aug 07 05:17:15 PM PDT 24
Finished Aug 07 05:24:52 PM PDT 24
Peak memory 201760 kb
Host smart-656246e0-151f-4c6d-b955-e16093e32465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867626717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1867626717
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.713099877
Short name T761
Test name
Test status
Simulation time 36066941168 ps
CPU time 79.02 seconds
Started Aug 07 05:17:15 PM PDT 24
Finished Aug 07 05:18:35 PM PDT 24
Peak memory 201308 kb
Host smart-2f62ddbc-86f8-4592-b86f-1068ddadcb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713099877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.713099877
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2646378724
Short name T60
Test name
Test status
Simulation time 4419042118 ps
CPU time 11.25 seconds
Started Aug 07 05:17:17 PM PDT 24
Finished Aug 07 05:17:28 PM PDT 24
Peak memory 201272 kb
Host smart-b76c06c0-74f1-42f3-b868-c673e76ef571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646378724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2646378724
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1954533216
Short name T211
Test name
Test status
Simulation time 6137989460 ps
CPU time 7.84 seconds
Started Aug 07 05:17:05 PM PDT 24
Finished Aug 07 05:17:13 PM PDT 24
Peak memory 201276 kb
Host smart-983a342b-0942-45b9-8f38-e1d7b2251c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954533216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1954533216
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2147630089
Short name T624
Test name
Test status
Simulation time 167125131057 ps
CPU time 172.33 seconds
Started Aug 07 05:17:23 PM PDT 24
Finished Aug 07 05:20:15 PM PDT 24
Peak memory 201456 kb
Host smart-30059b81-c5e1-4d58-8397-a9b35e6b4c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147630089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2147630089
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2435718024
Short name T280
Test name
Test status
Simulation time 56303220714 ps
CPU time 113.38 seconds
Started Aug 07 05:17:24 PM PDT 24
Finished Aug 07 05:19:17 PM PDT 24
Peak memory 209760 kb
Host smart-258f07fa-77d4-4aff-a86f-27ed81467dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435718024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2435718024
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2597484723
Short name T653
Test name
Test status
Simulation time 353277254 ps
CPU time 1.38 seconds
Started Aug 07 05:17:39 PM PDT 24
Finished Aug 07 05:17:40 PM PDT 24
Peak memory 201208 kb
Host smart-6a5a7929-18dd-4085-b466-6a9bd57e98da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597484723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2597484723
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.661678665
Short name T758
Test name
Test status
Simulation time 195151050215 ps
CPU time 431.13 seconds
Started Aug 07 05:17:33 PM PDT 24
Finished Aug 07 05:24:45 PM PDT 24
Peak memory 201424 kb
Host smart-8222ab29-cf34-4804-95f3-98572b8449d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661678665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.661678665
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1945992830
Short name T577
Test name
Test status
Simulation time 163882078929 ps
CPU time 62.47 seconds
Started Aug 07 05:17:34 PM PDT 24
Finished Aug 07 05:18:37 PM PDT 24
Peak memory 201452 kb
Host smart-d5f3c262-9210-4837-946b-e226af722e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945992830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1945992830
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3178822105
Short name T391
Test name
Test status
Simulation time 168558913275 ps
CPU time 372.91 seconds
Started Aug 07 05:17:35 PM PDT 24
Finished Aug 07 05:23:48 PM PDT 24
Peak memory 201412 kb
Host smart-1b31023a-849e-438e-acde-697047205f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178822105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3178822105
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1279403170
Short name T403
Test name
Test status
Simulation time 335144395462 ps
CPU time 195.36 seconds
Started Aug 07 05:17:26 PM PDT 24
Finished Aug 07 05:20:42 PM PDT 24
Peak memory 201384 kb
Host smart-4f2a6ebd-dbfb-46d9-b8fd-4703c1f4c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279403170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1279403170
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1116357785
Short name T502
Test name
Test status
Simulation time 492461256191 ps
CPU time 266.02 seconds
Started Aug 07 05:17:28 PM PDT 24
Finished Aug 07 05:21:54 PM PDT 24
Peak memory 201396 kb
Host smart-9913432c-a1f0-48fa-a275-11eaa58f489e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116357785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1116357785
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3252360521
Short name T324
Test name
Test status
Simulation time 351843471232 ps
CPU time 703.16 seconds
Started Aug 07 05:17:33 PM PDT 24
Finished Aug 07 05:29:17 PM PDT 24
Peak memory 201396 kb
Host smart-462d685e-b02a-4c2f-b6c6-5f016c5be932
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252360521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3252360521
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3244470250
Short name T750
Test name
Test status
Simulation time 593569505117 ps
CPU time 239.67 seconds
Started Aug 07 05:17:32 PM PDT 24
Finished Aug 07 05:21:31 PM PDT 24
Peak memory 201436 kb
Host smart-ee458c0f-a82c-42a6-8b33-805a6fe44147
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244470250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3244470250
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4247876539
Short name T351
Test name
Test status
Simulation time 84048420275 ps
CPU time 450.74 seconds
Started Aug 07 05:19:02 PM PDT 24
Finished Aug 07 05:26:33 PM PDT 24
Peak memory 201752 kb
Host smart-9cdde494-6c37-4503-8c5c-cc11b3e9457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247876539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4247876539
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2301829598
Short name T772
Test name
Test status
Simulation time 43637495506 ps
CPU time 27.43 seconds
Started Aug 07 05:17:40 PM PDT 24
Finished Aug 07 05:18:08 PM PDT 24
Peak memory 201236 kb
Host smart-06b8bf39-8ca7-419d-9c11-4bff30aa8c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301829598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2301829598
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2988043681
Short name T441
Test name
Test status
Simulation time 4549258259 ps
CPU time 6.19 seconds
Started Aug 07 05:17:40 PM PDT 24
Finished Aug 07 05:17:46 PM PDT 24
Peak memory 201288 kb
Host smart-deab677e-b3d3-4759-abe7-6519a9b00606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988043681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2988043681
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1953608423
Short name T445
Test name
Test status
Simulation time 5782955550 ps
CPU time 2.98 seconds
Started Aug 07 05:17:29 PM PDT 24
Finished Aug 07 05:17:33 PM PDT 24
Peak memory 201264 kb
Host smart-a3d4b2b2-7157-45d2-9311-78309434f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953608423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1953608423
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3079599684
Short name T621
Test name
Test status
Simulation time 173106077460 ps
CPU time 74.39 seconds
Started Aug 07 05:17:38 PM PDT 24
Finished Aug 07 05:18:53 PM PDT 24
Peak memory 201336 kb
Host smart-dcc64698-5255-47e2-902a-a105476d7ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079599684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3079599684
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3454869693
Short name T239
Test name
Test status
Simulation time 17232888634 ps
CPU time 53.1 seconds
Started Aug 07 05:17:38 PM PDT 24
Finished Aug 07 05:18:31 PM PDT 24
Peak memory 210072 kb
Host smart-21a72bfc-8b1e-4a9c-9d8a-939c6563576a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454869693 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3454869693
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1294706623
Short name T562
Test name
Test status
Simulation time 528456661 ps
CPU time 0.95 seconds
Started Aug 07 05:17:54 PM PDT 24
Finished Aug 07 05:17:55 PM PDT 24
Peak memory 201180 kb
Host smart-f5cccf61-8be3-43ec-a1c9-cd1509014489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294706623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1294706623
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.511163436
Short name T206
Test name
Test status
Simulation time 545233125045 ps
CPU time 407.59 seconds
Started Aug 07 05:17:50 PM PDT 24
Finished Aug 07 05:24:38 PM PDT 24
Peak memory 201424 kb
Host smart-3650f039-ad31-4f5c-b258-eb6d3a1e6ae9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511163436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.511163436
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4173804118
Short name T598
Test name
Test status
Simulation time 343463484198 ps
CPU time 209.38 seconds
Started Aug 07 05:17:50 PM PDT 24
Finished Aug 07 05:21:19 PM PDT 24
Peak memory 201492 kb
Host smart-816b980e-29d0-4687-bb05-8efabd33f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173804118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4173804118
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1839214069
Short name T338
Test name
Test status
Simulation time 503218376843 ps
CPU time 1192.44 seconds
Started Aug 07 05:17:41 PM PDT 24
Finished Aug 07 05:37:34 PM PDT 24
Peak memory 201452 kb
Host smart-225b44fe-9d6b-4b60-9ca4-41b5979bf9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839214069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1839214069
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1332439204
Short name T542
Test name
Test status
Simulation time 160105161036 ps
CPU time 56.04 seconds
Started Aug 07 05:17:43 PM PDT 24
Finished Aug 07 05:18:39 PM PDT 24
Peak memory 201408 kb
Host smart-f4d1a2b6-eca1-494d-9e5d-4cdb56163be6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332439204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1332439204
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.820507705
Short name T232
Test name
Test status
Simulation time 330883198228 ps
CPU time 194.5 seconds
Started Aug 07 05:19:01 PM PDT 24
Finished Aug 07 05:22:16 PM PDT 24
Peak memory 201396 kb
Host smart-dff3ace2-7a7c-4c3c-b456-1ebc2a0b8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820507705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.820507705
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.588067944
Short name T578
Test name
Test status
Simulation time 160545470568 ps
CPU time 240.64 seconds
Started Aug 07 05:17:45 PM PDT 24
Finished Aug 07 05:21:45 PM PDT 24
Peak memory 201400 kb
Host smart-bdbdead6-2c1d-49f1-9f18-ca3a6752a2b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=588067944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.588067944
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1222924002
Short name T342
Test name
Test status
Simulation time 536333164657 ps
CPU time 289.12 seconds
Started Aug 07 05:17:45 PM PDT 24
Finished Aug 07 05:22:34 PM PDT 24
Peak memory 201380 kb
Host smart-67b67aa3-40bd-43ea-aee8-b1bf4a5a8800
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222924002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1222924002
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4146258154
Short name T555
Test name
Test status
Simulation time 197825008149 ps
CPU time 135.72 seconds
Started Aug 07 05:17:51 PM PDT 24
Finished Aug 07 05:20:07 PM PDT 24
Peak memory 201412 kb
Host smart-5dff2fa9-f53b-4401-99ae-a7095cd21e7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146258154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4146258154
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3399434878
Short name T25
Test name
Test status
Simulation time 100878095647 ps
CPU time 370.34 seconds
Started Aug 07 05:17:54 PM PDT 24
Finished Aug 07 05:24:05 PM PDT 24
Peak memory 201892 kb
Host smart-5c2af41c-4bae-49fd-9f94-b6ace3dede4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399434878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3399434878
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1654164111
Short name T639
Test name
Test status
Simulation time 44318287430 ps
CPU time 8.63 seconds
Started Aug 07 05:17:56 PM PDT 24
Finished Aug 07 05:18:05 PM PDT 24
Peak memory 201304 kb
Host smart-e3a9fc07-a94e-48e7-a736-70ad7a4db15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654164111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1654164111
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2225318736
Short name T568
Test name
Test status
Simulation time 4071259779 ps
CPU time 10.15 seconds
Started Aug 07 05:17:49 PM PDT 24
Finished Aug 07 05:17:59 PM PDT 24
Peak memory 201228 kb
Host smart-3c1f66cd-b7ce-4494-a53d-2a7aae8a175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225318736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2225318736
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3858539321
Short name T560
Test name
Test status
Simulation time 6063347184 ps
CPU time 5.74 seconds
Started Aug 07 05:17:45 PM PDT 24
Finished Aug 07 05:17:51 PM PDT 24
Peak memory 201308 kb
Host smart-9db737de-c38c-4966-ab6d-b497d2624d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858539321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3858539321
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1375102217
Short name T16
Test name
Test status
Simulation time 244186585593 ps
CPU time 237.66 seconds
Started Aug 07 05:17:55 PM PDT 24
Finished Aug 07 05:21:52 PM PDT 24
Peak memory 217372 kb
Host smart-f77b1e69-f4f1-4c21-a51f-ec785d0af54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375102217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1375102217
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3154019150
Short name T448
Test name
Test status
Simulation time 359316982 ps
CPU time 1.4 seconds
Started Aug 07 05:18:17 PM PDT 24
Finished Aug 07 05:18:18 PM PDT 24
Peak memory 201212 kb
Host smart-21d834f7-7802-4e49-91dc-d2ff607463ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154019150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3154019150
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2579499071
Short name T748
Test name
Test status
Simulation time 496214919840 ps
CPU time 161.75 seconds
Started Aug 07 05:18:05 PM PDT 24
Finished Aug 07 05:20:47 PM PDT 24
Peak memory 201428 kb
Host smart-ce0fe883-6679-4641-b268-e8d817eb6aec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579499071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2579499071
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3357854327
Short name T316
Test name
Test status
Simulation time 365643403029 ps
CPU time 366.26 seconds
Started Aug 07 05:18:06 PM PDT 24
Finished Aug 07 05:24:13 PM PDT 24
Peak memory 201392 kb
Host smart-0ffa21b3-b158-4abd-adb9-d07de468f0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357854327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3357854327
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2463010117
Short name T780
Test name
Test status
Simulation time 164835311538 ps
CPU time 112.85 seconds
Started Aug 07 05:18:00 PM PDT 24
Finished Aug 07 05:19:53 PM PDT 24
Peak memory 201440 kb
Host smart-1da8d182-d3c8-4caf-a59e-2aa26d22785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463010117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2463010117
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1553399869
Short name T444
Test name
Test status
Simulation time 166202445009 ps
CPU time 408.29 seconds
Started Aug 07 05:17:59 PM PDT 24
Finished Aug 07 05:24:48 PM PDT 24
Peak memory 201384 kb
Host smart-11d074c5-c11f-4ea2-b1fb-6227ed0b3d1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553399869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1553399869
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.92387729
Short name T1
Test name
Test status
Simulation time 494937152136 ps
CPU time 1048.18 seconds
Started Aug 07 05:18:01 PM PDT 24
Finished Aug 07 05:35:29 PM PDT 24
Peak memory 201388 kb
Host smart-bd37362f-4801-44e4-8527-146718f8c44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92387729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.92387729
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1602713447
Short name T129
Test name
Test status
Simulation time 164916930143 ps
CPU time 90.62 seconds
Started Aug 07 05:18:00 PM PDT 24
Finished Aug 07 05:19:31 PM PDT 24
Peak memory 201472 kb
Host smart-a5e90212-7eb5-45d7-b70e-6d34d492bafa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602713447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1602713447
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4171812283
Short name T181
Test name
Test status
Simulation time 368979542098 ps
CPU time 199.2 seconds
Started Aug 07 05:18:00 PM PDT 24
Finished Aug 07 05:21:20 PM PDT 24
Peak memory 201324 kb
Host smart-bbbea321-8f7b-46c0-82ed-e24fe008c75c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171812283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4171812283
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3437993383
Short name T127
Test name
Test status
Simulation time 415305307929 ps
CPU time 935.59 seconds
Started Aug 07 05:18:06 PM PDT 24
Finished Aug 07 05:33:41 PM PDT 24
Peak memory 201372 kb
Host smart-b5824dc8-08f7-4a2b-bb71-b9dacd392b06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437993383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3437993383
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4158913349
Short name T46
Test name
Test status
Simulation time 70842246854 ps
CPU time 265.91 seconds
Started Aug 07 05:18:17 PM PDT 24
Finished Aug 07 05:22:43 PM PDT 24
Peak memory 201784 kb
Host smart-58c7d6d6-1655-42b3-aa82-bca1ad1b48e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158913349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4158913349
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1745436730
Short name T718
Test name
Test status
Simulation time 25583973410 ps
CPU time 53.9 seconds
Started Aug 07 05:18:10 PM PDT 24
Finished Aug 07 05:19:04 PM PDT 24
Peak memory 201356 kb
Host smart-7a5667d5-48b9-4445-8853-f8579d3f8453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745436730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1745436730
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3665733649
Short name T398
Test name
Test status
Simulation time 3170357702 ps
CPU time 7.57 seconds
Started Aug 07 05:18:06 PM PDT 24
Finished Aug 07 05:18:14 PM PDT 24
Peak memory 201284 kb
Host smart-7c7962eb-ded2-44d0-b9b7-ef5480699b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665733649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3665733649
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1911894901
Short name T376
Test name
Test status
Simulation time 5812721300 ps
CPU time 4.29 seconds
Started Aug 07 05:18:00 PM PDT 24
Finished Aug 07 05:18:04 PM PDT 24
Peak memory 201348 kb
Host smart-09a86a9e-1a28-4095-8830-f6a932dfb9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911894901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1911894901
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2898853638
Short name T754
Test name
Test status
Simulation time 63403525196 ps
CPU time 88.83 seconds
Started Aug 07 05:18:16 PM PDT 24
Finished Aug 07 05:19:45 PM PDT 24
Peak memory 210188 kb
Host smart-983de62a-8319-40d7-9989-031b8056dcbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898853638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2898853638
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.238954258
Short name T744
Test name
Test status
Simulation time 426803392 ps
CPU time 1.57 seconds
Started Aug 07 05:18:35 PM PDT 24
Finished Aug 07 05:18:37 PM PDT 24
Peak memory 201180 kb
Host smart-579eac87-8310-4d43-b19b-9cfd8c53e885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238954258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.238954258
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2946311005
Short name T547
Test name
Test status
Simulation time 498315539692 ps
CPU time 1224.93 seconds
Started Aug 07 05:18:27 PM PDT 24
Finished Aug 07 05:38:52 PM PDT 24
Peak memory 201388 kb
Host smart-a6dad9bf-6307-4182-9b7e-2eb2b2df2443
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946311005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2946311005
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2299139046
Short name T315
Test name
Test status
Simulation time 325799010260 ps
CPU time 338.75 seconds
Started Aug 07 05:18:23 PM PDT 24
Finished Aug 07 05:24:02 PM PDT 24
Peak memory 201424 kb
Host smart-80765c2e-8d3e-4101-8b9c-ec76b935a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299139046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2299139046
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2761460716
Short name T387
Test name
Test status
Simulation time 493651818276 ps
CPU time 1163.21 seconds
Started Aug 07 05:18:24 PM PDT 24
Finished Aug 07 05:37:47 PM PDT 24
Peak memory 201380 kb
Host smart-c5c480bb-1e83-4e78-bd37-2a647a5deede
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761460716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2761460716
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.63563180
Short name T487
Test name
Test status
Simulation time 477265047925 ps
CPU time 1114.24 seconds
Started Aug 07 05:18:24 PM PDT 24
Finished Aug 07 05:36:59 PM PDT 24
Peak memory 201368 kb
Host smart-0f9dc26a-dd77-486a-b814-6204f23e2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63563180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.63563180
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4004056156
Short name T352
Test name
Test status
Simulation time 328323436516 ps
CPU time 197.28 seconds
Started Aug 07 05:18:16 PM PDT 24
Finished Aug 07 05:21:34 PM PDT 24
Peak memory 201416 kb
Host smart-64253507-8b0f-4ab8-a65e-2172cf24845c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004056156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4004056156
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.350103796
Short name T788
Test name
Test status
Simulation time 164316620221 ps
CPU time 191.72 seconds
Started Aug 07 05:18:23 PM PDT 24
Finished Aug 07 05:21:35 PM PDT 24
Peak memory 201380 kb
Host smart-33e812f3-6e2a-48cc-9eb1-499865639f65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350103796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.350103796
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1582318082
Short name T396
Test name
Test status
Simulation time 603089924304 ps
CPU time 1290.99 seconds
Started Aug 07 05:18:26 PM PDT 24
Finished Aug 07 05:39:57 PM PDT 24
Peak memory 201388 kb
Host smart-29012fd4-1b05-40b6-9f73-38789981e96f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582318082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1582318082
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.532054545
Short name T71
Test name
Test status
Simulation time 130635562805 ps
CPU time 506.9 seconds
Started Aug 07 05:18:30 PM PDT 24
Finished Aug 07 05:26:57 PM PDT 24
Peak memory 201776 kb
Host smart-4decb2c5-2060-4d88-a8bb-5d2642621765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532054545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.532054545
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1404173995
Short name T706
Test name
Test status
Simulation time 24207341082 ps
CPU time 24.86 seconds
Started Aug 07 05:18:29 PM PDT 24
Finished Aug 07 05:18:54 PM PDT 24
Peak memory 201316 kb
Host smart-64f7f71f-0732-4451-aa78-f843c7873b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404173995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1404173995
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2246298516
Short name T606
Test name
Test status
Simulation time 5102267848 ps
CPU time 1.83 seconds
Started Aug 07 05:18:29 PM PDT 24
Finished Aug 07 05:18:31 PM PDT 24
Peak memory 201300 kb
Host smart-7503b393-fa4b-4075-93b5-3c1421d7b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246298516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2246298516
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2936441297
Short name T367
Test name
Test status
Simulation time 5996144864 ps
CPU time 4.61 seconds
Started Aug 07 05:18:17 PM PDT 24
Finished Aug 07 05:18:22 PM PDT 24
Peak memory 201308 kb
Host smart-778ed901-3a92-4a04-ad2e-1848c9f03153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936441297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2936441297
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3763910351
Short name T254
Test name
Test status
Simulation time 169356762600 ps
CPU time 376.57 seconds
Started Aug 07 05:18:35 PM PDT 24
Finished Aug 07 05:24:51 PM PDT 24
Peak memory 201424 kb
Host smart-bcf9380b-f1f4-47f9-afb4-939f28862180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763910351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3763910351
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2551605628
Short name T622
Test name
Test status
Simulation time 288071755053 ps
CPU time 199.45 seconds
Started Aug 07 05:18:29 PM PDT 24
Finished Aug 07 05:21:48 PM PDT 24
Peak memory 218196 kb
Host smart-88d17468-4e08-47f8-9061-8797895cd8c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551605628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2551605628
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.808974514
Short name T443
Test name
Test status
Simulation time 346271654 ps
CPU time 1.39 seconds
Started Aug 07 05:18:54 PM PDT 24
Finished Aug 07 05:18:56 PM PDT 24
Peak memory 201184 kb
Host smart-57896d20-f766-4121-bfd5-d0c571eabf0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808974514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.808974514
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2111395631
Short name T303
Test name
Test status
Simulation time 188695562951 ps
CPU time 122.37 seconds
Started Aug 07 05:18:45 PM PDT 24
Finished Aug 07 05:20:47 PM PDT 24
Peak memory 201420 kb
Host smart-8eb3a6c7-c43c-41f0-bce2-36a6de799c44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111395631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2111395631
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2687893426
Short name T720
Test name
Test status
Simulation time 519472475209 ps
CPU time 334.87 seconds
Started Aug 07 05:18:46 PM PDT 24
Finished Aug 07 05:24:21 PM PDT 24
Peak memory 201348 kb
Host smart-67355290-7afe-4162-a3c1-6583fcd92548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687893426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2687893426
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2925229569
Short name T186
Test name
Test status
Simulation time 492163655315 ps
CPU time 302.93 seconds
Started Aug 07 05:18:40 PM PDT 24
Finished Aug 07 05:23:43 PM PDT 24
Peak memory 201432 kb
Host smart-ecdb8158-27af-4cf1-a25e-22d348792d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925229569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2925229569
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4098535255
Short name T557
Test name
Test status
Simulation time 496331939838 ps
CPU time 310.62 seconds
Started Aug 07 05:19:02 PM PDT 24
Finished Aug 07 05:24:13 PM PDT 24
Peak memory 201432 kb
Host smart-d8fb3fcd-71a6-4aa4-8c02-7f0377e67d71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098535255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4098535255
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2103186281
Short name T490
Test name
Test status
Simulation time 327432847168 ps
CPU time 298.87 seconds
Started Aug 07 05:18:42 PM PDT 24
Finished Aug 07 05:23:41 PM PDT 24
Peak memory 201428 kb
Host smart-5401ed7c-6d1b-4cd0-8469-b380637800aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103186281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2103186281
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3885465066
Short name T157
Test name
Test status
Simulation time 167679443982 ps
CPU time 35.05 seconds
Started Aug 07 05:18:41 PM PDT 24
Finished Aug 07 05:19:16 PM PDT 24
Peak memory 201392 kb
Host smart-34890817-2d61-4608-a98d-58a916f56ca5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885465066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3885465066
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3890809423
Short name T607
Test name
Test status
Simulation time 248961690424 ps
CPU time 290.45 seconds
Started Aug 07 05:18:42 PM PDT 24
Finished Aug 07 05:23:32 PM PDT 24
Peak memory 201424 kb
Host smart-7a4b708e-3655-4ea5-bae9-effc11aa22a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890809423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3890809423
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2748274451
Short name T522
Test name
Test status
Simulation time 391176531646 ps
CPU time 289.39 seconds
Started Aug 07 05:18:43 PM PDT 24
Finished Aug 07 05:23:32 PM PDT 24
Peak memory 201428 kb
Host smart-9b46b3fa-eb48-4470-b70d-ab5829702f56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748274451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2748274451
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.498072033
Short name T225
Test name
Test status
Simulation time 125077701030 ps
CPU time 488.27 seconds
Started Aug 07 05:18:48 PM PDT 24
Finished Aug 07 05:26:56 PM PDT 24
Peak memory 201860 kb
Host smart-ed94469f-e178-4654-a162-78bb927f93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498072033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.498072033
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3085577401
Short name T406
Test name
Test status
Simulation time 24908181078 ps
CPU time 58.53 seconds
Started Aug 07 05:18:47 PM PDT 24
Finished Aug 07 05:19:45 PM PDT 24
Peak memory 201308 kb
Host smart-380668a1-8ac4-435d-9fe8-87de796633ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085577401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3085577401
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3000446815
Short name T665
Test name
Test status
Simulation time 2789907355 ps
CPU time 7.17 seconds
Started Aug 07 05:18:46 PM PDT 24
Finished Aug 07 05:18:54 PM PDT 24
Peak memory 201300 kb
Host smart-205dc224-0114-4e37-a846-8e3f85395216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000446815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3000446815
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4089056582
Short name T594
Test name
Test status
Simulation time 6007210712 ps
CPU time 12.25 seconds
Started Aug 07 05:18:41 PM PDT 24
Finished Aug 07 05:18:54 PM PDT 24
Peak memory 201284 kb
Host smart-569f3a05-6c1f-438d-a161-a9e139c9be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089056582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4089056582
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2360740677
Short name T432
Test name
Test status
Simulation time 285219935 ps
CPU time 1.27 seconds
Started Aug 07 05:19:19 PM PDT 24
Finished Aug 07 05:19:20 PM PDT 24
Peak memory 201208 kb
Host smart-ad3997bc-376f-4df0-a48b-ee5813b5cf6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360740677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2360740677
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3080915703
Short name T343
Test name
Test status
Simulation time 174099656000 ps
CPU time 101.48 seconds
Started Aug 07 05:19:11 PM PDT 24
Finished Aug 07 05:20:52 PM PDT 24
Peak memory 201420 kb
Host smart-fe9301a0-b909-49bc-a065-96e4b50a6188
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080915703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3080915703
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1066771914
Short name T623
Test name
Test status
Simulation time 161341532683 ps
CPU time 104.28 seconds
Started Aug 07 05:19:10 PM PDT 24
Finished Aug 07 05:20:55 PM PDT 24
Peak memory 201392 kb
Host smart-26d937c9-08c5-4b9f-8a47-1e5d2c88d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066771914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1066771914
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.320182647
Short name T466
Test name
Test status
Simulation time 163833997607 ps
CPU time 326.35 seconds
Started Aug 07 05:18:59 PM PDT 24
Finished Aug 07 05:24:25 PM PDT 24
Peak memory 201416 kb
Host smart-2bd5f363-e5da-43a2-a9e3-f7d9f01aa80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320182647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.320182647
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2758855530
Short name T377
Test name
Test status
Simulation time 495586593186 ps
CPU time 1146.52 seconds
Started Aug 07 05:18:59 PM PDT 24
Finished Aug 07 05:38:06 PM PDT 24
Peak memory 201416 kb
Host smart-de3d7d7d-92e8-46de-a42a-099810fc1895
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758855530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2758855530
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1659471648
Short name T173
Test name
Test status
Simulation time 164656562616 ps
CPU time 354.58 seconds
Started Aug 07 05:18:52 PM PDT 24
Finished Aug 07 05:24:47 PM PDT 24
Peak memory 201372 kb
Host smart-5e7c71ec-6954-4db9-afee-524122370254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659471648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1659471648
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.253967383
Short name T434
Test name
Test status
Simulation time 169384305982 ps
CPU time 412.76 seconds
Started Aug 07 05:18:52 PM PDT 24
Finished Aug 07 05:25:45 PM PDT 24
Peak memory 201448 kb
Host smart-18011e86-9911-4ee8-95fc-8e85b246a42d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=253967383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.253967383
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2636193174
Short name T712
Test name
Test status
Simulation time 347255757238 ps
CPU time 786.86 seconds
Started Aug 07 05:18:59 PM PDT 24
Finished Aug 07 05:32:06 PM PDT 24
Peak memory 201316 kb
Host smart-aa3eee39-40a6-4f26-88d0-6f1785f45bc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636193174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2636193174
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3131050789
Short name T741
Test name
Test status
Simulation time 398670218764 ps
CPU time 794.49 seconds
Started Aug 07 05:19:05 PM PDT 24
Finished Aug 07 05:32:19 PM PDT 24
Peak memory 201324 kb
Host smart-58ed6f4b-e691-487f-8e20-f549ccb23b4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131050789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3131050789
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2586123921
Short name T722
Test name
Test status
Simulation time 76675730352 ps
CPU time 276.82 seconds
Started Aug 07 05:19:11 PM PDT 24
Finished Aug 07 05:23:48 PM PDT 24
Peak memory 201840 kb
Host smart-888812e4-0de1-4b62-a94c-36e12ef9eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586123921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2586123921
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3823483568
Short name T401
Test name
Test status
Simulation time 45022895745 ps
CPU time 54.81 seconds
Started Aug 07 05:19:11 PM PDT 24
Finished Aug 07 05:20:06 PM PDT 24
Peak memory 201320 kb
Host smart-24893e75-33d5-45fe-b1ab-5df301c25630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823483568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3823483568
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2559020218
Short name T694
Test name
Test status
Simulation time 5078720244 ps
CPU time 6.6 seconds
Started Aug 07 05:19:13 PM PDT 24
Finished Aug 07 05:19:20 PM PDT 24
Peak memory 201284 kb
Host smart-e834e5bb-c194-4fe6-8821-b56ac06f6246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559020218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2559020218
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1151682129
Short name T447
Test name
Test status
Simulation time 6020377652 ps
CPU time 7.99 seconds
Started Aug 07 05:18:55 PM PDT 24
Finished Aug 07 05:19:03 PM PDT 24
Peak memory 201304 kb
Host smart-35d93d2d-609f-4106-8d53-83f24d510ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151682129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1151682129
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1525144698
Short name T373
Test name
Test status
Simulation time 416989489 ps
CPU time 0.71 seconds
Started Aug 07 05:19:35 PM PDT 24
Finished Aug 07 05:19:36 PM PDT 24
Peak memory 201192 kb
Host smart-48cccfda-1d14-4542-a1c3-912710fc1407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525144698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1525144698
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3269277618
Short name T419
Test name
Test status
Simulation time 330589083590 ps
CPU time 394.54 seconds
Started Aug 07 05:19:24 PM PDT 24
Finished Aug 07 05:25:58 PM PDT 24
Peak memory 201364 kb
Host smart-ba2f261b-3453-4915-942e-6d9f3f34e0be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269277618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3269277618
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1333396049
Short name T305
Test name
Test status
Simulation time 497048198026 ps
CPU time 585.93 seconds
Started Aug 07 05:19:16 PM PDT 24
Finished Aug 07 05:29:03 PM PDT 24
Peak memory 201364 kb
Host smart-9f0133cb-aa0a-470e-9e1a-d1f3b596526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333396049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1333396049
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3076562895
Short name T658
Test name
Test status
Simulation time 491039731622 ps
CPU time 562.04 seconds
Started Aug 07 05:19:24 PM PDT 24
Finished Aug 07 05:28:46 PM PDT 24
Peak memory 201356 kb
Host smart-3905e81a-3ef0-4e33-bd95-487951e9ef1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076562895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3076562895
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2083734897
Short name T469
Test name
Test status
Simulation time 607931823071 ps
CPU time 1300.06 seconds
Started Aug 07 05:19:28 PM PDT 24
Finished Aug 07 05:41:09 PM PDT 24
Peak memory 201460 kb
Host smart-84f46767-153a-4d3d-9a2c-c30a8ec904fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083734897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2083734897
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1977085617
Short name T586
Test name
Test status
Simulation time 105850780190 ps
CPU time 411.98 seconds
Started Aug 07 05:19:28 PM PDT 24
Finished Aug 07 05:26:20 PM PDT 24
Peak memory 201792 kb
Host smart-34ce9b2e-1730-4e79-a354-5e0720330a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977085617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1977085617
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1795337572
Short name T717
Test name
Test status
Simulation time 26808362199 ps
CPU time 5.13 seconds
Started Aug 07 05:19:30 PM PDT 24
Finished Aug 07 05:19:35 PM PDT 24
Peak memory 201284 kb
Host smart-d2378035-a5c8-41ae-920d-8ff7e701708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795337572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1795337572
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.130574128
Short name T382
Test name
Test status
Simulation time 3509575121 ps
CPU time 4.5 seconds
Started Aug 07 05:19:28 PM PDT 24
Finished Aug 07 05:19:32 PM PDT 24
Peak memory 201312 kb
Host smart-9382fcc8-c206-4267-8bf3-8696a5bbacb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130574128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.130574128
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3227899333
Short name T587
Test name
Test status
Simulation time 5661503376 ps
CPU time 2.16 seconds
Started Aug 07 05:19:16 PM PDT 24
Finished Aug 07 05:19:19 PM PDT 24
Peak memory 201276 kb
Host smart-60053fc4-cd79-4256-a876-eb6acbec30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227899333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3227899333
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.165749604
Short name T298
Test name
Test status
Simulation time 496539455890 ps
CPU time 232.5 seconds
Started Aug 07 05:19:34 PM PDT 24
Finished Aug 07 05:23:26 PM PDT 24
Peak memory 201332 kb
Host smart-4a06b016-a3b2-4723-bf79-27210914a491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165749604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
165749604
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3637166489
Short name T20
Test name
Test status
Simulation time 62301575529 ps
CPU time 220.66 seconds
Started Aug 07 05:19:34 PM PDT 24
Finished Aug 07 05:23:15 PM PDT 24
Peak memory 218100 kb
Host smart-795f3ab0-031c-4506-be81-07907f81b54f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637166489 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3637166489
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2245494433
Short name T421
Test name
Test status
Simulation time 465095114 ps
CPU time 0.85 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:13:08 PM PDT 24
Peak memory 201196 kb
Host smart-df6a92be-53aa-471f-b041-4fdba6758a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245494433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2245494433
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3322341682
Short name T59
Test name
Test status
Simulation time 185951375191 ps
CPU time 107.75 seconds
Started Aug 07 05:13:08 PM PDT 24
Finished Aug 07 05:14:56 PM PDT 24
Peak memory 201396 kb
Host smart-44bc32c8-ed3c-43ef-b837-95dd671ce55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322341682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3322341682
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3262390403
Short name T517
Test name
Test status
Simulation time 497821699580 ps
CPU time 603.28 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:23:10 PM PDT 24
Peak memory 201392 kb
Host smart-9ce10956-d943-4bfe-9b82-931734bb56b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262390403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3262390403
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3085888687
Short name T195
Test name
Test status
Simulation time 321604175201 ps
CPU time 131.72 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:15:18 PM PDT 24
Peak memory 201412 kb
Host smart-3a1f2fc4-f83b-44c0-81d3-7092bde20da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085888687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3085888687
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3523050422
Short name T390
Test name
Test status
Simulation time 166022706868 ps
CPU time 395.64 seconds
Started Aug 07 05:13:04 PM PDT 24
Finished Aug 07 05:19:40 PM PDT 24
Peak memory 201388 kb
Host smart-348dbd5d-d58d-423d-94e0-8b390692c096
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523050422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3523050422
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1419228661
Short name T715
Test name
Test status
Simulation time 615904940776 ps
CPU time 1416.45 seconds
Started Aug 07 05:13:08 PM PDT 24
Finished Aug 07 05:36:44 PM PDT 24
Peak memory 201380 kb
Host smart-8f4ea738-82b1-4960-8827-3b9fce86a0cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419228661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1419228661
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.939948247
Short name T513
Test name
Test status
Simulation time 24057632212 ps
CPU time 57.64 seconds
Started Aug 07 05:13:09 PM PDT 24
Finished Aug 07 05:14:06 PM PDT 24
Peak memory 201296 kb
Host smart-3a0f9b5a-caee-4b07-acb1-6f965de70b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939948247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.939948247
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2159847798
Short name T150
Test name
Test status
Simulation time 3254281196 ps
CPU time 2.52 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:13:09 PM PDT 24
Peak memory 201328 kb
Host smart-3252f483-405b-474e-b14c-84618fd33191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159847798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2159847798
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3268833606
Short name T90
Test name
Test status
Simulation time 8902517284 ps
CPU time 2.4 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:13:09 PM PDT 24
Peak memory 217780 kb
Host smart-5d1bb246-d5c3-419f-8d24-9eb083063d1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268833606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3268833606
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3010953170
Short name T385
Test name
Test status
Simulation time 5847949698 ps
CPU time 14.19 seconds
Started Aug 07 05:13:09 PM PDT 24
Finished Aug 07 05:13:23 PM PDT 24
Peak memory 201252 kb
Host smart-4bb1bb37-39aa-48a9-8f59-fbabd1ce5d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010953170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3010953170
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2827684852
Short name T792
Test name
Test status
Simulation time 1214277251 ps
CPU time 3.24 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:13:10 PM PDT 24
Peak memory 201108 kb
Host smart-1ce727ce-df7f-4889-a796-37f799659937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827684852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2827684852
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2815715360
Short name T50
Test name
Test status
Simulation time 243394758524 ps
CPU time 127.89 seconds
Started Aug 07 05:13:07 PM PDT 24
Finished Aug 07 05:15:15 PM PDT 24
Peak memory 209720 kb
Host smart-f3c65407-c702-4d90-a4fe-8a80c62cead1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815715360 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2815715360
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2976500242
Short name T567
Test name
Test status
Simulation time 372561192 ps
CPU time 0.83 seconds
Started Aug 07 05:19:53 PM PDT 24
Finished Aug 07 05:19:53 PM PDT 24
Peak memory 201208 kb
Host smart-a632bd74-4f41-486e-a481-5d9f4c6f83c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976500242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2976500242
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4006576329
Short name T255
Test name
Test status
Simulation time 529735271389 ps
CPU time 240.06 seconds
Started Aug 07 05:19:45 PM PDT 24
Finished Aug 07 05:23:45 PM PDT 24
Peak memory 201424 kb
Host smart-945f0cea-4bf3-45ff-b5f0-3436aec9072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006576329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4006576329
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3752632441
Short name T209
Test name
Test status
Simulation time 161208517840 ps
CPU time 53.93 seconds
Started Aug 07 05:19:41 PM PDT 24
Finished Aug 07 05:20:35 PM PDT 24
Peak memory 201448 kb
Host smart-7f7f2f72-fac8-4ce1-af8d-3bb0088d8dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752632441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3752632441
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3000194403
Short name T370
Test name
Test status
Simulation time 334061539391 ps
CPU time 187.71 seconds
Started Aug 07 05:19:40 PM PDT 24
Finished Aug 07 05:22:48 PM PDT 24
Peak memory 201412 kb
Host smart-d6321413-7ad5-47fb-9fcb-76abbaa6a371
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000194403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3000194403
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2433382059
Short name T35
Test name
Test status
Simulation time 484850235693 ps
CPU time 1109.07 seconds
Started Aug 07 05:19:36 PM PDT 24
Finished Aug 07 05:38:05 PM PDT 24
Peak memory 201412 kb
Host smart-0c602bea-9c71-4ef3-a2f5-51f9c52d3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433382059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2433382059
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2616510650
Short name T610
Test name
Test status
Simulation time 326161867886 ps
CPU time 807.36 seconds
Started Aug 07 05:19:44 PM PDT 24
Finished Aug 07 05:33:12 PM PDT 24
Peak memory 201364 kb
Host smart-9db29c41-2364-475b-8a1a-d0ec70fca2c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616510650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2616510650
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.925299843
Short name T192
Test name
Test status
Simulation time 582886251170 ps
CPU time 83.51 seconds
Started Aug 07 05:19:44 PM PDT 24
Finished Aug 07 05:21:08 PM PDT 24
Peak memory 201392 kb
Host smart-259264ec-a74e-4b0d-a319-1209571c6bfd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925299843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.925299843
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3100460559
Short name T117
Test name
Test status
Simulation time 410909799176 ps
CPU time 944.07 seconds
Started Aug 07 05:19:45 PM PDT 24
Finished Aug 07 05:35:30 PM PDT 24
Peak memory 201352 kb
Host smart-204da7cb-d975-4682-9e62-25eb0207777a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100460559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3100460559
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1047234918
Short name T550
Test name
Test status
Simulation time 126331871159 ps
CPU time 664.02 seconds
Started Aug 07 05:19:52 PM PDT 24
Finished Aug 07 05:30:56 PM PDT 24
Peak memory 201748 kb
Host smart-956bc71f-d3ba-49c6-90b8-d08e9b907e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047234918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1047234918
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1651734883
Short name T540
Test name
Test status
Simulation time 31729266347 ps
CPU time 69.57 seconds
Started Aug 07 05:19:52 PM PDT 24
Finished Aug 07 05:21:02 PM PDT 24
Peak memory 201296 kb
Host smart-d620f762-e16f-4464-862f-1217ec5f94f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651734883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1651734883
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1487974010
Short name T583
Test name
Test status
Simulation time 4211849747 ps
CPU time 3.26 seconds
Started Aug 07 05:19:46 PM PDT 24
Finished Aug 07 05:19:49 PM PDT 24
Peak memory 201268 kb
Host smart-acfcdd5a-b79d-4753-b6d2-055b86913a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487974010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1487974010
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2100544514
Short name T489
Test name
Test status
Simulation time 5611095711 ps
CPU time 6.6 seconds
Started Aug 07 05:19:35 PM PDT 24
Finished Aug 07 05:19:42 PM PDT 24
Peak memory 201304 kb
Host smart-27450e83-220c-4a8e-a52b-01b9e900637e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100544514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2100544514
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.497430361
Short name T18
Test name
Test status
Simulation time 522407873198 ps
CPU time 363.24 seconds
Started Aug 07 05:19:53 PM PDT 24
Finished Aug 07 05:25:57 PM PDT 24
Peak memory 217780 kb
Host smart-9ec0a48d-12e1-45e2-83ab-50036565e5a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497430361 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.497430361
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3517697580
Short name T627
Test name
Test status
Simulation time 450606759 ps
CPU time 0.87 seconds
Started Aug 07 05:20:14 PM PDT 24
Finished Aug 07 05:20:15 PM PDT 24
Peak memory 201148 kb
Host smart-2e438d05-4710-4eaa-90fb-582d5190c91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517697580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3517697580
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1847222951
Short name T335
Test name
Test status
Simulation time 176070770787 ps
CPU time 176.66 seconds
Started Aug 07 05:20:02 PM PDT 24
Finished Aug 07 05:22:59 PM PDT 24
Peak memory 201420 kb
Host smart-63270ff0-8a1c-4244-9738-65928e41a054
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847222951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1847222951
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.280161668
Short name T45
Test name
Test status
Simulation time 318902388557 ps
CPU time 765.82 seconds
Started Aug 07 05:19:57 PM PDT 24
Finished Aug 07 05:32:43 PM PDT 24
Peak memory 201412 kb
Host smart-bdec52a1-6863-49fe-b4f6-5fbb2d2a60dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280161668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.280161668
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2934861834
Short name T677
Test name
Test status
Simulation time 496144866089 ps
CPU time 287.23 seconds
Started Aug 07 05:20:03 PM PDT 24
Finished Aug 07 05:24:51 PM PDT 24
Peak memory 201452 kb
Host smart-a88ea525-c4c3-4234-ad15-4e579eb7c100
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934861834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2934861834
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.162665079
Short name T155
Test name
Test status
Simulation time 160417116793 ps
CPU time 357.57 seconds
Started Aug 07 05:19:57 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 201372 kb
Host smart-7dfc3118-eec8-4ed4-b4ad-04b932a47931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162665079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.162665079
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3283884451
Short name T189
Test name
Test status
Simulation time 489630020196 ps
CPU time 129.48 seconds
Started Aug 07 05:19:57 PM PDT 24
Finished Aug 07 05:22:07 PM PDT 24
Peak memory 201412 kb
Host smart-7175efdf-69c1-429e-b2e5-1adb614157ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283884451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3283884451
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2077556147
Short name T243
Test name
Test status
Simulation time 528240202007 ps
CPU time 1233.99 seconds
Started Aug 07 05:20:04 PM PDT 24
Finished Aug 07 05:40:38 PM PDT 24
Peak memory 201460 kb
Host smart-7e4b16d2-30d9-4534-a517-180892ffbefb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077556147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2077556147
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3806148440
Short name T590
Test name
Test status
Simulation time 399843956316 ps
CPU time 198.02 seconds
Started Aug 07 05:20:04 PM PDT 24
Finished Aug 07 05:23:22 PM PDT 24
Peak memory 201340 kb
Host smart-baa7126f-d69b-4ba1-93a8-cc706eb1bc66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806148440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3806148440
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.606878944
Short name T786
Test name
Test status
Simulation time 88864839784 ps
CPU time 488.86 seconds
Started Aug 07 05:20:08 PM PDT 24
Finished Aug 07 05:28:17 PM PDT 24
Peak memory 201800 kb
Host smart-f1e80189-c981-4609-894b-b7bb0bfb203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606878944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.606878944
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1596732065
Short name T505
Test name
Test status
Simulation time 23004214817 ps
CPU time 10.94 seconds
Started Aug 07 05:20:07 PM PDT 24
Finished Aug 07 05:20:18 PM PDT 24
Peak memory 201316 kb
Host smart-eea79c8d-2379-48d3-881b-19d60c4dc046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596732065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1596732065
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2063209565
Short name T358
Test name
Test status
Simulation time 5144332211 ps
CPU time 1.98 seconds
Started Aug 07 05:20:07 PM PDT 24
Finished Aug 07 05:20:10 PM PDT 24
Peak memory 201272 kb
Host smart-73a1faf5-da52-4b63-ba31-7d4acb5f394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063209565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2063209565
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.205354024
Short name T509
Test name
Test status
Simulation time 5469524796 ps
CPU time 11.65 seconds
Started Aug 07 05:19:56 PM PDT 24
Finished Aug 07 05:20:08 PM PDT 24
Peak memory 201308 kb
Host smart-8ca0f754-6f16-4c4c-8524-1957740efb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205354024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.205354024
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.559765994
Short name T350
Test name
Test status
Simulation time 258068268944 ps
CPU time 341.97 seconds
Started Aug 07 05:20:17 PM PDT 24
Finished Aug 07 05:25:59 PM PDT 24
Peak memory 218188 kb
Host smart-a823dd6c-e4ee-406d-888a-9a91ba4ac7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559765994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
559765994
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3808189510
Short name T53
Test name
Test status
Simulation time 135339330954 ps
CPU time 202.37 seconds
Started Aug 07 05:20:08 PM PDT 24
Finished Aug 07 05:23:31 PM PDT 24
Peak memory 210204 kb
Host smart-1c2b776d-aec1-47bf-9ed7-56d788251159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808189510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3808189510
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1126457819
Short name T783
Test name
Test status
Simulation time 465635203 ps
CPU time 1.66 seconds
Started Aug 07 05:20:33 PM PDT 24
Finished Aug 07 05:20:35 PM PDT 24
Peak memory 201180 kb
Host smart-2e4dc0ed-d1e0-4bda-8772-73adaf8ebcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126457819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1126457819
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2486390638
Short name T769
Test name
Test status
Simulation time 508401395496 ps
CPU time 213.83 seconds
Started Aug 07 05:20:29 PM PDT 24
Finished Aug 07 05:24:03 PM PDT 24
Peak memory 201416 kb
Host smart-b7e6bad0-7797-45c1-a7d9-5122746579b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486390638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2486390638
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1238098810
Short name T572
Test name
Test status
Simulation time 175616725797 ps
CPU time 73.38 seconds
Started Aug 07 05:20:29 PM PDT 24
Finished Aug 07 05:21:43 PM PDT 24
Peak memory 201360 kb
Host smart-236734a3-28f9-4242-b523-a29facc3affb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238098810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1238098810
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1823247104
Short name T312
Test name
Test status
Simulation time 483759135074 ps
CPU time 1109.44 seconds
Started Aug 07 05:20:19 PM PDT 24
Finished Aug 07 05:38:49 PM PDT 24
Peak memory 201452 kb
Host smart-be9f17bc-ae33-4855-accc-c255e03e5313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823247104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1823247104
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.90842382
Short name T425
Test name
Test status
Simulation time 324447668983 ps
CPU time 200.53 seconds
Started Aug 07 05:20:21 PM PDT 24
Finished Aug 07 05:23:42 PM PDT 24
Peak memory 201436 kb
Host smart-2b42b28c-118a-4875-93d4-075675b8aad1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=90842382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt
_fixed.90842382
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4156835556
Short name T290
Test name
Test status
Simulation time 490515109782 ps
CPU time 524.46 seconds
Started Aug 07 05:20:22 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 201384 kb
Host smart-10917b83-b472-44c9-8fc7-4a636c68ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156835556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4156835556
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3286312034
Short name T369
Test name
Test status
Simulation time 335373986503 ps
CPU time 727.74 seconds
Started Aug 07 05:20:20 PM PDT 24
Finished Aug 07 05:32:28 PM PDT 24
Peak memory 201432 kb
Host smart-6058c029-3183-4a73-b1cd-d731295014be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286312034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3286312034
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1359226164
Short name T213
Test name
Test status
Simulation time 384192476284 ps
CPU time 231.7 seconds
Started Aug 07 05:20:20 PM PDT 24
Finished Aug 07 05:24:12 PM PDT 24
Peak memory 201452 kb
Host smart-47def282-f2e9-4108-9cce-b2b2cc5258ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359226164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1359226164
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3161700466
Short name T727
Test name
Test status
Simulation time 587923157541 ps
CPU time 1226.69 seconds
Started Aug 07 05:20:20 PM PDT 24
Finished Aug 07 05:40:46 PM PDT 24
Peak memory 201436 kb
Host smart-fa5664c2-59b2-49d7-9c74-5685e60dcab4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161700466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3161700466
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3579473215
Short name T534
Test name
Test status
Simulation time 94124638480 ps
CPU time 265.49 seconds
Started Aug 07 05:20:26 PM PDT 24
Finished Aug 07 05:24:52 PM PDT 24
Peak memory 201856 kb
Host smart-1d187f4f-8396-44ae-a0e5-d646726ef87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579473215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3579473215
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4139430943
Short name T630
Test name
Test status
Simulation time 41468789535 ps
CPU time 25.75 seconds
Started Aug 07 05:20:29 PM PDT 24
Finished Aug 07 05:20:55 PM PDT 24
Peak memory 201284 kb
Host smart-8592eabb-1b32-4d3e-b63e-dd2ef92bcc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139430943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4139430943
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.919510206
Short name T497
Test name
Test status
Simulation time 4564456593 ps
CPU time 6.03 seconds
Started Aug 07 05:20:28 PM PDT 24
Finished Aug 07 05:20:34 PM PDT 24
Peak memory 201256 kb
Host smart-40221d36-7712-4d89-a963-e77d5a490899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919510206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.919510206
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.74409247
Short name T743
Test name
Test status
Simulation time 5550453535 ps
CPU time 3.53 seconds
Started Aug 07 05:20:15 PM PDT 24
Finished Aug 07 05:20:19 PM PDT 24
Peak memory 201316 kb
Host smart-c5f19bc4-ffb4-444c-bb59-bc8a1cc8a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74409247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.74409247
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2766966263
Short name T106
Test name
Test status
Simulation time 406495665 ps
CPU time 1.05 seconds
Started Aug 07 05:20:48 PM PDT 24
Finished Aug 07 05:20:50 PM PDT 24
Peak memory 201180 kb
Host smart-ebc43fac-9a32-4cf5-bf73-742b0f06f9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766966263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2766966263
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4023671339
Short name T125
Test name
Test status
Simulation time 328309981253 ps
CPU time 640.74 seconds
Started Aug 07 05:20:45 PM PDT 24
Finished Aug 07 05:31:25 PM PDT 24
Peak memory 201460 kb
Host smart-f7c6448d-03bd-470c-816f-ccfe549ffabb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023671339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4023671339
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2828907471
Short name T179
Test name
Test status
Simulation time 392416556341 ps
CPU time 850.32 seconds
Started Aug 07 05:20:43 PM PDT 24
Finished Aug 07 05:34:54 PM PDT 24
Peak memory 201400 kb
Host smart-7472296a-0971-4073-864f-f3f9168cb8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828907471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2828907471
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3749218970
Short name T634
Test name
Test status
Simulation time 337762436053 ps
CPU time 416.47 seconds
Started Aug 07 05:20:39 PM PDT 24
Finished Aug 07 05:27:36 PM PDT 24
Peak memory 201368 kb
Host smart-60195488-9d30-416a-8016-a508e6c065d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749218970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3749218970
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.897409647
Short name T423
Test name
Test status
Simulation time 330052780132 ps
CPU time 83.52 seconds
Started Aug 07 05:20:38 PM PDT 24
Finished Aug 07 05:22:01 PM PDT 24
Peak memory 201456 kb
Host smart-f6431570-6aa3-4b7b-bc86-6859803e3c03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=897409647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.897409647
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1927432446
Short name T152
Test name
Test status
Simulation time 496712640137 ps
CPU time 178.86 seconds
Started Aug 07 05:20:39 PM PDT 24
Finished Aug 07 05:23:38 PM PDT 24
Peak memory 201368 kb
Host smart-7bfaf73c-1032-418d-97e6-e55d941588ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927432446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1927432446
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.943095596
Short name T414
Test name
Test status
Simulation time 326463011891 ps
CPU time 729.42 seconds
Started Aug 07 05:20:39 PM PDT 24
Finished Aug 07 05:32:48 PM PDT 24
Peak memory 201352 kb
Host smart-b64a4450-4daa-4746-bed8-e5e984cdd9f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943095596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.943095596
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1344498851
Short name T757
Test name
Test status
Simulation time 509212327783 ps
CPU time 168.76 seconds
Started Aug 07 05:20:45 PM PDT 24
Finished Aug 07 05:23:34 PM PDT 24
Peak memory 201316 kb
Host smart-da8a1328-6608-4162-91cf-d8daf8d34f85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344498851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1344498851
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.902440427
Short name T219
Test name
Test status
Simulation time 197291958679 ps
CPU time 127.51 seconds
Started Aug 07 05:20:42 PM PDT 24
Finished Aug 07 05:22:50 PM PDT 24
Peak memory 201424 kb
Host smart-6130c6d1-119a-426b-90b6-8dfd8cd1c86b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902440427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.902440427
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1991577181
Short name T698
Test name
Test status
Simulation time 87089737990 ps
CPU time 459.2 seconds
Started Aug 07 05:20:44 PM PDT 24
Finished Aug 07 05:28:23 PM PDT 24
Peak memory 201768 kb
Host smart-68ae69b2-417e-414b-85d0-1d837de39c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991577181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1991577181
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2705361734
Short name T499
Test name
Test status
Simulation time 27250876048 ps
CPU time 32.25 seconds
Started Aug 07 05:20:43 PM PDT 24
Finished Aug 07 05:21:16 PM PDT 24
Peak memory 201308 kb
Host smart-2f0229c1-a62c-4428-91ac-6899e4eaf09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705361734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2705361734
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1339746835
Short name T54
Test name
Test status
Simulation time 2944927849 ps
CPU time 3.97 seconds
Started Aug 07 05:20:44 PM PDT 24
Finished Aug 07 05:20:48 PM PDT 24
Peak memory 201308 kb
Host smart-732e68c2-bab1-476d-bff8-4039ea8e6375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339746835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1339746835
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4217641328
Short name T47
Test name
Test status
Simulation time 6008329153 ps
CPU time 4.5 seconds
Started Aug 07 05:20:33 PM PDT 24
Finished Aug 07 05:20:37 PM PDT 24
Peak memory 201276 kb
Host smart-09c69156-c597-415e-9fad-37db7099a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217641328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4217641328
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3916532921
Short name T493
Test name
Test status
Simulation time 211666515464 ps
CPU time 442.01 seconds
Started Aug 07 05:20:44 PM PDT 24
Finished Aug 07 05:28:07 PM PDT 24
Peak memory 201364 kb
Host smart-2cea8eb5-8e8d-4948-a58f-f2ab6e6676ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916532921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3916532921
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3427353996
Short name T22
Test name
Test status
Simulation time 23980235994 ps
CPU time 53.32 seconds
Started Aug 07 05:20:44 PM PDT 24
Finished Aug 07 05:21:38 PM PDT 24
Peak memory 201516 kb
Host smart-105ee20c-d6ac-4d9c-b571-bbe53d0d860b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427353996 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3427353996
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.90014413
Short name T34
Test name
Test status
Simulation time 467917253 ps
CPU time 0.87 seconds
Started Aug 07 05:21:19 PM PDT 24
Finished Aug 07 05:21:19 PM PDT 24
Peak memory 201184 kb
Host smart-846a7fcd-0f09-45e6-b305-5dd9319ff110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90014413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.90014413
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2172047658
Short name T733
Test name
Test status
Simulation time 343664931335 ps
CPU time 198.35 seconds
Started Aug 07 05:20:57 PM PDT 24
Finished Aug 07 05:24:16 PM PDT 24
Peak memory 201424 kb
Host smart-9f5c3e08-5197-49c1-8fc7-13ecd613d148
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172047658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2172047658
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3105917351
Short name T495
Test name
Test status
Simulation time 552493427036 ps
CPU time 1153.35 seconds
Started Aug 07 05:21:06 PM PDT 24
Finished Aug 07 05:40:20 PM PDT 24
Peak memory 201376 kb
Host smart-f8ec471f-db3d-49ba-86be-f7ec51ac904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105917351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3105917351
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1135957663
Short name T275
Test name
Test status
Simulation time 164005023440 ps
CPU time 400.78 seconds
Started Aug 07 05:20:53 PM PDT 24
Finished Aug 07 05:27:34 PM PDT 24
Peak memory 201420 kb
Host smart-7fc14db1-2820-4544-8601-fdf0651ea71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135957663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1135957663
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1807020639
Short name T362
Test name
Test status
Simulation time 335371090326 ps
CPU time 682.41 seconds
Started Aug 07 05:20:53 PM PDT 24
Finished Aug 07 05:32:16 PM PDT 24
Peak memory 201436 kb
Host smart-cbf1ecf8-b580-471c-b347-d938049564cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807020639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1807020639
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2094236717
Short name T244
Test name
Test status
Simulation time 328068894774 ps
CPU time 723.42 seconds
Started Aug 07 05:20:48 PM PDT 24
Finished Aug 07 05:32:52 PM PDT 24
Peak memory 201464 kb
Host smart-372ab857-fae7-4949-94c0-c64ec47641fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094236717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2094236717
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.69187580
Short name T32
Test name
Test status
Simulation time 164555300893 ps
CPU time 185.73 seconds
Started Aug 07 05:20:52 PM PDT 24
Finished Aug 07 05:23:58 PM PDT 24
Peak memory 201324 kb
Host smart-00384719-16f9-45db-8b18-fa1c4c815aba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=69187580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed
.69187580
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.369271817
Short name T462
Test name
Test status
Simulation time 195083179525 ps
CPU time 430.61 seconds
Started Aug 07 05:21:05 PM PDT 24
Finished Aug 07 05:28:15 PM PDT 24
Peak memory 201380 kb
Host smart-4cc22cae-7c75-485e-a7d5-6f03aa82e897
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369271817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.369271817
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3190769684
Short name T609
Test name
Test status
Simulation time 63614062406 ps
CPU time 324.64 seconds
Started Aug 07 05:21:12 PM PDT 24
Finished Aug 07 05:26:37 PM PDT 24
Peak memory 201792 kb
Host smart-343ab806-06fc-44ac-8c51-2f5b9e859bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190769684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3190769684
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1834593737
Short name T662
Test name
Test status
Simulation time 45978936743 ps
CPU time 25.24 seconds
Started Aug 07 05:21:06 PM PDT 24
Finished Aug 07 05:21:31 PM PDT 24
Peak memory 201264 kb
Host smart-1ab9e0ed-8cc2-4a8c-986c-41c60cd50a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834593737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1834593737
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2158886368
Short name T686
Test name
Test status
Simulation time 4112351508 ps
CPU time 2.86 seconds
Started Aug 07 05:20:57 PM PDT 24
Finished Aug 07 05:21:00 PM PDT 24
Peak memory 201272 kb
Host smart-048c7eed-0124-443a-9a14-1fef6c1f8c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158886368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2158886368
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4088630154
Short name T420
Test name
Test status
Simulation time 5620922746 ps
CPU time 12.62 seconds
Started Aug 07 05:20:49 PM PDT 24
Finished Aug 07 05:21:02 PM PDT 24
Peak memory 201276 kb
Host smart-86f419e4-17de-414b-a709-6329c1a314fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088630154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4088630154
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2368032048
Short name T611
Test name
Test status
Simulation time 270744329921 ps
CPU time 567.59 seconds
Started Aug 07 05:21:11 PM PDT 24
Finished Aug 07 05:30:39 PM PDT 24
Peak memory 201732 kb
Host smart-47b010b6-c5f3-4346-9b75-8d9c0a7c202d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368032048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2368032048
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2538263448
Short name T349
Test name
Test status
Simulation time 31866606131 ps
CPU time 93.67 seconds
Started Aug 07 05:21:12 PM PDT 24
Finished Aug 07 05:22:46 PM PDT 24
Peak memory 211116 kb
Host smart-36f1c3a8-10ac-4a9d-bd4e-ca8bbc8aca5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538263448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2538263448
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2364584688
Short name T498
Test name
Test status
Simulation time 376824988 ps
CPU time 0.85 seconds
Started Aug 07 05:21:35 PM PDT 24
Finished Aug 07 05:21:36 PM PDT 24
Peak memory 201140 kb
Host smart-421e554c-74fc-4a9f-9bb1-abc7501000ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364584688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2364584688
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1678734060
Short name T682
Test name
Test status
Simulation time 194510221535 ps
CPU time 241.09 seconds
Started Aug 07 05:21:28 PM PDT 24
Finished Aug 07 05:25:29 PM PDT 24
Peak memory 201432 kb
Host smart-40f03732-2206-41b0-9f3e-1a73d5e04d75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678734060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1678734060
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3453464787
Short name T307
Test name
Test status
Simulation time 159643575343 ps
CPU time 96.05 seconds
Started Aug 07 05:21:19 PM PDT 24
Finished Aug 07 05:22:55 PM PDT 24
Peak memory 201412 kb
Host smart-94df5699-2ba4-4ea5-970e-1f33d072126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453464787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3453464787
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4153406046
Short name T729
Test name
Test status
Simulation time 332618280566 ps
CPU time 728.34 seconds
Started Aug 07 05:21:19 PM PDT 24
Finished Aug 07 05:33:27 PM PDT 24
Peak memory 201432 kb
Host smart-633ffeb9-f840-499e-9307-619abc6870ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153406046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4153406046
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1440749185
Short name T565
Test name
Test status
Simulation time 164755438038 ps
CPU time 368.87 seconds
Started Aug 07 05:21:20 PM PDT 24
Finished Aug 07 05:27:29 PM PDT 24
Peak memory 201352 kb
Host smart-0e8520cb-1282-4a0a-8b5b-a456ecf991f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440749185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1440749185
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.223619626
Short name T10
Test name
Test status
Simulation time 492061834016 ps
CPU time 1066.02 seconds
Started Aug 07 05:21:19 PM PDT 24
Finished Aug 07 05:39:05 PM PDT 24
Peak memory 201368 kb
Host smart-cf697092-158c-4186-8110-e91cf549db37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=223619626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.223619626
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1873322582
Short name T113
Test name
Test status
Simulation time 586421990024 ps
CPU time 106.51 seconds
Started Aug 07 05:21:26 PM PDT 24
Finished Aug 07 05:23:13 PM PDT 24
Peak memory 201348 kb
Host smart-1a64e002-a3e5-4524-a625-01e23939be76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873322582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1873322582
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2198578727
Short name T749
Test name
Test status
Simulation time 199064371115 ps
CPU time 113.17 seconds
Started Aug 07 05:21:24 PM PDT 24
Finished Aug 07 05:23:18 PM PDT 24
Peak memory 201432 kb
Host smart-9b024ddc-897b-447c-bbd9-2c6450c6a55a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198578727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2198578727
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.843203920
Short name T230
Test name
Test status
Simulation time 97047340125 ps
CPU time 303.08 seconds
Started Aug 07 05:21:27 PM PDT 24
Finished Aug 07 05:26:30 PM PDT 24
Peak memory 201752 kb
Host smart-c059a441-8181-4897-a74e-989d0b24914b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843203920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.843203920
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.127967619
Short name T684
Test name
Test status
Simulation time 45154523951 ps
CPU time 28.58 seconds
Started Aug 07 05:21:26 PM PDT 24
Finished Aug 07 05:21:55 PM PDT 24
Peak memory 201304 kb
Host smart-91c03ed9-35a7-49ce-a9b4-e44318dd6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127967619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.127967619
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2643583769
Short name T389
Test name
Test status
Simulation time 4117854242 ps
CPU time 2.7 seconds
Started Aug 07 05:21:26 PM PDT 24
Finished Aug 07 05:21:29 PM PDT 24
Peak memory 201308 kb
Host smart-6e037748-c745-47b6-8675-279fb815e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643583769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2643583769
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.798189275
Short name T486
Test name
Test status
Simulation time 6041658128 ps
CPU time 3.18 seconds
Started Aug 07 05:21:20 PM PDT 24
Finished Aug 07 05:21:24 PM PDT 24
Peak memory 201320 kb
Host smart-9574e607-b6da-45b5-9e72-26935dd861fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798189275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.798189275
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1665793168
Short name T703
Test name
Test status
Simulation time 82866318170 ps
CPU time 38.73 seconds
Started Aug 07 05:21:27 PM PDT 24
Finished Aug 07 05:22:06 PM PDT 24
Peak memory 209748 kb
Host smart-4ec05c3c-6e2e-4514-a939-846bc9582501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665793168 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1665793168
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2682514918
Short name T751
Test name
Test status
Simulation time 439523449 ps
CPU time 1.12 seconds
Started Aug 07 05:21:44 PM PDT 24
Finished Aug 07 05:21:46 PM PDT 24
Peak memory 201240 kb
Host smart-9a7a1720-197b-4c49-ab1b-20ac6e82bde8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682514918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2682514918
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4203640209
Short name T746
Test name
Test status
Simulation time 163988254598 ps
CPU time 248.67 seconds
Started Aug 07 05:21:39 PM PDT 24
Finished Aug 07 05:25:47 PM PDT 24
Peak memory 201380 kb
Host smart-c48cb424-e6e4-41e3-acea-ee1197404420
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203640209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4203640209
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1673478020
Short name T162
Test name
Test status
Simulation time 166371029130 ps
CPU time 367.41 seconds
Started Aug 07 05:21:34 PM PDT 24
Finished Aug 07 05:27:41 PM PDT 24
Peak memory 201384 kb
Host smart-51065f19-05a3-4f9e-b70e-ad69f742a557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673478020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1673478020
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4276109472
Short name T459
Test name
Test status
Simulation time 162649142878 ps
CPU time 368.94 seconds
Started Aug 07 05:21:39 PM PDT 24
Finished Aug 07 05:27:48 PM PDT 24
Peak memory 201432 kb
Host smart-077aba4e-a681-40d8-b80c-161e34a9812d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276109472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4276109472
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2412883978
Short name T508
Test name
Test status
Simulation time 493229736949 ps
CPU time 535.82 seconds
Started Aug 07 05:21:35 PM PDT 24
Finished Aug 07 05:30:31 PM PDT 24
Peak memory 201436 kb
Host smart-5dc22910-c567-4e9c-b0a5-88dd6d8fb73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412883978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2412883978
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.646069278
Short name T755
Test name
Test status
Simulation time 163891655457 ps
CPU time 91.59 seconds
Started Aug 07 05:21:33 PM PDT 24
Finished Aug 07 05:23:04 PM PDT 24
Peak memory 201316 kb
Host smart-d8cd5432-9de8-4497-8922-dfe1609a920d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646069278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.646069278
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.471020126
Short name T701
Test name
Test status
Simulation time 557922180613 ps
CPU time 674.71 seconds
Started Aug 07 05:21:39 PM PDT 24
Finished Aug 07 05:32:54 PM PDT 24
Peak memory 201376 kb
Host smart-e74c0920-0509-424e-9039-2562ebe29c03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471020126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.471020126
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2793239335
Short name T463
Test name
Test status
Simulation time 596070684444 ps
CPU time 362.12 seconds
Started Aug 07 05:21:38 PM PDT 24
Finished Aug 07 05:27:40 PM PDT 24
Peak memory 201432 kb
Host smart-f4562161-b8a9-4201-b03f-078a844d6180
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793239335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2793239335
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3977998168
Short name T530
Test name
Test status
Simulation time 107254600244 ps
CPU time 385.49 seconds
Started Aug 07 05:21:44 PM PDT 24
Finished Aug 07 05:28:10 PM PDT 24
Peak memory 201760 kb
Host smart-c40caf00-7a31-4548-bd86-8b036f1b4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977998168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3977998168
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3242795469
Short name T526
Test name
Test status
Simulation time 23964606668 ps
CPU time 25.56 seconds
Started Aug 07 05:21:40 PM PDT 24
Finished Aug 07 05:22:06 PM PDT 24
Peak memory 201264 kb
Host smart-9366d173-f568-4743-86fc-969c2281b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242795469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3242795469
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1863877916
Short name T395
Test name
Test status
Simulation time 4457954510 ps
CPU time 3.28 seconds
Started Aug 07 05:21:39 PM PDT 24
Finished Aug 07 05:21:43 PM PDT 24
Peak memory 201316 kb
Host smart-06408832-fa1f-45fd-80f1-e6815a1680ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863877916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1863877916
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2084288793
Short name T601
Test name
Test status
Simulation time 5750605656 ps
CPU time 3.74 seconds
Started Aug 07 05:21:34 PM PDT 24
Finished Aug 07 05:21:38 PM PDT 24
Peak memory 201308 kb
Host smart-16ff5a99-e27c-4bc0-bda4-5b94db80d29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084288793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2084288793
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2738518914
Short name T767
Test name
Test status
Simulation time 242260205666 ps
CPU time 796.83 seconds
Started Aug 07 05:21:46 PM PDT 24
Finished Aug 07 05:35:03 PM PDT 24
Peak memory 201832 kb
Host smart-ddbc787e-d825-4e4d-8d10-67788aa96afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738518914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2738518914
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3321642914
Short name T21
Test name
Test status
Simulation time 7450995037 ps
CPU time 20.01 seconds
Started Aug 07 05:21:45 PM PDT 24
Finished Aug 07 05:22:05 PM PDT 24
Peak memory 210108 kb
Host smart-aef019c5-048b-4d57-b58d-363cbbed1af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321642914 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3321642914
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1368311158
Short name T407
Test name
Test status
Simulation time 389986657 ps
CPU time 0.85 seconds
Started Aug 07 05:22:08 PM PDT 24
Finished Aug 07 05:22:09 PM PDT 24
Peak memory 201212 kb
Host smart-03aeee65-83c6-4f23-bd94-c172ad9d7329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368311158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1368311158
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4020225193
Short name T494
Test name
Test status
Simulation time 160015548835 ps
CPU time 96.36 seconds
Started Aug 07 05:21:55 PM PDT 24
Finished Aug 07 05:23:31 PM PDT 24
Peak memory 201328 kb
Host smart-d778ea1c-faee-4280-b19d-fb79c0b5daae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020225193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4020225193
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1313414096
Short name T218
Test name
Test status
Simulation time 499214791870 ps
CPU time 294.29 seconds
Started Aug 07 05:24:06 PM PDT 24
Finished Aug 07 05:29:01 PM PDT 24
Peak memory 201428 kb
Host smart-3bc7fdd6-4145-43f7-9425-52518ce00f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313414096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1313414096
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1268912858
Short name T699
Test name
Test status
Simulation time 327272655889 ps
CPU time 199.75 seconds
Started Aug 07 05:21:50 PM PDT 24
Finished Aug 07 05:25:10 PM PDT 24
Peak memory 201404 kb
Host smart-d0b4029a-ec60-4a39-96aa-0bf74b94b6b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268912858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1268912858
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2478266562
Short name T114
Test name
Test status
Simulation time 159754073457 ps
CPU time 95.7 seconds
Started Aug 07 05:21:52 PM PDT 24
Finished Aug 07 05:23:28 PM PDT 24
Peak memory 201400 kb
Host smart-73be6cd5-69b4-4604-b98d-e04efe0c6a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478266562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2478266562
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1879216246
Short name T428
Test name
Test status
Simulation time 488036965997 ps
CPU time 276.81 seconds
Started Aug 07 05:21:51 PM PDT 24
Finished Aug 07 05:26:27 PM PDT 24
Peak memory 201444 kb
Host smart-9e6d032c-6194-4115-a34d-2be8f04106d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879216246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1879216246
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4029580496
Short name T328
Test name
Test status
Simulation time 623682456659 ps
CPU time 1409.33 seconds
Started Aug 07 05:21:56 PM PDT 24
Finished Aug 07 05:45:26 PM PDT 24
Peak memory 201404 kb
Host smart-3ccd40fc-f450-4fe7-8fe5-9a781cfabc4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029580496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4029580496
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1763508831
Short name T592
Test name
Test status
Simulation time 199999879782 ps
CPU time 325.48 seconds
Started Aug 07 05:21:55 PM PDT 24
Finished Aug 07 05:27:21 PM PDT 24
Peak memory 201400 kb
Host smart-3ae320f0-fee2-4b97-9fbf-2b15928556cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763508831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1763508831
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2534631594
Short name T72
Test name
Test status
Simulation time 31549752670 ps
CPU time 19.38 seconds
Started Aug 07 05:22:02 PM PDT 24
Finished Aug 07 05:22:21 PM PDT 24
Peak memory 201292 kb
Host smart-e52d462e-74f7-4f97-987e-4722e18ae8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534631594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2534631594
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4067849633
Short name T726
Test name
Test status
Simulation time 4788305838 ps
CPU time 2.26 seconds
Started Aug 07 05:22:10 PM PDT 24
Finished Aug 07 05:22:12 PM PDT 24
Peak memory 201300 kb
Host smart-7c3ab5d4-8242-4af2-a17d-6713b186e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067849633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4067849633
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.979689807
Short name T399
Test name
Test status
Simulation time 5639888289 ps
CPU time 7.35 seconds
Started Aug 07 05:21:46 PM PDT 24
Finished Aug 07 05:21:53 PM PDT 24
Peak memory 201276 kb
Host smart-258ddcd4-022d-4f1c-aca7-459c47de3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979689807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.979689807
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1091842801
Short name T39
Test name
Test status
Simulation time 163760897934 ps
CPU time 382.19 seconds
Started Aug 07 05:22:02 PM PDT 24
Finished Aug 07 05:28:24 PM PDT 24
Peak memory 201424 kb
Host smart-ca764fcb-22ca-4034-a600-3c5b064b61af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091842801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1091842801
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1454376736
Short name T538
Test name
Test status
Simulation time 459747862 ps
CPU time 1.6 seconds
Started Aug 07 05:22:19 PM PDT 24
Finished Aug 07 05:22:21 PM PDT 24
Peak memory 201112 kb
Host smart-86ce2095-7891-406e-bfcb-57f8d2bf6011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454376736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1454376736
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2944356512
Short name T322
Test name
Test status
Simulation time 323829971534 ps
CPU time 192.16 seconds
Started Aug 07 05:22:10 PM PDT 24
Finished Aug 07 05:25:23 PM PDT 24
Peak memory 201400 kb
Host smart-8fe34f25-d21a-4219-a19c-1224787fec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944356512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2944356512
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3055154655
Short name T121
Test name
Test status
Simulation time 497539903029 ps
CPU time 556.47 seconds
Started Aug 07 05:22:07 PM PDT 24
Finished Aug 07 05:31:24 PM PDT 24
Peak memory 201356 kb
Host smart-c3c54fea-87ee-414c-9aaa-b2a237ca5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055154655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3055154655
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3296698303
Short name T470
Test name
Test status
Simulation time 497411388916 ps
CPU time 1204 seconds
Started Aug 07 05:22:16 PM PDT 24
Finished Aug 07 05:42:20 PM PDT 24
Peak memory 201400 kb
Host smart-eb1c47ad-334c-4145-8a56-5fbeb2a25842
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296698303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3296698303
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2773368507
Short name T710
Test name
Test status
Simulation time 497279258933 ps
CPU time 1064.21 seconds
Started Aug 07 05:22:08 PM PDT 24
Finished Aug 07 05:39:52 PM PDT 24
Peak memory 201416 kb
Host smart-637c3d4d-50a0-4d1e-b73a-d88b0559d425
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773368507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2773368507
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.901434186
Short name T263
Test name
Test status
Simulation time 191091851125 ps
CPU time 447.83 seconds
Started Aug 07 05:22:12 PM PDT 24
Finished Aug 07 05:29:40 PM PDT 24
Peak memory 201376 kb
Host smart-0650ec68-ccaa-49e1-9230-3ea9a9b26ed0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901434186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.901434186
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2789577453
Short name T640
Test name
Test status
Simulation time 217349607487 ps
CPU time 131.12 seconds
Started Aug 07 05:22:13 PM PDT 24
Finished Aug 07 05:24:24 PM PDT 24
Peak memory 201352 kb
Host smart-b84d7305-f1bf-48c7-b055-0f8c15582a2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789577453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2789577453
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2497718837
Short name T752
Test name
Test status
Simulation time 44174974235 ps
CPU time 22.31 seconds
Started Aug 07 05:22:13 PM PDT 24
Finished Aug 07 05:22:36 PM PDT 24
Peak memory 201316 kb
Host smart-0d68ca86-e218-4244-8a6d-290d8cc393e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497718837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2497718837
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3719316674
Short name T104
Test name
Test status
Simulation time 4986674370 ps
CPU time 3.46 seconds
Started Aug 07 05:22:13 PM PDT 24
Finished Aug 07 05:22:17 PM PDT 24
Peak memory 201296 kb
Host smart-1b784ca6-2c71-49ac-81c8-54eaac73f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719316674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3719316674
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3907409250
Short name T519
Test name
Test status
Simulation time 5723004047 ps
CPU time 7.91 seconds
Started Aug 07 05:22:06 PM PDT 24
Finished Aug 07 05:22:14 PM PDT 24
Peak memory 201364 kb
Host smart-86427dc0-6bf7-400a-a276-3d1edfd8d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907409250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3907409250
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2459505296
Short name T584
Test name
Test status
Simulation time 322529233 ps
CPU time 1.37 seconds
Started Aug 07 05:22:28 PM PDT 24
Finished Aug 07 05:22:30 PM PDT 24
Peak memory 201172 kb
Host smart-dddd5bf8-54f5-4f54-9a67-047faa50f829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459505296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2459505296
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.244949520
Short name T680
Test name
Test status
Simulation time 339144615229 ps
CPU time 691.73 seconds
Started Aug 07 05:22:25 PM PDT 24
Finished Aug 07 05:33:56 PM PDT 24
Peak memory 201488 kb
Host smart-91500ae1-d283-4b16-a54d-f20b40c6a11f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244949520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.244949520
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4193912333
Short name T194
Test name
Test status
Simulation time 493518365948 ps
CPU time 299.64 seconds
Started Aug 07 05:22:22 PM PDT 24
Finished Aug 07 05:27:22 PM PDT 24
Peak memory 201388 kb
Host smart-9de7fdfd-0cdd-408b-a55c-902fb7c69a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193912333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4193912333
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.794103257
Short name T193
Test name
Test status
Simulation time 331790346886 ps
CPU time 98.41 seconds
Started Aug 07 05:22:18 PM PDT 24
Finished Aug 07 05:23:56 PM PDT 24
Peak memory 201452 kb
Host smart-517ea7ca-c72e-4d95-b7f3-b0d312a3b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794103257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.794103257
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2775627952
Short name T548
Test name
Test status
Simulation time 167047718438 ps
CPU time 203.93 seconds
Started Aug 07 05:22:19 PM PDT 24
Finished Aug 07 05:25:43 PM PDT 24
Peak memory 201404 kb
Host smart-a39a1de1-a45a-4d2b-951f-24e84f37ff3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775627952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2775627952
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3380725970
Short name T326
Test name
Test status
Simulation time 490458865461 ps
CPU time 792.3 seconds
Started Aug 07 05:22:18 PM PDT 24
Finished Aug 07 05:35:31 PM PDT 24
Peak memory 201432 kb
Host smart-e3430379-0734-456a-b08c-1105bca85386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380725970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3380725970
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.232402660
Short name T392
Test name
Test status
Simulation time 493897141129 ps
CPU time 563.28 seconds
Started Aug 07 05:22:20 PM PDT 24
Finished Aug 07 05:31:43 PM PDT 24
Peak memory 201292 kb
Host smart-a2e4e2fc-f0e4-44ad-9525-2465757d18c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=232402660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.232402660
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.490329036
Short name T537
Test name
Test status
Simulation time 538778203473 ps
CPU time 649.8 seconds
Started Aug 07 05:22:19 PM PDT 24
Finished Aug 07 05:33:09 PM PDT 24
Peak memory 201416 kb
Host smart-0d481742-47d9-4a3c-b3d1-36f22cafd904
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490329036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.490329036
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2079035940
Short name T708
Test name
Test status
Simulation time 410883360623 ps
CPU time 833.08 seconds
Started Aug 07 05:22:22 PM PDT 24
Finished Aug 07 05:36:16 PM PDT 24
Peak memory 201512 kb
Host smart-798fb9e1-c8fa-4072-a7b1-1c4180bb76e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079035940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2079035940
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3108918867
Short name T647
Test name
Test status
Simulation time 100027414936 ps
CPU time 355.36 seconds
Started Aug 07 05:22:29 PM PDT 24
Finished Aug 07 05:28:25 PM PDT 24
Peak memory 201796 kb
Host smart-5b1aa918-b347-4f49-a686-c1fcd0e695a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108918867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3108918867
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1390397203
Short name T107
Test name
Test status
Simulation time 41771110034 ps
CPU time 99.94 seconds
Started Aug 07 05:22:32 PM PDT 24
Finished Aug 07 05:24:12 PM PDT 24
Peak memory 201268 kb
Host smart-1e69da0d-6b1a-4f60-8b5a-eadf012dbdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390397203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1390397203
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.905367336
Short name T461
Test name
Test status
Simulation time 4635572663 ps
CPU time 2.57 seconds
Started Aug 07 05:22:23 PM PDT 24
Finished Aug 07 05:22:26 PM PDT 24
Peak memory 201264 kb
Host smart-54e5c5ae-3134-4d90-836c-cb29905f5f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905367336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.905367336
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2117617170
Short name T374
Test name
Test status
Simulation time 5840635453 ps
CPU time 13.83 seconds
Started Aug 07 05:22:18 PM PDT 24
Finished Aug 07 05:22:32 PM PDT 24
Peak memory 201296 kb
Host smart-629f901e-4349-41cf-a00d-747aec9097ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117617170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2117617170
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.535714350
Short name T288
Test name
Test status
Simulation time 170354643659 ps
CPU time 96.55 seconds
Started Aug 07 05:22:30 PM PDT 24
Finished Aug 07 05:24:06 PM PDT 24
Peak memory 201364 kb
Host smart-aba2a017-f440-4e7d-b0e5-d037f1ca53eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535714350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
535714350
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.477893855
Short name T325
Test name
Test status
Simulation time 40635520680 ps
CPU time 87.77 seconds
Started Aug 07 05:22:31 PM PDT 24
Finished Aug 07 05:23:59 PM PDT 24
Peak memory 210096 kb
Host smart-98379c29-d2b8-41cd-b3f3-bcf7aedd2c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477893855 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.477893855
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.620915364
Short name T442
Test name
Test status
Simulation time 332248091 ps
CPU time 1.3 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:13:18 PM PDT 24
Peak memory 201184 kb
Host smart-93acbd2a-3735-496c-95cf-476775d24354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620915364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.620915364
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.249833493
Short name T337
Test name
Test status
Simulation time 163408532187 ps
CPU time 200.06 seconds
Started Aug 07 05:13:13 PM PDT 24
Finished Aug 07 05:16:33 PM PDT 24
Peak memory 201408 kb
Host smart-86aaea32-a754-44c4-9f25-f1f85c81b972
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249833493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.249833493
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3760430358
Short name T737
Test name
Test status
Simulation time 163659063601 ps
CPU time 189.39 seconds
Started Aug 07 05:13:12 PM PDT 24
Finished Aug 07 05:16:22 PM PDT 24
Peak memory 201464 kb
Host smart-0dba40b0-fa3e-4f09-8c8d-160d0392fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760430358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3760430358
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1923353314
Short name T160
Test name
Test status
Simulation time 162808590604 ps
CPU time 203.04 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:16:34 PM PDT 24
Peak memory 201380 kb
Host smart-34f7c4f0-176e-4739-ac6d-209a2ef8aa50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923353314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1923353314
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3284418276
Short name T397
Test name
Test status
Simulation time 162807507490 ps
CPU time 333.05 seconds
Started Aug 07 05:13:13 PM PDT 24
Finished Aug 07 05:18:46 PM PDT 24
Peak memory 201396 kb
Host smart-0587cda2-8344-4363-9810-1475bfe06d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284418276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3284418276
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2560068988
Short name T378
Test name
Test status
Simulation time 163800571453 ps
CPU time 358.1 seconds
Started Aug 07 05:13:12 PM PDT 24
Finished Aug 07 05:19:10 PM PDT 24
Peak memory 201348 kb
Host smart-0727cdb9-329d-4767-849a-488c8a0f4733
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560068988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2560068988
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4221588111
Short name T593
Test name
Test status
Simulation time 541771227687 ps
CPU time 727.35 seconds
Started Aug 07 05:13:14 PM PDT 24
Finished Aug 07 05:25:22 PM PDT 24
Peak memory 201408 kb
Host smart-72115ab2-8c84-4ae5-b2b0-681b8bda8ea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221588111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4221588111
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2056248420
Short name T42
Test name
Test status
Simulation time 200993440310 ps
CPU time 176.12 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:16:07 PM PDT 24
Peak memory 201372 kb
Host smart-8bd89393-c12f-4866-b4b6-d65b44dc9d2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056248420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2056248420
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4139053598
Short name T226
Test name
Test status
Simulation time 109042049531 ps
CPU time 540.79 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:22:12 PM PDT 24
Peak memory 201868 kb
Host smart-1ea40d3f-3625-4120-874d-2d99074793bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139053598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4139053598
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2050921505
Short name T482
Test name
Test status
Simulation time 26945457610 ps
CPU time 16.45 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:13:28 PM PDT 24
Peak memory 201324 kb
Host smart-c2494913-3c3d-49a1-8063-b9c64e691977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050921505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2050921505
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2617731942
Short name T128
Test name
Test status
Simulation time 4926148319 ps
CPU time 11.86 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:13:23 PM PDT 24
Peak memory 201312 kb
Host smart-85099bb8-cb30-4450-bdfe-8b25d661cc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617731942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2617731942
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2301169231
Short name T89
Test name
Test status
Simulation time 4043996612 ps
CPU time 3.16 seconds
Started Aug 07 05:13:13 PM PDT 24
Finished Aug 07 05:13:16 PM PDT 24
Peak memory 217072 kb
Host smart-2a00f937-4fd6-40cd-a975-574b6b6bfb91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301169231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2301169231
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1680098650
Short name T716
Test name
Test status
Simulation time 5829648238 ps
CPU time 3.9 seconds
Started Aug 07 05:13:06 PM PDT 24
Finished Aug 07 05:13:10 PM PDT 24
Peak memory 201320 kb
Host smart-d76dc1f4-6505-4a2b-a071-4062afff0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680098650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1680098650
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2193111374
Short name T507
Test name
Test status
Simulation time 264663242468 ps
CPU time 851.82 seconds
Started Aug 07 05:13:10 PM PDT 24
Finished Aug 07 05:27:22 PM PDT 24
Peak memory 211736 kb
Host smart-0465a73a-0796-4ad3-bd17-2f06a53e86b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193111374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2193111374
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2957883372
Short name T27
Test name
Test status
Simulation time 51730036225 ps
CPU time 109.08 seconds
Started Aug 07 05:13:11 PM PDT 24
Finished Aug 07 05:15:00 PM PDT 24
Peak memory 217936 kb
Host smart-9ac5625e-0332-42f8-9443-39f78bb1ee2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957883372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2957883372
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3037749878
Short name T766
Test name
Test status
Simulation time 505608080 ps
CPU time 1.79 seconds
Started Aug 07 05:22:47 PM PDT 24
Finished Aug 07 05:22:49 PM PDT 24
Peak memory 201192 kb
Host smart-65ea37c5-d145-4735-8e9f-96b8931a5fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037749878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3037749878
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.424682664
Short name T323
Test name
Test status
Simulation time 165216663239 ps
CPU time 140.09 seconds
Started Aug 07 05:22:42 PM PDT 24
Finished Aug 07 05:25:03 PM PDT 24
Peak memory 201408 kb
Host smart-11d8fc90-7e1f-4510-ae28-4eaa9293e84b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424682664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.424682664
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2979482851
Short name T506
Test name
Test status
Simulation time 544872555708 ps
CPU time 1267.22 seconds
Started Aug 07 05:22:43 PM PDT 24
Finished Aug 07 05:43:50 PM PDT 24
Peak memory 201392 kb
Host smart-06ab5f55-9219-4f45-a2f4-0d9457e4b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979482851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2979482851
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2710686326
Short name T241
Test name
Test status
Simulation time 158114044868 ps
CPU time 348.1 seconds
Started Aug 07 05:22:36 PM PDT 24
Finished Aug 07 05:28:24 PM PDT 24
Peak memory 201440 kb
Host smart-f01b824d-968a-4676-9615-f1236a710f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710686326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2710686326
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3037532558
Short name T220
Test name
Test status
Simulation time 488355631202 ps
CPU time 287.46 seconds
Started Aug 07 05:22:34 PM PDT 24
Finished Aug 07 05:27:22 PM PDT 24
Peak memory 201456 kb
Host smart-d892ce77-2f44-4a38-93a2-d2c2285646eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037532558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3037532558
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3942154755
Short name T292
Test name
Test status
Simulation time 324809512601 ps
CPU time 206.96 seconds
Started Aug 07 05:22:28 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 201324 kb
Host smart-2cabcf01-a5fc-4e11-8294-ad50a1347b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942154755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3942154755
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.359584435
Short name T363
Test name
Test status
Simulation time 163210382384 ps
CPU time 354.08 seconds
Started Aug 07 05:22:31 PM PDT 24
Finished Aug 07 05:28:26 PM PDT 24
Peak memory 201336 kb
Host smart-ed688a79-e2b8-4cd0-8f4d-b7600b81cbaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=359584435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.359584435
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2914633057
Short name T36
Test name
Test status
Simulation time 353294473117 ps
CPU time 202.57 seconds
Started Aug 07 05:22:43 PM PDT 24
Finished Aug 07 05:26:06 PM PDT 24
Peak memory 201328 kb
Host smart-da9c2d23-19b0-4098-9dc0-9c1955eb866f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914633057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2914633057
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2231941944
Short name T210
Test name
Test status
Simulation time 213619168623 ps
CPU time 77.97 seconds
Started Aug 07 05:22:42 PM PDT 24
Finished Aug 07 05:24:00 PM PDT 24
Peak memory 201376 kb
Host smart-53de96cc-d8c4-4e2e-87d8-17a290918607
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231941944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2231941944
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4130374342
Short name T679
Test name
Test status
Simulation time 118711458873 ps
CPU time 468.7 seconds
Started Aug 07 05:22:48 PM PDT 24
Finished Aug 07 05:30:36 PM PDT 24
Peak memory 201796 kb
Host smart-528c6766-1265-42d9-94f1-672472204118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130374342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4130374342
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2395648232
Short name T365
Test name
Test status
Simulation time 43357777998 ps
CPU time 94.53 seconds
Started Aug 07 05:22:49 PM PDT 24
Finished Aug 07 05:24:23 PM PDT 24
Peak memory 201316 kb
Host smart-548150b2-008f-4190-9f7d-73e02586670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395648232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2395648232
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4196375007
Short name T709
Test name
Test status
Simulation time 4068845672 ps
CPU time 2.93 seconds
Started Aug 07 05:22:40 PM PDT 24
Finished Aug 07 05:22:43 PM PDT 24
Peak memory 201280 kb
Host smart-8e0b2242-b6f2-4509-80c6-e2a916220571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196375007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4196375007
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2313240174
Short name T460
Test name
Test status
Simulation time 6093353691 ps
CPU time 13.55 seconds
Started Aug 07 05:22:32 PM PDT 24
Finished Aug 07 05:22:46 PM PDT 24
Peak memory 201272 kb
Host smart-27a73492-c81b-4c78-a009-5ffc5d73e42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313240174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2313240174
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2847817355
Short name T52
Test name
Test status
Simulation time 94090550427 ps
CPU time 47.14 seconds
Started Aug 07 05:22:46 PM PDT 24
Finished Aug 07 05:23:33 PM PDT 24
Peak memory 209704 kb
Host smart-f3c2517f-a6c8-4ed4-bf3d-06f52066fb8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847817355 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2847817355
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4110326533
Short name T415
Test name
Test status
Simulation time 286944227 ps
CPU time 1.31 seconds
Started Aug 07 05:23:12 PM PDT 24
Finished Aug 07 05:23:13 PM PDT 24
Peak memory 201180 kb
Host smart-157c6214-35bc-4c2d-9150-8aba59e78aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110326533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4110326533
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3788317547
Short name T37
Test name
Test status
Simulation time 166225988040 ps
CPU time 10.75 seconds
Started Aug 07 05:22:57 PM PDT 24
Finished Aug 07 05:23:07 PM PDT 24
Peak memory 201336 kb
Host smart-d9a1ed2c-be9e-486a-ac3f-5c1ebd0fc472
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788317547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3788317547
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1877101901
Short name T608
Test name
Test status
Simulation time 193466237230 ps
CPU time 112.08 seconds
Started Aug 07 05:23:00 PM PDT 24
Finished Aug 07 05:24:52 PM PDT 24
Peak memory 201420 kb
Host smart-c2be2b2d-008f-4d25-8634-883f0d91784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877101901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1877101901
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.795204391
Short name T416
Test name
Test status
Simulation time 162554663772 ps
CPU time 275.64 seconds
Started Aug 07 05:22:55 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 201404 kb
Host smart-3172f631-31f5-4513-af8e-6c330b1e1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795204391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.795204391
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1229563107
Short name T602
Test name
Test status
Simulation time 485926751158 ps
CPU time 296.44 seconds
Started Aug 07 05:22:52 PM PDT 24
Finished Aug 07 05:27:49 PM PDT 24
Peak memory 201428 kb
Host smart-c0a8d91a-821b-4597-a5b2-0ea4afccb6b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229563107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1229563107
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2849530530
Short name T454
Test name
Test status
Simulation time 162342432348 ps
CPU time 374.75 seconds
Started Aug 07 05:22:53 PM PDT 24
Finished Aug 07 05:29:08 PM PDT 24
Peak memory 201384 kb
Host smart-78d1c0e5-d3cc-41db-aeec-998c3ce18b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849530530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2849530530
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.539111015
Short name T539
Test name
Test status
Simulation time 499900694865 ps
CPU time 316.77 seconds
Started Aug 07 05:22:55 PM PDT 24
Finished Aug 07 05:28:12 PM PDT 24
Peak memory 201356 kb
Host smart-553ac722-3a64-4e58-90a5-1898bc549787
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=539111015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.539111015
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3730504197
Short name T734
Test name
Test status
Simulation time 183532131197 ps
CPU time 107.77 seconds
Started Aug 07 05:23:00 PM PDT 24
Finished Aug 07 05:24:48 PM PDT 24
Peak memory 201400 kb
Host smart-26975af3-4807-4b5f-b742-1a18733343da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730504197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3730504197
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1732306954
Short name T360
Test name
Test status
Simulation time 202064154338 ps
CPU time 487.33 seconds
Started Aug 07 05:22:59 PM PDT 24
Finished Aug 07 05:31:06 PM PDT 24
Peak memory 201392 kb
Host smart-01694716-4dee-43cb-ab02-da121a0c54c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732306954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1732306954
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3226412092
Short name T347
Test name
Test status
Simulation time 127767975642 ps
CPU time 642.89 seconds
Started Aug 07 05:23:10 PM PDT 24
Finished Aug 07 05:33:53 PM PDT 24
Peak memory 201800 kb
Host smart-bd9d181a-5b64-483c-9148-792dd034482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226412092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3226412092
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2511491524
Short name T43
Test name
Test status
Simulation time 40503664806 ps
CPU time 90.59 seconds
Started Aug 07 05:23:05 PM PDT 24
Finished Aug 07 05:24:35 PM PDT 24
Peak memory 201320 kb
Host smart-c358615b-d17d-4106-835a-e13793a72571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511491524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2511491524
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2743704946
Short name T357
Test name
Test status
Simulation time 4008349843 ps
CPU time 1.4 seconds
Started Aug 07 05:23:04 PM PDT 24
Finished Aug 07 05:23:06 PM PDT 24
Peak memory 201304 kb
Host smart-3cd9d59e-205a-4d98-b269-d4fd737be0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743704946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2743704946
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4047770863
Short name T551
Test name
Test status
Simulation time 5960235282 ps
CPU time 4.31 seconds
Started Aug 07 05:22:54 PM PDT 24
Finished Aug 07 05:22:58 PM PDT 24
Peak memory 201308 kb
Host smart-c81345e1-25f9-40b6-9804-7f01558f06c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047770863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4047770863
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1540699935
Short name T161
Test name
Test status
Simulation time 329142948193 ps
CPU time 756.19 seconds
Started Aug 07 05:23:04 PM PDT 24
Finished Aug 07 05:35:40 PM PDT 24
Peak memory 201424 kb
Host smart-07f12403-47e1-444f-a570-e2e639155de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540699935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1540699935
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.67256856
Short name T759
Test name
Test status
Simulation time 85672595193 ps
CPU time 75.12 seconds
Started Aug 07 05:23:03 PM PDT 24
Finished Aug 07 05:24:19 PM PDT 24
Peak memory 210108 kb
Host smart-768d0099-aef4-44cd-affc-0927c8412e93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67256856 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.67256856
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2650048071
Short name T681
Test name
Test status
Simulation time 324531698 ps
CPU time 1.37 seconds
Started Aug 07 05:23:18 PM PDT 24
Finished Aug 07 05:23:20 PM PDT 24
Peak memory 201224 kb
Host smart-1a4ccc91-8ea8-4624-a3ca-3f90f52cd9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650048071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2650048071
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3546202087
Short name T277
Test name
Test status
Simulation time 539269429194 ps
CPU time 254.36 seconds
Started Aug 07 05:23:17 PM PDT 24
Finished Aug 07 05:27:32 PM PDT 24
Peak memory 201360 kb
Host smart-975e75a0-4d85-4e6f-bd36-ea5206187eca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546202087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3546202087
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3675529635
Short name T573
Test name
Test status
Simulation time 331683129419 ps
CPU time 704.67 seconds
Started Aug 07 05:23:15 PM PDT 24
Finished Aug 07 05:34:59 PM PDT 24
Peak memory 201436 kb
Host smart-f827aea4-9c10-49f8-9ef9-a8ac1bcb304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675529635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3675529635
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3755626642
Short name T777
Test name
Test status
Simulation time 163208140802 ps
CPU time 203.61 seconds
Started Aug 07 05:23:16 PM PDT 24
Finished Aug 07 05:26:40 PM PDT 24
Peak memory 201388 kb
Host smart-e038f2f2-ceab-4a8f-a243-cb85edf752b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755626642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3755626642
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3575600116
Short name T329
Test name
Test status
Simulation time 162033926684 ps
CPU time 354.18 seconds
Started Aug 07 05:23:12 PM PDT 24
Finished Aug 07 05:29:06 PM PDT 24
Peak memory 201408 kb
Host smart-73617cf6-7665-4833-aaaf-52f99f3c4a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575600116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3575600116
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2700060984
Short name T666
Test name
Test status
Simulation time 170229019140 ps
CPU time 363.74 seconds
Started Aug 07 05:23:27 PM PDT 24
Finished Aug 07 05:29:31 PM PDT 24
Peak memory 201400 kb
Host smart-5de41979-6f6a-4e21-979d-765006406999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700060984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2700060984
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1725463155
Short name T481
Test name
Test status
Simulation time 186517772296 ps
CPU time 424.06 seconds
Started Aug 07 05:23:17 PM PDT 24
Finished Aug 07 05:30:21 PM PDT 24
Peak memory 201452 kb
Host smart-6132e2b4-2623-445c-8398-25b0f4faf0fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725463155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1725463155
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1964925967
Short name T368
Test name
Test status
Simulation time 618719222870 ps
CPU time 695.76 seconds
Started Aug 07 05:23:14 PM PDT 24
Finished Aug 07 05:34:50 PM PDT 24
Peak memory 201368 kb
Host smart-7726ec9b-30d9-4bc0-91f9-9ffa0724d898
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964925967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1964925967
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2480514701
Short name T597
Test name
Test status
Simulation time 128000046276 ps
CPU time 698.54 seconds
Started Aug 07 05:23:23 PM PDT 24
Finished Aug 07 05:35:01 PM PDT 24
Peak memory 201776 kb
Host smart-b1a20e87-3c52-47b6-a618-0ae64db38355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480514701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2480514701
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3110363012
Short name T464
Test name
Test status
Simulation time 32101798097 ps
CPU time 72.09 seconds
Started Aug 07 05:23:23 PM PDT 24
Finished Aug 07 05:24:35 PM PDT 24
Peak memory 201212 kb
Host smart-b169342f-7a81-4830-abcb-dc0738717221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110363012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3110363012
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2889024161
Short name T785
Test name
Test status
Simulation time 3947392890 ps
CPU time 9.08 seconds
Started Aug 07 05:23:14 PM PDT 24
Finished Aug 07 05:23:23 PM PDT 24
Peak memory 201328 kb
Host smart-986a6eba-e144-4fb9-8369-985b54afdbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889024161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2889024161
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.137508309
Short name T541
Test name
Test status
Simulation time 5996844646 ps
CPU time 7.52 seconds
Started Aug 07 05:23:11 PM PDT 24
Finished Aug 07 05:23:19 PM PDT 24
Peak memory 201212 kb
Host smart-6e88d58b-081d-4e3a-90ff-7421d361fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137508309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.137508309
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1054380807
Short name T235
Test name
Test status
Simulation time 441259700912 ps
CPU time 1242.76 seconds
Started Aug 07 05:23:23 PM PDT 24
Finished Aug 07 05:44:06 PM PDT 24
Peak memory 209996 kb
Host smart-0a38b65d-0066-4f07-bcd1-b2536970bb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054380807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1054380807
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4289242356
Short name T222
Test name
Test status
Simulation time 356846727783 ps
CPU time 146.11 seconds
Started Aug 07 05:23:22 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 210108 kb
Host smart-418f6b32-35e2-4839-a1f2-c6994a0c966f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289242356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4289242356
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.769873261
Short name T24
Test name
Test status
Simulation time 410466519 ps
CPU time 1.08 seconds
Started Aug 07 05:23:42 PM PDT 24
Finished Aug 07 05:23:43 PM PDT 24
Peak memory 201184 kb
Host smart-4fa991be-ca84-453c-b01f-e1b7db2d0dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769873261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.769873261
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3491772917
Short name T276
Test name
Test status
Simulation time 353984854465 ps
CPU time 221.94 seconds
Started Aug 07 05:23:37 PM PDT 24
Finished Aug 07 05:27:20 PM PDT 24
Peak memory 201428 kb
Host smart-cc140be3-45d9-469c-99f5-9cf098b70dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491772917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3491772917
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1646741979
Short name T153
Test name
Test status
Simulation time 322387843101 ps
CPU time 618.12 seconds
Started Aug 07 05:23:27 PM PDT 24
Finished Aug 07 05:33:45 PM PDT 24
Peak memory 201400 kb
Host smart-4c131801-9fe9-400c-a083-348e686555b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646741979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1646741979
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.162075480
Short name T659
Test name
Test status
Simulation time 160658960215 ps
CPU time 115.13 seconds
Started Aug 07 05:23:28 PM PDT 24
Finished Aug 07 05:25:24 PM PDT 24
Peak memory 201400 kb
Host smart-be8591fb-532f-4c53-a434-237148c8631a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=162075480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.162075480
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3177085075
Short name T637
Test name
Test status
Simulation time 166347080021 ps
CPU time 398.34 seconds
Started Aug 07 05:23:23 PM PDT 24
Finished Aug 07 05:30:01 PM PDT 24
Peak memory 201408 kb
Host smart-6f1f5667-67f0-4809-949a-6f7f3591414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177085075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3177085075
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.721979559
Short name T529
Test name
Test status
Simulation time 161406326143 ps
CPU time 97.51 seconds
Started Aug 07 05:23:27 PM PDT 24
Finished Aug 07 05:25:04 PM PDT 24
Peak memory 201380 kb
Host smart-dd247f53-6a71-4cf4-87b8-a008a646d0e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=721979559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.721979559
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1160573989
Short name T247
Test name
Test status
Simulation time 381818298819 ps
CPU time 870.72 seconds
Started Aug 07 05:23:27 PM PDT 24
Finished Aug 07 05:37:58 PM PDT 24
Peak memory 201396 kb
Host smart-9ea15fa9-5e3d-47f0-815f-cf82915430e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160573989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1160573989
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3212731229
Short name T518
Test name
Test status
Simulation time 585293593808 ps
CPU time 658.94 seconds
Started Aug 07 05:23:33 PM PDT 24
Finished Aug 07 05:34:32 PM PDT 24
Peak memory 201412 kb
Host smart-a76c667a-2db5-43bb-ba4a-b7fd9b9ac153
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212731229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3212731229
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2994734740
Short name T437
Test name
Test status
Simulation time 103594914085 ps
CPU time 351.63 seconds
Started Aug 07 05:23:44 PM PDT 24
Finished Aug 07 05:29:36 PM PDT 24
Peak memory 201804 kb
Host smart-1c43d464-0ea0-4362-a683-791836e4e740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994734740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2994734740
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.460151510
Short name T354
Test name
Test status
Simulation time 45685576113 ps
CPU time 20.73 seconds
Started Aug 07 05:23:37 PM PDT 24
Finished Aug 07 05:23:58 PM PDT 24
Peak memory 201300 kb
Host smart-24592b46-a317-4416-85d4-68ed8d47ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460151510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.460151510
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4037104484
Short name T615
Test name
Test status
Simulation time 2936011770 ps
CPU time 2.59 seconds
Started Aug 07 05:23:39 PM PDT 24
Finished Aug 07 05:23:42 PM PDT 24
Peak memory 201280 kb
Host smart-b5604106-88bc-4345-bd62-939868b1116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037104484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4037104484
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1868267359
Short name T564
Test name
Test status
Simulation time 5918341441 ps
CPU time 14.12 seconds
Started Aug 07 05:23:20 PM PDT 24
Finished Aug 07 05:23:34 PM PDT 24
Peak memory 201276 kb
Host smart-dacd9708-2ecb-413e-a80c-178e121f5fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868267359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1868267359
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.666857345
Short name T511
Test name
Test status
Simulation time 206719841827 ps
CPU time 457.48 seconds
Started Aug 07 05:23:44 PM PDT 24
Finished Aug 07 05:31:22 PM PDT 24
Peak memory 201388 kb
Host smart-593ba30e-3e06-44a7-8556-f7e6a882f33b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666857345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
666857345
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3206169792
Short name T248
Test name
Test status
Simulation time 293102366768 ps
CPU time 267.18 seconds
Started Aug 07 05:23:42 PM PDT 24
Finished Aug 07 05:28:09 PM PDT 24
Peak memory 210092 kb
Host smart-b7048796-41b7-4f89-8147-7ec26dd62fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206169792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3206169792
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.357042033
Short name T388
Test name
Test status
Simulation time 493387331 ps
CPU time 1.69 seconds
Started Aug 07 05:23:55 PM PDT 24
Finished Aug 07 05:23:57 PM PDT 24
Peak memory 201196 kb
Host smart-c4fce478-ff43-46e1-974c-4afbb41965af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357042033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.357042033
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3587572148
Short name T728
Test name
Test status
Simulation time 324842831302 ps
CPU time 187.9 seconds
Started Aug 07 05:23:49 PM PDT 24
Finished Aug 07 05:26:57 PM PDT 24
Peak memory 201368 kb
Host smart-935a6dd2-ae1c-47f9-98d0-571fd2fc5be9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587572148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3587572148
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2715851365
Short name T175
Test name
Test status
Simulation time 449585155866 ps
CPU time 319.05 seconds
Started Aug 07 05:23:53 PM PDT 24
Finished Aug 07 05:29:12 PM PDT 24
Peak memory 201480 kb
Host smart-dbca63b3-f629-40c0-8484-2e4710a559f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715851365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2715851365
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.139497885
Short name T166
Test name
Test status
Simulation time 489908469376 ps
CPU time 560.9 seconds
Started Aug 07 05:23:50 PM PDT 24
Finished Aug 07 05:33:11 PM PDT 24
Peak memory 201380 kb
Host smart-2d9b2407-b549-418a-83e3-e11281dc71ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139497885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.139497885
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3862202775
Short name T503
Test name
Test status
Simulation time 163717925149 ps
CPU time 186.48 seconds
Started Aug 07 05:23:50 PM PDT 24
Finished Aug 07 05:26:57 PM PDT 24
Peak memory 201404 kb
Host smart-dbee8f74-6bf8-4125-bbe7-60b4e50c4757
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862202775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3862202775
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1122013642
Short name T745
Test name
Test status
Simulation time 162472720287 ps
CPU time 332.83 seconds
Started Aug 07 05:23:47 PM PDT 24
Finished Aug 07 05:29:20 PM PDT 24
Peak memory 201324 kb
Host smart-830b2c3a-9553-49ab-b63c-2263402ae858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122013642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1122013642
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1481059995
Short name T491
Test name
Test status
Simulation time 330096985830 ps
CPU time 741.17 seconds
Started Aug 07 05:23:49 PM PDT 24
Finished Aug 07 05:36:10 PM PDT 24
Peak memory 201364 kb
Host smart-9b6dafd5-5519-4b4e-9b3c-95dd5c260999
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481059995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1481059995
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3296832254
Short name T278
Test name
Test status
Simulation time 180563905051 ps
CPU time 226.23 seconds
Started Aug 07 05:23:51 PM PDT 24
Finished Aug 07 05:27:37 PM PDT 24
Peak memory 201348 kb
Host smart-2f641e08-726c-446b-86db-fc1e450a0a2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296832254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3296832254
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2237126905
Short name T400
Test name
Test status
Simulation time 411235445405 ps
CPU time 483.72 seconds
Started Aug 07 05:23:48 PM PDT 24
Finished Aug 07 05:31:52 PM PDT 24
Peak memory 201424 kb
Host smart-ce4b2c08-e220-409d-ad05-f7a4a0c8ee37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237126905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2237126905
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.866078087
Short name T29
Test name
Test status
Simulation time 97663655805 ps
CPU time 375.21 seconds
Started Aug 07 05:23:54 PM PDT 24
Finished Aug 07 05:30:09 PM PDT 24
Peak memory 201796 kb
Host smart-2516a3d5-89ab-4e31-b688-30ad472b713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866078087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.866078087
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1047058158
Short name T617
Test name
Test status
Simulation time 35569934134 ps
CPU time 83.17 seconds
Started Aug 07 05:23:55 PM PDT 24
Finished Aug 07 05:25:18 PM PDT 24
Peak memory 201280 kb
Host smart-f688286f-57fd-4697-952f-91f8732b2544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047058158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1047058158
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2042810053
Short name T417
Test name
Test status
Simulation time 5276930089 ps
CPU time 3.1 seconds
Started Aug 07 05:23:54 PM PDT 24
Finished Aug 07 05:23:58 PM PDT 24
Peak memory 201268 kb
Host smart-50ad92bd-a58d-414b-a6ff-971fa716ba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042810053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2042810053
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2309250938
Short name T429
Test name
Test status
Simulation time 5978200671 ps
CPU time 3.38 seconds
Started Aug 07 05:23:49 PM PDT 24
Finished Aug 07 05:23:52 PM PDT 24
Peak memory 201324 kb
Host smart-c077f4c8-7ba1-4205-9c5d-9326b2e68993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309250938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2309250938
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2236669652
Short name T605
Test name
Test status
Simulation time 165720379616 ps
CPU time 399.01 seconds
Started Aug 07 05:23:52 PM PDT 24
Finished Aug 07 05:30:31 PM PDT 24
Peak memory 201440 kb
Host smart-9be5b7b7-f828-4f55-9862-a53f4126d191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236669652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2236669652
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3807251048
Short name T361
Test name
Test status
Simulation time 509059527 ps
CPU time 0.87 seconds
Started Aug 07 05:25:08 PM PDT 24
Finished Aug 07 05:25:09 PM PDT 24
Peak memory 201164 kb
Host smart-4ce3caae-3f7b-4da9-854e-9da1b9a0012e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807251048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3807251048
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2808030986
Short name T654
Test name
Test status
Simulation time 325603181580 ps
CPU time 735.5 seconds
Started Aug 07 05:24:02 PM PDT 24
Finished Aug 07 05:36:18 PM PDT 24
Peak memory 201420 kb
Host smart-5e7a374f-aca6-4623-90d7-d8775a7ee9d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808030986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2808030986
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2910608838
Short name T253
Test name
Test status
Simulation time 158538070855 ps
CPU time 325.77 seconds
Started Aug 07 05:24:00 PM PDT 24
Finished Aug 07 05:29:26 PM PDT 24
Peak memory 201360 kb
Host smart-007e08a7-9473-45cc-99d1-311ebc495b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910608838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2910608838
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.45483145
Short name T436
Test name
Test status
Simulation time 334464802845 ps
CPU time 146.94 seconds
Started Aug 07 05:23:58 PM PDT 24
Finished Aug 07 05:26:25 PM PDT 24
Peak memory 201416 kb
Host smart-aa854ebe-0647-4aec-bab4-325f0fee7cf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=45483145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed
.45483145
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3142730645
Short name T111
Test name
Test status
Simulation time 413562030655 ps
CPU time 1032.79 seconds
Started Aug 07 05:24:06 PM PDT 24
Finished Aug 07 05:41:19 PM PDT 24
Peak memory 201412 kb
Host smart-4ca04f21-c083-4f53-bf43-fa641ee163c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142730645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3142730645
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2784018346
Short name T483
Test name
Test status
Simulation time 99786151495 ps
CPU time 510.59 seconds
Started Aug 07 05:24:14 PM PDT 24
Finished Aug 07 05:32:45 PM PDT 24
Peak memory 201844 kb
Host smart-c6dd8d64-9791-4823-a177-94ab560804fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784018346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2784018346
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1007804549
Short name T569
Test name
Test status
Simulation time 27166790346 ps
CPU time 16.63 seconds
Started Aug 07 05:24:14 PM PDT 24
Finished Aug 07 05:24:31 PM PDT 24
Peak memory 201300 kb
Host smart-022cdb8b-904b-4aa2-9032-9715e3e37b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007804549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1007804549
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3295798602
Short name T384
Test name
Test status
Simulation time 5189432424 ps
CPU time 12.6 seconds
Started Aug 07 05:24:11 PM PDT 24
Finished Aug 07 05:24:24 PM PDT 24
Peak memory 201232 kb
Host smart-198dfc9e-1efa-453a-aa43-55507c1768c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295798602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3295798602
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2697666406
Short name T628
Test name
Test status
Simulation time 5949386144 ps
CPU time 14.14 seconds
Started Aug 07 05:24:00 PM PDT 24
Finished Aug 07 05:24:15 PM PDT 24
Peak memory 201212 kb
Host smart-8bde6ad6-bb78-4221-80b3-cec45b0978eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697666406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2697666406
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2460500693
Short name T38
Test name
Test status
Simulation time 200343204141 ps
CPU time 229.62 seconds
Started Aug 07 05:24:10 PM PDT 24
Finished Aug 07 05:28:00 PM PDT 24
Peak memory 201384 kb
Host smart-11916d58-3295-4e13-a095-ba76fdc9ca8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460500693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2460500693
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2008550137
Short name T228
Test name
Test status
Simulation time 371981304699 ps
CPU time 281.38 seconds
Started Aug 07 05:24:12 PM PDT 24
Finished Aug 07 05:28:53 PM PDT 24
Peak memory 210256 kb
Host smart-d9fa4d22-a277-4a4a-b97d-60b652be80d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008550137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2008550137
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1156544754
Short name T500
Test name
Test status
Simulation time 478969370 ps
CPU time 0.69 seconds
Started Aug 07 05:24:18 PM PDT 24
Finished Aug 07 05:24:19 PM PDT 24
Peak memory 201160 kb
Host smart-7f7241ad-ec86-460c-a11c-80e95b1547c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156544754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1156544754
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2168630648
Short name T321
Test name
Test status
Simulation time 328327608809 ps
CPU time 754.43 seconds
Started Aug 07 05:24:21 PM PDT 24
Finished Aug 07 05:36:56 PM PDT 24
Peak memory 201352 kb
Host smart-33038c9c-8c4a-4520-b44a-2a73356774ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168630648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2168630648
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2425532041
Short name T664
Test name
Test status
Simulation time 527922772949 ps
CPU time 1193.89 seconds
Started Aug 07 05:24:18 PM PDT 24
Finished Aug 07 05:44:12 PM PDT 24
Peak memory 201464 kb
Host smart-7fe6e76b-cbdf-499f-9298-e26a6fe009e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425532041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2425532041
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.605093341
Short name T576
Test name
Test status
Simulation time 164837760528 ps
CPU time 59.27 seconds
Started Aug 07 05:24:13 PM PDT 24
Finished Aug 07 05:25:12 PM PDT 24
Peak memory 201372 kb
Host smart-286d6f37-ba07-42a1-808a-b9443c2ca40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605093341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.605093341
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2828656032
Short name T122
Test name
Test status
Simulation time 326539994872 ps
CPU time 200.17 seconds
Started Aug 07 05:24:11 PM PDT 24
Finished Aug 07 05:27:31 PM PDT 24
Peak memory 201404 kb
Host smart-563059a3-261e-4361-9b64-421308e6602d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828656032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2828656032
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4291801688
Short name T191
Test name
Test status
Simulation time 492730596598 ps
CPU time 92.59 seconds
Started Aug 07 05:24:10 PM PDT 24
Finished Aug 07 05:25:43 PM PDT 24
Peak memory 201376 kb
Host smart-aaaa3965-063d-4258-ae4f-a3c60e3f6ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291801688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4291801688
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3335678315
Short name T784
Test name
Test status
Simulation time 323654123484 ps
CPU time 728.63 seconds
Started Aug 07 05:24:10 PM PDT 24
Finished Aug 07 05:36:19 PM PDT 24
Peak memory 201348 kb
Host smart-87d411f9-a857-492b-be1c-a4f977714170
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335678315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3335678315
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3709001826
Short name T199
Test name
Test status
Simulation time 580263076778 ps
CPU time 388.74 seconds
Started Aug 07 05:24:13 PM PDT 24
Finished Aug 07 05:30:42 PM PDT 24
Peak memory 201344 kb
Host smart-c464d709-8c55-4f41-ac1d-68ba2adbdae7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709001826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3709001826
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3099867582
Short name T553
Test name
Test status
Simulation time 595467046005 ps
CPU time 134.33 seconds
Started Aug 07 05:24:18 PM PDT 24
Finished Aug 07 05:26:32 PM PDT 24
Peak memory 201476 kb
Host smart-be776c29-1fec-49f5-9bd5-905e51de4997
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099867582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3099867582
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3442614030
Short name T465
Test name
Test status
Simulation time 134110327294 ps
CPU time 662.77 seconds
Started Aug 07 05:24:18 PM PDT 24
Finished Aug 07 05:35:21 PM PDT 24
Peak memory 201820 kb
Host smart-46479a40-102d-4fe5-b7b4-7d9964d3ba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442614030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3442614030
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.781852677
Short name T446
Test name
Test status
Simulation time 43990181819 ps
CPU time 102.01 seconds
Started Aug 07 05:24:20 PM PDT 24
Finished Aug 07 05:26:02 PM PDT 24
Peak memory 201264 kb
Host smart-fc5cccca-d5ff-4edb-b217-d27681cc2747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781852677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.781852677
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1574023731
Short name T719
Test name
Test status
Simulation time 3847517554 ps
CPU time 9.41 seconds
Started Aug 07 05:24:18 PM PDT 24
Finished Aug 07 05:24:28 PM PDT 24
Peak memory 201340 kb
Host smart-9d9475de-2279-44a6-b106-6a5b46f81d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574023731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1574023731
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3628976758
Short name T433
Test name
Test status
Simulation time 6102671891 ps
CPU time 14.4 seconds
Started Aug 07 05:24:12 PM PDT 24
Finished Aug 07 05:24:26 PM PDT 24
Peak memory 201324 kb
Host smart-94c01b66-49cd-4c7d-bdb0-bd7921932b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628976758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3628976758
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1563291631
Short name T492
Test name
Test status
Simulation time 175641673265 ps
CPU time 99.41 seconds
Started Aug 07 05:24:16 PM PDT 24
Finished Aug 07 05:25:56 PM PDT 24
Peak memory 201344 kb
Host smart-86a51e55-49c2-46a5-9983-41fbb47c65bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563291631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1563291631
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3953824899
Short name T559
Test name
Test status
Simulation time 257967982014 ps
CPU time 321.46 seconds
Started Aug 07 05:24:17 PM PDT 24
Finished Aug 07 05:29:39 PM PDT 24
Peak memory 209732 kb
Host smart-e057751a-a7c7-495d-a8e6-db10b805840b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953824899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3953824899
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2710679632
Short name T778
Test name
Test status
Simulation time 328921075 ps
CPU time 1.3 seconds
Started Aug 07 05:24:33 PM PDT 24
Finished Aug 07 05:24:34 PM PDT 24
Peak memory 201148 kb
Host smart-e1a059e2-60d5-450d-b043-33ed9ec9ab98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710679632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2710679632
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2255879173
Short name T676
Test name
Test status
Simulation time 322482147525 ps
CPU time 798.06 seconds
Started Aug 07 05:24:23 PM PDT 24
Finished Aug 07 05:37:41 PM PDT 24
Peak memory 201364 kb
Host smart-6efa31d0-aa4a-42a7-87f6-a0238a802a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255879173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2255879173
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.587743082
Short name T383
Test name
Test status
Simulation time 322719983950 ps
CPU time 685.04 seconds
Started Aug 07 05:24:24 PM PDT 24
Finished Aug 07 05:35:49 PM PDT 24
Peak memory 201396 kb
Host smart-4bbdce58-5df0-4496-be2a-67476b09cf1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=587743082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.587743082
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.393833895
Short name T672
Test name
Test status
Simulation time 327031986901 ps
CPU time 184.36 seconds
Started Aug 07 05:24:23 PM PDT 24
Finished Aug 07 05:27:28 PM PDT 24
Peak memory 201404 kb
Host smart-eab635e0-e6c8-443b-add3-2a852655d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393833895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.393833895
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1763810311
Short name T473
Test name
Test status
Simulation time 170485239413 ps
CPU time 92.83 seconds
Started Aug 07 05:24:22 PM PDT 24
Finished Aug 07 05:25:55 PM PDT 24
Peak memory 201384 kb
Host smart-72f91e28-57c1-4dee-b484-bf78b0fd9f30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763810311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1763810311
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2537878563
Short name T690
Test name
Test status
Simulation time 394103610844 ps
CPU time 140.37 seconds
Started Aug 07 05:24:29 PM PDT 24
Finished Aug 07 05:26:50 PM PDT 24
Peak memory 201384 kb
Host smart-2df01d93-3631-4a1a-b244-ebe331e68eef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537878563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2537878563
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.969749845
Short name T68
Test name
Test status
Simulation time 120813899264 ps
CPU time 650.95 seconds
Started Aug 07 05:24:35 PM PDT 24
Finished Aug 07 05:35:26 PM PDT 24
Peak memory 201848 kb
Host smart-f1e4490e-e022-4c31-aa67-4eb44e62d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969749845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.969749845
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3292883407
Short name T585
Test name
Test status
Simulation time 30188874806 ps
CPU time 69.81 seconds
Started Aug 07 05:24:35 PM PDT 24
Finished Aug 07 05:25:45 PM PDT 24
Peak memory 201300 kb
Host smart-d733eaa5-b3cd-44dc-972d-037601b087ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292883407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3292883407
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.922866845
Short name T28
Test name
Test status
Simulation time 3376283938 ps
CPU time 7.7 seconds
Started Aug 07 05:24:34 PM PDT 24
Finished Aug 07 05:24:42 PM PDT 24
Peak memory 201316 kb
Host smart-3a7bc6d8-8d42-4eea-9dba-2ccb1da1b717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922866845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.922866845
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.518060328
Short name T762
Test name
Test status
Simulation time 5980645512 ps
CPU time 2.54 seconds
Started Aug 07 05:24:21 PM PDT 24
Finished Aug 07 05:24:24 PM PDT 24
Peak memory 201312 kb
Host smart-a4c0ea57-f35e-47b7-a1f1-0720ed2a125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518060328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.518060328
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2195171987
Short name T580
Test name
Test status
Simulation time 417852747297 ps
CPU time 1230.75 seconds
Started Aug 07 05:24:34 PM PDT 24
Finished Aug 07 05:45:05 PM PDT 24
Peak memory 201836 kb
Host smart-1985f6e0-9bd5-4965-9706-8334b660c1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195171987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2195171987
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.418403286
Short name T19
Test name
Test status
Simulation time 34796494037 ps
CPU time 68.9 seconds
Started Aug 07 05:24:34 PM PDT 24
Finished Aug 07 05:25:43 PM PDT 24
Peak memory 210184 kb
Host smart-788f3714-752f-4ffd-811f-e0eda301060e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418403286 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.418403286
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3893886728
Short name T670
Test name
Test status
Simulation time 330610956 ps
CPU time 1.02 seconds
Started Aug 07 05:25:10 PM PDT 24
Finished Aug 07 05:25:11 PM PDT 24
Peak memory 201196 kb
Host smart-473919d0-2b97-456b-9ee9-816d349ce538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893886728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3893886728
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2358102228
Short name T282
Test name
Test status
Simulation time 526739928310 ps
CPU time 847.22 seconds
Started Aug 07 05:24:47 PM PDT 24
Finished Aug 07 05:38:55 PM PDT 24
Peak memory 201328 kb
Host smart-4a0f1f33-6b17-4c71-807c-6e845da4d6a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358102228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2358102228
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4077885439
Short name T645
Test name
Test status
Simulation time 184827034990 ps
CPU time 114.49 seconds
Started Aug 07 05:24:48 PM PDT 24
Finished Aug 07 05:26:42 PM PDT 24
Peak memory 201424 kb
Host smart-f6893194-c044-4ad8-9419-e432048d7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077885439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4077885439
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3302402007
Short name T612
Test name
Test status
Simulation time 329726299654 ps
CPU time 221.58 seconds
Started Aug 07 05:24:39 PM PDT 24
Finished Aug 07 05:28:21 PM PDT 24
Peak memory 201424 kb
Host smart-9e5b19b4-323a-4483-b00e-e3d58806c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302402007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3302402007
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2201831883
Short name T431
Test name
Test status
Simulation time 173874951776 ps
CPU time 404.9 seconds
Started Aug 07 05:24:43 PM PDT 24
Finished Aug 07 05:31:28 PM PDT 24
Peak memory 201468 kb
Host smart-86210252-faf6-4d8f-ace4-992a4298af85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201831883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2201831883
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3497578787
Short name T543
Test name
Test status
Simulation time 334886455796 ps
CPU time 401.33 seconds
Started Aug 07 05:24:41 PM PDT 24
Finished Aug 07 05:31:23 PM PDT 24
Peak memory 201380 kb
Host smart-698e294a-ea95-4d80-82b6-29906fc59550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497578787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3497578787
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3679884118
Short name T561
Test name
Test status
Simulation time 490851137312 ps
CPU time 99.96 seconds
Started Aug 07 05:24:42 PM PDT 24
Finished Aug 07 05:26:22 PM PDT 24
Peak memory 201408 kb
Host smart-1f9b63ff-1613-446b-9175-1d348a9e9d33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679884118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3679884118
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.221815832
Short name T336
Test name
Test status
Simulation time 171505625560 ps
CPU time 203.65 seconds
Started Aug 07 05:24:47 PM PDT 24
Finished Aug 07 05:28:11 PM PDT 24
Peak memory 201440 kb
Host smart-eac46fa6-6730-4c68-8c66-187acf984090
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221815832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.221815832
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3050531899
Short name T250
Test name
Test status
Simulation time 398204965386 ps
CPU time 852.99 seconds
Started Aug 07 05:24:49 PM PDT 24
Finished Aug 07 05:39:02 PM PDT 24
Peak memory 201380 kb
Host smart-4c326069-6fce-423a-94a4-2a48da1608c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050531899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3050531899
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4232647114
Short name T596
Test name
Test status
Simulation time 73671647738 ps
CPU time 384.59 seconds
Started Aug 07 05:24:49 PM PDT 24
Finished Aug 07 05:31:13 PM PDT 24
Peak memory 201784 kb
Host smart-cf279f9d-9821-45aa-987a-ed36fc28a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232647114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4232647114
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2351779384
Short name T412
Test name
Test status
Simulation time 26348083062 ps
CPU time 57.07 seconds
Started Aug 07 05:24:45 PM PDT 24
Finished Aug 07 05:25:42 PM PDT 24
Peak memory 201340 kb
Host smart-573044f1-b3fe-4995-aba9-a45dd2661303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351779384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2351779384
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.55975534
Short name T691
Test name
Test status
Simulation time 4358315364 ps
CPU time 1.83 seconds
Started Aug 07 05:24:47 PM PDT 24
Finished Aug 07 05:24:49 PM PDT 24
Peak memory 201304 kb
Host smart-6a208445-6689-4761-afb2-ca2dfc448f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55975534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.55975534
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1085654032
Short name T579
Test name
Test status
Simulation time 6049252998 ps
CPU time 5.52 seconds
Started Aug 07 05:24:42 PM PDT 24
Finished Aug 07 05:24:47 PM PDT 24
Peak memory 201276 kb
Host smart-004eb979-6e1a-495e-bfdb-8e3a8d4fdeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085654032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1085654032
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1692154488
Short name T625
Test name
Test status
Simulation time 54136253082 ps
CPU time 58.19 seconds
Started Aug 07 05:24:54 PM PDT 24
Finished Aug 07 05:25:52 PM PDT 24
Peak memory 201212 kb
Host smart-5fe65c1e-2df9-4051-b0e8-b6d109b3aea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692154488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1692154488
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.734272897
Short name T330
Test name
Test status
Simulation time 190199713783 ps
CPU time 46.33 seconds
Started Aug 07 05:24:54 PM PDT 24
Finished Aug 07 05:25:41 PM PDT 24
Peak memory 209692 kb
Host smart-1b290b00-ce4a-4ddd-9eb9-77ef06868d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734272897 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.734272897
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1610558532
Short name T172
Test name
Test status
Simulation time 487508192 ps
CPU time 1.15 seconds
Started Aug 07 05:25:01 PM PDT 24
Finished Aug 07 05:25:02 PM PDT 24
Peak memory 201156 kb
Host smart-e0a1e74e-7c4b-49e9-a2a4-28d0fdada55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610558532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1610558532
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2009175706
Short name T40
Test name
Test status
Simulation time 348548703003 ps
CPU time 50.12 seconds
Started Aug 07 05:24:57 PM PDT 24
Finished Aug 07 05:25:48 PM PDT 24
Peak memory 201368 kb
Host smart-0da4a890-9dd3-4a5b-b64f-f6399211d988
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009175706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2009175706
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2745732793
Short name T217
Test name
Test status
Simulation time 518278674271 ps
CPU time 1085.63 seconds
Started Aug 07 05:25:01 PM PDT 24
Finished Aug 07 05:43:06 PM PDT 24
Peak memory 201384 kb
Host smart-c4596462-4f1d-431a-bb61-a520f80b9263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745732793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2745732793
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2033438296
Short name T31
Test name
Test status
Simulation time 492568504319 ps
CPU time 1128.51 seconds
Started Aug 07 05:24:59 PM PDT 24
Finished Aug 07 05:43:47 PM PDT 24
Peak memory 201416 kb
Host smart-86890f0a-352f-48a0-882b-73e7d26b1972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033438296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2033438296
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.23415786
Short name T763
Test name
Test status
Simulation time 168369545016 ps
CPU time 91.23 seconds
Started Aug 07 05:24:55 PM PDT 24
Finished Aug 07 05:26:26 PM PDT 24
Peak memory 201624 kb
Host smart-f7912e76-28ed-4abd-87bd-76f2bd9e913d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=23415786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed
.23415786
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1548657332
Short name T237
Test name
Test status
Simulation time 416168789729 ps
CPU time 258.31 seconds
Started Aug 07 05:25:00 PM PDT 24
Finished Aug 07 05:29:18 PM PDT 24
Peak memory 201628 kb
Host smart-dda38b6e-3dbd-4c4f-a206-5af8590c70cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548657332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1548657332
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.800024018
Short name T409
Test name
Test status
Simulation time 201937459927 ps
CPU time 457.85 seconds
Started Aug 07 05:25:02 PM PDT 24
Finished Aug 07 05:32:40 PM PDT 24
Peak memory 201336 kb
Host smart-e0949ea4-debc-4b86-b668-9afe7dcfefd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800024018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.800024018
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3611416064
Short name T478
Test name
Test status
Simulation time 120236091982 ps
CPU time 399.42 seconds
Started Aug 07 05:24:59 PM PDT 24
Finished Aug 07 05:31:39 PM PDT 24
Peak memory 201840 kb
Host smart-f4b4261a-5112-481c-968b-e16843610f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611416064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3611416064
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3321971078
Short name T787
Test name
Test status
Simulation time 42363280502 ps
CPU time 23.37 seconds
Started Aug 07 05:25:00 PM PDT 24
Finished Aug 07 05:25:23 PM PDT 24
Peak memory 201312 kb
Host smart-a9744aff-ac4b-4e69-b8c8-2a7b74618b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321971078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3321971078
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1687025138
Short name T359
Test name
Test status
Simulation time 5184542740 ps
CPU time 12.55 seconds
Started Aug 07 05:24:59 PM PDT 24
Finished Aug 07 05:25:12 PM PDT 24
Peak memory 201240 kb
Host smart-b0b040d5-fa33-40a5-b1cc-3e73b778eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687025138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1687025138
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1787905260
Short name T477
Test name
Test status
Simulation time 5934351082 ps
CPU time 3.51 seconds
Started Aug 07 05:24:54 PM PDT 24
Finished Aug 07 05:24:57 PM PDT 24
Peak memory 201320 kb
Host smart-746c4362-270d-4f1b-b56c-b9d16bac6b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787905260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1787905260
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1244832532
Short name T301
Test name
Test status
Simulation time 408286716468 ps
CPU time 1167.33 seconds
Started Aug 07 05:24:59 PM PDT 24
Finished Aug 07 05:44:27 PM PDT 24
Peak memory 201812 kb
Host smart-c641e3ae-a26b-450a-a0a6-2594a6cf0360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244832532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1244832532
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3749326830
Short name T61
Test name
Test status
Simulation time 473088758 ps
CPU time 0.87 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:13:18 PM PDT 24
Peak memory 201184 kb
Host smart-e3e8fd20-77fc-43e6-b4fe-4b361212f544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749326830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3749326830
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.492671641
Short name T512
Test name
Test status
Simulation time 356215193086 ps
CPU time 825.41 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:27:01 PM PDT 24
Peak memory 201344 kb
Host smart-ecd162d5-abf6-4e2b-8631-93680a7cf1e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492671641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.492671641
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2498229654
Short name T563
Test name
Test status
Simulation time 165537730264 ps
CPU time 387.78 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:19:45 PM PDT 24
Peak memory 201368 kb
Host smart-0d705e68-7d1a-429c-a32a-cc7d5793e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498229654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2498229654
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3242152626
Short name T124
Test name
Test status
Simulation time 165647230493 ps
CPU time 82.76 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:14:39 PM PDT 24
Peak memory 201444 kb
Host smart-2b48a496-e9d9-40f4-925b-b06bf472b465
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242152626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3242152626
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1118927099
Short name T739
Test name
Test status
Simulation time 333350312569 ps
CPU time 737.59 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:25:35 PM PDT 24
Peak memory 201360 kb
Host smart-31e689f0-1d2a-4b19-b4df-87cc495e88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118927099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1118927099
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.880288363
Short name T704
Test name
Test status
Simulation time 159293668274 ps
CPU time 90.44 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:14:46 PM PDT 24
Peak memory 201376 kb
Host smart-c0b37123-8801-4945-85cc-eb4f6272dc83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=880288363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.880288363
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1179498103
Short name T177
Test name
Test status
Simulation time 267751334211 ps
CPU time 193.04 seconds
Started Aug 07 05:13:18 PM PDT 24
Finished Aug 07 05:16:31 PM PDT 24
Peak memory 201396 kb
Host smart-84184073-1ce7-43a4-bec9-486d6f423699
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179498103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1179498103
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3127078394
Short name T108
Test name
Test status
Simulation time 389140707573 ps
CPU time 504.43 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:21:42 PM PDT 24
Peak memory 201368 kb
Host smart-a620388c-3d85-4469-b468-c6c17ee1958e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127078394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3127078394
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2777664350
Short name T404
Test name
Test status
Simulation time 85077108138 ps
CPU time 346.25 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:19:03 PM PDT 24
Peak memory 201760 kb
Host smart-6d6fb86f-e22b-4fbc-88c4-7686f641f97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777664350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2777664350
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.9800452
Short name T707
Test name
Test status
Simulation time 29118568918 ps
CPU time 66.68 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:14:23 PM PDT 24
Peak memory 201272 kb
Host smart-7b2021f6-0611-4968-b62f-717ddcae55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9800452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.9800452
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3180587364
Short name T675
Test name
Test status
Simulation time 4611675907 ps
CPU time 6.09 seconds
Started Aug 07 05:13:16 PM PDT 24
Finished Aug 07 05:13:23 PM PDT 24
Peak memory 201256 kb
Host smart-3e0045e3-a8b9-4f18-81ec-98611223e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180587364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3180587364
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.606945992
Short name T366
Test name
Test status
Simulation time 6055475852 ps
CPU time 2.52 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:13:20 PM PDT 24
Peak memory 201340 kb
Host smart-1a6bdd44-35a2-4585-9c51-e2ec6fc94095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606945992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.606945992
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2667597215
Short name T331
Test name
Test status
Simulation time 302688861862 ps
CPU time 661.29 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:24:19 PM PDT 24
Peak memory 212140 kb
Host smart-044cec50-ee95-4416-a982-e6e9bc7e0f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667597215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2667597215
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1544522530
Short name T536
Test name
Test status
Simulation time 395973142 ps
CPU time 1.47 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:13:24 PM PDT 24
Peak memory 201212 kb
Host smart-26d8b2d3-9185-4a48-8d48-3026111eea3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544522530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1544522530
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.388950924
Short name T756
Test name
Test status
Simulation time 334775678011 ps
CPU time 117.59 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:15:20 PM PDT 24
Peak memory 201348 kb
Host smart-0af4e662-60d3-4ba8-9bb8-9de850bfda40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388950924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.388950924
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.585114876
Short name T187
Test name
Test status
Simulation time 334515706449 ps
CPU time 236.32 seconds
Started Aug 07 05:13:26 PM PDT 24
Finished Aug 07 05:17:23 PM PDT 24
Peak memory 201452 kb
Host smart-79cd6f17-ab84-434f-88c2-26325834eab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585114876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.585114876
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2072409787
Short name T683
Test name
Test status
Simulation time 326121418662 ps
CPU time 773.62 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:26:16 PM PDT 24
Peak memory 201480 kb
Host smart-63fe64f9-4f3a-4d55-9e71-92afcb285246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072409787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2072409787
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3501143462
Short name T636
Test name
Test status
Simulation time 333316049167 ps
CPU time 108.3 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:15:11 PM PDT 24
Peak memory 201396 kb
Host smart-bfe5c6ca-7d2d-481c-9ea1-256a51a924ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501143462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3501143462
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3164937326
Short name T180
Test name
Test status
Simulation time 161694676971 ps
CPU time 94.7 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:14:57 PM PDT 24
Peak memory 201388 kb
Host smart-dac7423e-a2f1-47ed-9510-0acb9da8f775
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164937326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3164937326
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4212639465
Short name T372
Test name
Test status
Simulation time 205213608171 ps
CPU time 230.94 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:17:13 PM PDT 24
Peak memory 201356 kb
Host smart-d24e3c80-dcc6-4634-9953-d249f14386ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212639465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4212639465
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1460446904
Short name T700
Test name
Test status
Simulation time 100083097795 ps
CPU time 359.81 seconds
Started Aug 07 05:13:26 PM PDT 24
Finished Aug 07 05:19:26 PM PDT 24
Peak memory 201860 kb
Host smart-c3c2d957-4709-4b75-bffa-e328ad2bacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460446904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1460446904
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4209566097
Short name T650
Test name
Test status
Simulation time 33561602927 ps
CPU time 21.52 seconds
Started Aug 07 05:13:26 PM PDT 24
Finished Aug 07 05:13:47 PM PDT 24
Peak memory 201312 kb
Host smart-0e28454e-7dfe-4a22-93e0-611a22d179a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209566097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4209566097
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4277579688
Short name T426
Test name
Test status
Simulation time 4038136243 ps
CPU time 10.12 seconds
Started Aug 07 05:13:24 PM PDT 24
Finished Aug 07 05:13:34 PM PDT 24
Peak memory 201316 kb
Host smart-f9371d80-5737-4a96-a131-90a0a14e42a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277579688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4277579688
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1869522767
Short name T723
Test name
Test status
Simulation time 5909893166 ps
CPU time 2.74 seconds
Started Aug 07 05:13:17 PM PDT 24
Finished Aug 07 05:13:20 PM PDT 24
Peak memory 201324 kb
Host smart-c065e41d-2a63-40d1-80c9-4468b980bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869522767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1869522767
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3095403992
Short name T289
Test name
Test status
Simulation time 166687244039 ps
CPU time 95.65 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:14:58 PM PDT 24
Peak memory 201364 kb
Host smart-fdcc1820-0095-4ab6-baf9-3186acb271b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095403992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3095403992
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.414807114
Short name T790
Test name
Test status
Simulation time 96892572374 ps
CPU time 241.32 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:17:24 PM PDT 24
Peak memory 217432 kb
Host smart-e03e6ecf-ab47-4e08-9060-b881cd5e0cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414807114 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.414807114
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2315168621
Short name T23
Test name
Test status
Simulation time 432016286 ps
CPU time 1.53 seconds
Started Aug 07 05:13:31 PM PDT 24
Finished Aug 07 05:13:33 PM PDT 24
Peak memory 201200 kb
Host smart-f639779b-7cd7-45a4-b00e-7d162da58986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315168621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2315168621
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1782014338
Short name T309
Test name
Test status
Simulation time 355628122051 ps
CPU time 401.17 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:20:04 PM PDT 24
Peak memory 201360 kb
Host smart-6339a3e2-45ee-4604-961d-f77d07e9169a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782014338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1782014338
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.535149447
Short name T614
Test name
Test status
Simulation time 347348727093 ps
CPU time 70.11 seconds
Started Aug 07 05:13:26 PM PDT 24
Finished Aug 07 05:14:36 PM PDT 24
Peak memory 201372 kb
Host smart-9a101c62-96fe-4423-8064-df645e8c74b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535149447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.535149447
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3885805443
Short name T638
Test name
Test status
Simulation time 165363245910 ps
CPU time 99.63 seconds
Started Aug 07 05:13:24 PM PDT 24
Finished Aug 07 05:15:03 PM PDT 24
Peak memory 201416 kb
Host smart-c4e42f8f-970f-46f0-bdde-567403dc0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885805443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3885805443
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3276558986
Short name T405
Test name
Test status
Simulation time 160850098054 ps
CPU time 371.94 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:19:34 PM PDT 24
Peak memory 201400 kb
Host smart-9d51ffb1-359f-4f63-91a1-4bb9cf44de1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276558986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3276558986
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3352733375
Short name T291
Test name
Test status
Simulation time 478693588442 ps
CPU time 501.7 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:21:44 PM PDT 24
Peak memory 201368 kb
Host smart-19e34020-1845-46ef-8ee8-126600526ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352733375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3352733375
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.584202813
Short name T456
Test name
Test status
Simulation time 331885452093 ps
CPU time 103.47 seconds
Started Aug 07 05:13:21 PM PDT 24
Finished Aug 07 05:15:05 PM PDT 24
Peak memory 201344 kb
Host smart-85e0db52-6a03-497a-b044-7d1badf32509
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=584202813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.584202813
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2886303138
Short name T262
Test name
Test status
Simulation time 178919942741 ps
CPU time 404.87 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:20:08 PM PDT 24
Peak memory 201364 kb
Host smart-9b7d7883-6df7-4614-a8b5-18667194cdef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886303138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2886303138
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1179570745
Short name T474
Test name
Test status
Simulation time 212667163496 ps
CPU time 458.76 seconds
Started Aug 07 05:13:24 PM PDT 24
Finished Aug 07 05:21:03 PM PDT 24
Peak memory 201396 kb
Host smart-cf816b0f-5b2a-4688-9a12-97a46cd90ded
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179570745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1179570745
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.243184775
Short name T229
Test name
Test status
Simulation time 112788743309 ps
CPU time 527.34 seconds
Started Aug 07 05:13:29 PM PDT 24
Finished Aug 07 05:22:16 PM PDT 24
Peak memory 201776 kb
Host smart-7062a6c6-f9d9-4596-95cb-039aa281c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243184775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.243184775
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.5895605
Short name T411
Test name
Test status
Simulation time 36231867200 ps
CPU time 84.84 seconds
Started Aug 07 05:15:38 PM PDT 24
Finished Aug 07 05:17:03 PM PDT 24
Peak memory 201360 kb
Host smart-cf8aae23-1384-4008-8f39-9a5640304f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5895605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.5895605
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3502531229
Short name T740
Test name
Test status
Simulation time 4852450003 ps
CPU time 3.04 seconds
Started Aug 07 05:13:22 PM PDT 24
Finished Aug 07 05:13:25 PM PDT 24
Peak memory 201304 kb
Host smart-5c9d2a7f-67e6-44a1-96d7-1f7002077f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502531229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3502531229
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2268074687
Short name T8
Test name
Test status
Simulation time 5946620097 ps
CPU time 13.25 seconds
Started Aug 07 05:13:23 PM PDT 24
Finished Aug 07 05:13:36 PM PDT 24
Peak memory 201336 kb
Host smart-526b1ec0-f1c3-4d46-9f30-bff26e7f116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268074687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2268074687
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3834792532
Short name T674
Test name
Test status
Simulation time 273554542840 ps
CPU time 613.1 seconds
Started Aug 07 05:13:30 PM PDT 24
Finished Aug 07 05:23:43 PM PDT 24
Peak memory 212372 kb
Host smart-28a02ec3-7154-4951-b687-3b5b371a018a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834792532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3834792532
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3860535186
Short name T15
Test name
Test status
Simulation time 24039843645 ps
CPU time 25.92 seconds
Started Aug 07 05:13:28 PM PDT 24
Finished Aug 07 05:13:54 PM PDT 24
Peak memory 209720 kb
Host smart-c5a25756-e8b9-4d87-a9df-43842f5bc1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860535186 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3860535186
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4279593261
Short name T695
Test name
Test status
Simulation time 352020300 ps
CPU time 0.82 seconds
Started Aug 07 05:13:39 PM PDT 24
Finished Aug 07 05:13:40 PM PDT 24
Peak memory 201212 kb
Host smart-0d7e2ea0-56fb-479f-821f-494ac46820fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279593261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4279593261
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1708310167
Short name T711
Test name
Test status
Simulation time 188749656459 ps
CPU time 112.99 seconds
Started Aug 07 05:13:32 PM PDT 24
Finished Aug 07 05:15:26 PM PDT 24
Peak memory 201372 kb
Host smart-7b038159-4d02-4803-877b-3e5b4fe329df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708310167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1708310167
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1552690905
Short name T306
Test name
Test status
Simulation time 493246468903 ps
CPU time 372.3 seconds
Started Aug 07 05:13:32 PM PDT 24
Finished Aug 07 05:19:44 PM PDT 24
Peak memory 201368 kb
Host smart-43b4c4c7-1dee-42c4-a6cd-77e068f42a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552690905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1552690905
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1819438433
Short name T641
Test name
Test status
Simulation time 163204586001 ps
CPU time 63.25 seconds
Started Aug 07 05:13:30 PM PDT 24
Finished Aug 07 05:14:33 PM PDT 24
Peak memory 201452 kb
Host smart-4f302bbd-bf8a-4565-ac91-d0314e0162c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819438433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1819438433
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1311851992
Short name T9
Test name
Test status
Simulation time 329686189477 ps
CPU time 56.44 seconds
Started Aug 07 05:13:29 PM PDT 24
Finished Aug 07 05:14:26 PM PDT 24
Peak memory 201420 kb
Host smart-442f7549-3ecd-4702-ad81-ec9c7de8e1d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311851992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1311851992
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1170963109
Short name T620
Test name
Test status
Simulation time 327637830258 ps
CPU time 191.96 seconds
Started Aug 07 05:13:28 PM PDT 24
Finished Aug 07 05:16:40 PM PDT 24
Peak memory 201364 kb
Host smart-a7f4f155-2150-403a-bfc9-a78197e3d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170963109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1170963109
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2145170982
Short name T496
Test name
Test status
Simulation time 494292995488 ps
CPU time 91.29 seconds
Started Aug 07 05:13:29 PM PDT 24
Finished Aug 07 05:15:00 PM PDT 24
Peak memory 201384 kb
Host smart-1829dcf6-b381-4c33-a39f-ba220a5056b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145170982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2145170982
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1108549891
Short name T520
Test name
Test status
Simulation time 601894437849 ps
CPU time 160.85 seconds
Started Aug 07 05:13:33 PM PDT 24
Finished Aug 07 05:16:14 PM PDT 24
Peak memory 201364 kb
Host smart-7fb1cb66-f2f9-4273-9760-4ade48a3ba3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108549891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1108549891
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2303754487
Short name T457
Test name
Test status
Simulation time 122807071540 ps
CPU time 464.5 seconds
Started Aug 07 05:13:40 PM PDT 24
Finished Aug 07 05:21:25 PM PDT 24
Peak memory 201856 kb
Host smart-f2f72368-8a21-423d-8bfe-9ee5b72cb5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303754487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2303754487
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2670723897
Short name T451
Test name
Test status
Simulation time 36956395480 ps
CPU time 17.08 seconds
Started Aug 07 05:13:39 PM PDT 24
Finished Aug 07 05:13:56 PM PDT 24
Peak memory 201344 kb
Host smart-3cf5cd81-e3cf-4e19-aca8-d6027fe2f20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670723897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2670723897
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.582523699
Short name T600
Test name
Test status
Simulation time 4271612067 ps
CPU time 6.23 seconds
Started Aug 07 05:13:39 PM PDT 24
Finished Aug 07 05:13:45 PM PDT 24
Peak memory 201300 kb
Host smart-15505f60-cf1d-45b9-ae67-6443d6755ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582523699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.582523699
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2096413098
Short name T613
Test name
Test status
Simulation time 6157809281 ps
CPU time 8.57 seconds
Started Aug 07 05:13:29 PM PDT 24
Finished Aug 07 05:13:38 PM PDT 24
Peak memory 201320 kb
Host smart-de0d584e-a074-4322-b044-24b0c40679b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096413098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2096413098
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.752469067
Short name T13
Test name
Test status
Simulation time 42716352338 ps
CPU time 23.44 seconds
Started Aug 07 05:13:40 PM PDT 24
Finished Aug 07 05:14:04 PM PDT 24
Peak memory 217984 kb
Host smart-afa9c728-c50f-4f4c-99d3-ca3d5e921683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752469067 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.752469067
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2532507848
Short name T644
Test name
Test status
Simulation time 347727514 ps
CPU time 1.43 seconds
Started Aug 07 05:13:52 PM PDT 24
Finished Aug 07 05:13:54 PM PDT 24
Peak memory 201208 kb
Host smart-50cbf76c-954c-4a2e-8df5-9bf477175369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532507848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2532507848
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3200215861
Short name T79
Test name
Test status
Simulation time 181808366589 ps
CPU time 379.06 seconds
Started Aug 07 05:13:45 PM PDT 24
Finished Aug 07 05:20:04 PM PDT 24
Peak memory 201408 kb
Host smart-facc7f32-7c2b-49ea-9392-f43b39e61f3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200215861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3200215861
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1124828144
Short name T48
Test name
Test status
Simulation time 167601521067 ps
CPU time 106.1 seconds
Started Aug 07 05:13:39 PM PDT 24
Finished Aug 07 05:15:25 PM PDT 24
Peak memory 201428 kb
Host smart-9e3f484e-a013-4821-8fb0-7755ba659d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124828144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1124828144
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.482943153
Short name T776
Test name
Test status
Simulation time 329472329526 ps
CPU time 210.87 seconds
Started Aug 07 05:13:46 PM PDT 24
Finished Aug 07 05:17:17 PM PDT 24
Peak memory 201400 kb
Host smart-684b90ee-48fa-4222-acf1-134bf22783fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=482943153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.482943153
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2693950226
Short name T274
Test name
Test status
Simulation time 504002987242 ps
CPU time 549.17 seconds
Started Aug 07 05:13:38 PM PDT 24
Finished Aug 07 05:22:47 PM PDT 24
Peak memory 201348 kb
Host smart-87a79dae-1b5e-44cf-8a07-620eb8b3cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693950226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2693950226
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3564506303
Short name T556
Test name
Test status
Simulation time 164726521415 ps
CPU time 49.27 seconds
Started Aug 07 05:13:38 PM PDT 24
Finished Aug 07 05:14:28 PM PDT 24
Peak memory 201340 kb
Host smart-68edb61e-bb5d-405d-81c2-5ef0943f2207
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564506303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3564506303
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2506762930
Short name T345
Test name
Test status
Simulation time 622300248676 ps
CPU time 720.27 seconds
Started Aug 07 05:13:45 PM PDT 24
Finished Aug 07 05:25:46 PM PDT 24
Peak memory 201428 kb
Host smart-5fe82ae5-bfa8-4556-901f-82d7480ea7c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506762930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2506762930
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1220189853
Short name T118
Test name
Test status
Simulation time 602320625301 ps
CPU time 669.11 seconds
Started Aug 07 05:13:43 PM PDT 24
Finished Aug 07 05:24:53 PM PDT 24
Peak memory 201440 kb
Host smart-b017ba46-98ec-4528-b501-a9f37e85cf04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220189853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1220189853
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.616036626
Short name T468
Test name
Test status
Simulation time 151200722365 ps
CPU time 723.54 seconds
Started Aug 07 05:13:53 PM PDT 24
Finished Aug 07 05:25:57 PM PDT 24
Peak memory 201840 kb
Host smart-b32159a4-00cf-4f97-8cdb-2a77ae0a1134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616036626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.616036626
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4006120977
Short name T545
Test name
Test status
Simulation time 44063696502 ps
CPU time 25.04 seconds
Started Aug 07 05:13:49 PM PDT 24
Finished Aug 07 05:14:14 PM PDT 24
Peak memory 201236 kb
Host smart-396fb785-5eec-438b-80a0-66c8401bf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006120977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4006120977
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.34580783
Short name T713
Test name
Test status
Simulation time 4808704489 ps
CPU time 12.85 seconds
Started Aug 07 05:13:45 PM PDT 24
Finished Aug 07 05:13:58 PM PDT 24
Peak memory 201240 kb
Host smart-e8ec2884-47e8-4353-802a-996cb6be01ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34580783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.34580783
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4274476617
Short name T408
Test name
Test status
Simulation time 5577608730 ps
CPU time 7.49 seconds
Started Aug 07 05:13:39 PM PDT 24
Finished Aug 07 05:13:47 PM PDT 24
Peak memory 201348 kb
Host smart-fe9802a5-2e58-404d-ad7a-8cc519e54be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274476617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4274476617
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.259141401
Short name T702
Test name
Test status
Simulation time 3848006321 ps
CPU time 10.21 seconds
Started Aug 07 05:13:48 PM PDT 24
Finished Aug 07 05:13:59 PM PDT 24
Peak memory 201272 kb
Host smart-4de0a8c1-b31b-49d7-a18f-587cb7803fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259141401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.259141401
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1926042445
Short name T221
Test name
Test status
Simulation time 42370245563 ps
CPU time 90.41 seconds
Started Aug 07 05:13:52 PM PDT 24
Finished Aug 07 05:15:22 PM PDT 24
Peak memory 217900 kb
Host smart-9eb3217e-0a87-42e4-83ec-fabe6f290b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926042445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1926042445
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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