Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7001	1			T4	20		T5	8		T7	20
testmodes[AdcCtrlTestmodeNormal]	5673	1			T1	1		T3	3		T5	5
testmodes[AdcCtrlTestmodeLowpower]	5783	1			T1	1		T2	3		T5	33
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3712	1			T4	19		T5	4		T7	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1835	1			T5	3		T8	4		T9	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1344	1			T14	17		T47	10		T46	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1808	1			T5	4		T8	3		T9	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2078	1			T3	2		T5	1		T8	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1451	1			T1	1		T14	19		T47	30
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1380	1			T14	18		T47	19		T46	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1419	1			T5	1		T12	1		T14	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2733	1			T2	2		T5	32		T6	11