Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23339

1

T1

23

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3391

1

T1

5

T2

15

T3

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20653

1

T1

28

T3

45

T4

20

auto[1]

6077

1

T2

16

T3

1

T9

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T221	8		T222	4		-	-
values[0]	51	1			T223	28		T224	23		-	-
values[1]	546	1			T3	1		T13	9		T149	2
values[2]	875	1			T3	45		T46	1		T50	1
values[3]	479	1			T46	4		T225	1		T226	1
values[4]	751	1			T12	21		T46	7		T50	1
values[5]	2838	1			T2	14		T15	1		T48	1
values[6]	901	1			T1	23		T2	1		T5	20
values[7]	588	1			T60	14		T78	2		T32	16
values[8]	669	1			T1	5		T2	1		T51	23
values[9]	1514	1			T11	39		T13	5		T48	1
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T3	1		T13	9		T50	1
values[1]	663	1			T3	45		T46	1		T67	17
values[2]	626	1			T12	21		T46	4		T160	14
values[3]	2956	1			T15	1		T153	3		T126	2
values[4]	879	1			T2	14		T5	20		T9	16
values[5]	637	1			T1	23		T2	1		T154	27
values[6]	680	1			T1	5		T55	11		T45	3
values[7]	748	1			T2	1		T48	1		T51	23
values[8]	978	1			T11	39		T54	12		T55	22
values[9]	264	1			T13	5		T38	16		T44	11
minimum	17524	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	1		T13	9		T44	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	1		T149	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	9		T67	1		T227	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	15		T46	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	12		T46	3		T228	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T160	1		T225	1		T229	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T15	1		T153	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T46	4		T51	1		T54	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	9		T50	1		T54	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	14		T9	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	12		T2	1		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T154	14		T33	3		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T55	9		T60	14		T78	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	3		T45	2		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T150	1		T160	1		T33	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	1		T48	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	11		T57	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T11	24		T54	12		T42	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T13	5		T230	23		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T38	16		T44	11		T69	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17397	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T68	2		T231	7		T232	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	1		T160	9		T29	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	8		T67	16		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	13		T159	11		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	9		T46	1		T228	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T160	13		T229	6		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T41	19		T149	11		T31	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	3		T51	1		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	11		T55	4		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	15		T159	13		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	11		T32	9		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T166	10		T234	11		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	2		T78	17		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	2		T45	1		T78	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T160	12		T236	11		T151	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	11		T67	8		T194	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	11		T35	6		T163	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	15		T42	24		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T230	18		T190	1		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T69	4		T177	14		T238	26
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T35	1		T42	2		T198	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	3		T222	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T223	15		T224	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	1		T13	9		T68	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	1		T150	1		T58	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	9		T44	9		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	15		T46	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	3		T226	1		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T225	1		T239	10		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	12		T50	1		T154	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	4		T54	10		T44	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T15	1		T153	3		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	14		T48	1		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	12		T2	1		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	1		T45	2		T154	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T60	14		T32	7		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T78	1		T168	1		T163	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T55	9		T78	14		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	3		T2	1		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T13	5		T55	11		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	489	1			T11	24		T48	1		T54	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T221	5		T222	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T223	13		T224	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T68	2		T231	7		T232	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T149	1		T58	3		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	8		T67	16		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	13		T159	11		T160	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	1		T241	1		T189	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T239	7		T233	9		T242	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	9		T149	11		T228	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	3		T159	18		T160	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T41	19		T45	1		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T51	1		T58	11		T229	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	11		T5	11		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	15		T45	1		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	9		T152	13		T172	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T78	1		T163	12		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T55	2		T78	17		T160	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	2		T51	11		T244	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T55	11		T35	6		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T11	15		T42	24		T67	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T13	1		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	1		T149	2		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	9		T67	17		T227	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	14		T46	1		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	10		T46	2		T228	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T160	14		T225	1		T229	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T15	1		T153	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T46	6		T51	2		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	12		T50	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T9	16		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	12		T2	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	1		T33	1		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T55	3		T60	1		T78	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	3		T45	2		T78	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T150	1		T160	13		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	1		T48	1		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	12		T57	1		T35	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T11	17		T54	1		T42	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T13	1		T230	20		T190	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	1		T44	1		T69	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17518	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	8		T44	8		T68	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	18		T58	5		T212	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	8		T227	3		T245	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	14		T58	2		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	11		T46	2		T228	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T229	4		T246	7		T165	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T37	27		T43	28		T60	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T46	1		T54	9		T44	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	8		T54	14		T55	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	13		T51	11		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	11		T154	12		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T154	13		T33	2		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T55	8		T60	13		T78	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	2		T45	1		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	8		T236	14		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	11		T65	8		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	10		T248	10		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T11	22		T54	11		T42	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T13	4		T230	21		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T38	15		T44	10		T69	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T249	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T221	6		T222	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T223	14		T224	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T13	1		T68	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T149	2		T150	1		T58	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	9		T44	1		T67	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	14		T46	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	2		T226	1		T148	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T225	1		T239	8		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	10		T50	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T46	6		T54	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T15	1		T153	3		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T48	1		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	12		T2	1		T5	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	16		T45	2		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T60	1		T32	10		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T78	2		T168	1		T163	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T55	3		T78	18		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	3		T2	1		T51	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T13	1		T55	12		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T11	17		T48	1		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T223	14		T224	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	8		T68	3		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T58	5		T212	1		T240	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	8		T44	8		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	14		T29	18		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T46	2		T245	5		T189	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T239	9		T250	10		T242	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	11		T154	6		T228	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T46	1		T54	9		T44	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T37	27		T43	28		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	13		T51	11		T60	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	11		T5	8		T54	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	1		T154	13		T161	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T60	13		T32	6		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T163	10		T243	12		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T55	8		T78	13		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	2		T51	11		T65	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T13	4		T55	10		T33	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T11	22		T54	11		T38	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23438

1

T1

28

T2

16

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3292

1

T3

28

T5

20

T11

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20462

1

T1

5

T2

2

T3

18

auto[1]

6268

1

T1

23

T2

14

T3

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	430	1			T14	2		T47	1		T46	5
values[0]	66	1			T157	24		T194	15		T162	1
values[1]	752	1			T1	23		T2	1		T9	16
values[2]	3185	1			T3	45		T5	20		T15	1
values[3]	725	1			T2	14		T50	1		T51	23
values[4]	705	1			T55	22		T38	16		T65	12
values[5]	629	1			T2	1		T3	1		T11	28
values[6]	533	1			T46	5		T54	22		T198	1
values[7]	586	1			T1	5		T13	9		T46	7
values[8]	723	1			T11	11		T54	15		T42	26
values[9]	1320	1			T12	21		T57	1		T60	14
minimum	17076	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1022	1			T1	23		T2	1		T9	16
values[1]	3185	1			T2	14		T3	45		T5	20
values[2]	632	1			T51	23		T35	7		T39	1
values[3]	679	1			T3	1		T11	28		T55	22
values[4]	660	1			T2	1		T13	5		T46	5
values[5]	569	1			T54	12		T44	9		T161	1
values[6]	674	1			T1	5		T11	11		T13	9
values[7]	785	1			T54	15		T42	26		T60	14
values[8]	756	1			T12	21		T57	1		T149	9
values[9]	249	1			T78	2		T159	12		T58	12
minimum	17519	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T1	12		T2	1		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T154	14		T157	12		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1692	1			T2	14		T3	9		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	15		T5	9		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	1		T39	1		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T51	12		T45	2		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T11	15		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T55	11		T65	12		T58	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	1		T13	5		T46	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T55	7		T45	3		T158	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T54	12		T161	1		T152	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	9		T247	9		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	3		T13	9		T46	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	9		T42	12		T61	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T42	13		T60	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	15		T61	11		T154	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T57	1		T33	9		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	12		T149	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T78	1		T159	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T58	9		T253	1		T240	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17397	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	11		T9	15		T55	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T157	12		T194	14		T27	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T3	8		T41	19		T67	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	13		T5	11		T159	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	6		T58	2		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	11		T45	1		T229	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	13		T161	13		T229	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T55	11		T58	11		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	1		T160	12		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	4		T45	1		T228	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T152	9		T231	7		T254	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T247	6		T230	11		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T46	3		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	2		T42	11		T67	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T42	13		T149	5		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T236	11		T255	9		T19	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T244	1		T256	13		T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	9		T149	7		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T78	1		T159	11		T252	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T58	3		T253	15		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	1		T42	2		T198	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T14	2		T47	1		T46	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T256	1		T257	1		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T157	12		T194	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	12		T2	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T154	14		T150	1		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T3	9		T15	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	15		T5	9		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	14		T35	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	1		T51	12		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	16		T194	1		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T55	11		T65	12		T58	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T3	1		T11	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T55	7		T45	3		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	4		T54	22		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T158	12		T247	9		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	3		T13	9		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T42	12		T44	9		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T42	13		T149	1		T258	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	9		T54	15		T61	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T57	1		T60	14		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T12	12		T61	11		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T177	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T157	12		T194	14		T70	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	11		T9	15		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T228	3		T69	4		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T3	8		T41	19		T67	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	13		T5	11		T159	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	6		T68	1		T254	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	11		T45	1		T163	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T161	13		T58	2		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T55	11		T58	11		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	13		T160	12		T247	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T55	4		T45	1		T228	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T46	1		T169	9		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T247	6		T230	11		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	2		T46	3		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T42	11		T259	2		T260	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T42	13		T149	5		T36	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	2		T67	8		T149	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T78	1		T159	11		T244	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T12	9		T149	6		T160	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2