Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23368

1

T1

23

T2

1

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3362

1

T1

5

T2

15

T3

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20599

1

T1

28

T3

45

T4

20

auto[1]

6131

1

T2

16

T3

1

T9

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	376	1			T11	28		T57	1		T35	7
values[0]	18	1			T249	18		-	-		-	-
values[1]	607	1			T3	1		T13	9		T149	2
values[2]	800	1			T3	45		T46	1		T50	1
values[3]	585	1			T12	21		T228	31		T225	1
values[4]	669	1			T46	11		T50	1		T54	10
values[5]	2893	1			T2	14		T15	1		T48	1
values[6]	778	1			T2	1		T5	20		T9	16
values[7]	720	1			T1	23		T45	3		T60	14
values[8]	700	1			T1	5		T2	1		T55	11
values[9]	1078	1			T11	11		T13	5		T48	1
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	587	1			T3	1		T13	9		T46	1
values[1]	711	1			T3	45		T67	17		T159	12
values[2]	644	1			T12	21		T46	4		T160	14
values[3]	2906	1			T15	1		T153	3		T126	2
values[4]	893	1			T2	14		T5	20		T9	16
values[5]	619	1			T1	23		T2	1		T154	27
values[6]	671	1			T1	5		T55	11		T45	3
values[7]	762	1			T2	1		T51	23		T65	9
values[8]	1063	1			T11	39		T13	5		T48	1
values[9]	169	1			T44	11		T69	12		T230	41
minimum	17705	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T13	9		T44	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	1		T50	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	9		T67	1		T227	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	15		T159	1		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	12		T46	3		T228	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	1		T229	5		T246	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T15	1		T153	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T46	4		T51	1		T54	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	9		T50	1		T54	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	14		T9	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	12		T2	1		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	14		T33	3		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T55	9		T60	14		T78	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	3		T45	2		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T158	12		T150	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	1		T51	12		T65	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	5		T55	11		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T11	24		T48	1		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T230	23		T190	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T44	11		T69	8		T238	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17449	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T240	22		T291	1		T237	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T68	2		T231	7		T232	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	1		T160	9		T29	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	8		T67	16		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	13		T159	11		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	9		T46	1		T228	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T160	13		T229	6		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T41	19		T149	11		T31	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	3		T51	1		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	11		T55	4		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	15		T159	13		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	11		T32	9		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T166	10		T234	11		T235	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	2		T78	17		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	2		T45	1		T78	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T160	12		T236	11		T151	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T51	11		T67	8		T194	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T55	11		T35	6		T163	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	15		T42	24		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T230	18		T190	1		T311	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T69	4		T238	14		T327	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T240	10		T237	16		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T57	1		T35	1		T152	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	15		T42	25		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T249	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T13	9		T68	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T149	1		T150	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	9		T44	9		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	15		T46	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	12		T228	12		T244	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T225	1		T229	5		T165	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	3		T50	1		T60	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	4		T54	10		T44	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T15	1		T153	3		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	14		T48	1		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	1		T5	9		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	1		T154	14		T161	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	12		T60	14		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	2		T78	1		T247	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T55	9		T78	14		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	3		T2	1		T65	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	5		T55	11		T33	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T11	9		T48	1		T51	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T35	6		T70	1		T230	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	13		T42	24		T290	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T249	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T68	2		T231	7		T232	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T149	1		T160	9		T58	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	8		T67	16		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	13		T159	11		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	9		T228	19		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T229	6		T239	7		T233	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	1		T149	11		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	3		T159	18		T160	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T41	19		T45	1		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	1		T229	9		T255	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	11		T55	4		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	15		T161	13		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	11		T32	9		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	1		T78	1		T247	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T55	2		T78	17		T160	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	2		T67	8		T244	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T55	11		T151	5		T163	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	2		T51	11		T194	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T13	1		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	1		T50	1		T149	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T67	17		T227	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	14		T159	12		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	10		T46	2		T228	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T160	14		T229	7		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T15	1		T153	3		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	6		T51	2		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	12		T50	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T9	16		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	12		T2	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T154	1		T33	1		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T55	3		T60	1		T78	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	3		T45	2		T78	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T158	1		T150	1		T160	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	1		T51	12		T65	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T55	12		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T11	17		T48	1		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T230	20		T190	2		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T44	1		T69	8		T238	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17587	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T240	11		T291	1		T237	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	8		T44	8		T68	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	18		T58	5		T212	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	8		T227	3		T314	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	14		T58	2		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	11		T46	2		T228	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T229	4		T246	7		T165	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T37	27		T43	28		T60	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T46	1		T54	9		T44	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	8		T54	14		T55	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	13		T51	11		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	11		T154	12		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T154	13		T33	2		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T55	8		T60	13		T78	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	2		T45	1		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T158	11		T33	8		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	11		T65	8		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	4		T55	10		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T11	22		T54	11		T38	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T230	21		T311	10		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T44	10		T69	4		T238	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T271	11		T21	1		T239	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T240	21		T237	16		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T57	1		T35	7		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	14		T42	26		T290	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T249	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	1		T13	1		T68	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	2		T150	1		T160	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	9		T44	1		T67	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	14		T46	1		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	10		T228	20		T244	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T225	1		T229	7		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	2		T50	1		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	6		T54	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T15	1		T153	3		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T48	1		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	1		T5	12		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	16		T154	1		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	12		T60	1		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	2		T78	2		T247	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T55	3		T78	18		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	3		T2	1		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	1		T55	12		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T11	3		T48	1		T51	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T152	9		T230	12		T21	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	14		T42	23		T322	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T249	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	8		T68	3		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T58	5		T212	1		T240	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	8		T44	8		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	14		T29	18		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	11		T228	11		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T229	4		T165	9		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	2		T60	15		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T46	1		T54	9		T44	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T37	27		T43	28		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	13		T51	11		T60	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	8		T54	14		T55	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T154	13		T161	17		T33	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	11		T60	13		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	1		T247	8		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T55	8		T78	13		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	2		T65	8		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	4		T55	10		T33	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T11	8		T51	11		T54	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22