Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22861

1

T1

5

T3

28

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3869

1

T1

23

T2

16

T3

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20732

1

T1

5

T2

1

T3

46

auto[1]

5998

1

T1

23

T2

15

T9

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	163	1			T51	2		T45	3		T198	1
values[0]	9	1			T291	1		T315	1		T328	5
values[1]	719	1			T48	1		T51	23		T54	10
values[2]	2942	1			T2	1		T3	29		T13	5
values[3]	630	1			T50	1		T57	1		T39	1
values[4]	638	1			T13	9		T48	1		T50	1
values[5]	648	1			T3	17		T78	2		T158	3
values[6]	910	1			T1	5		T2	15		T46	7
values[7]	878	1			T5	20		T55	11		T42	26
values[8]	741	1			T1	23		T9	16		T11	11
values[9]	946	1			T11	28		T12	21		T55	22
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	694	1			T3	28		T48	1		T50	1
values[1]	2997	1			T2	1		T3	1		T13	5
values[2]	591	1			T13	9		T50	2		T57	1
values[3]	591	1			T48	1		T35	7		T44	11
values[4]	654	1			T2	14		T3	17		T54	12
values[5]	950	1			T1	5		T2	1		T5	20
values[6]	860	1			T42	26		T60	14		T65	9
values[7]	688	1			T1	23		T9	16		T11	11
values[8]	884	1			T11	28		T12	21		T45	3
values[9]	95	1			T51	2		T198	1		T230	18
minimum	17726	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	15		T50	1		T58	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	1		T51	12		T54	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T15	1		T153	3		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T3	1		T13	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	9		T61	14		T160	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	9		T50	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T35	1		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	11		T78	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T194	1		T162	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	14		T3	9		T54	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	3		T5	9		T55	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T46	4		T54	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T65	9		T149	1		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T42	13		T60	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	1		T51	12		T55	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	12		T9	1		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	15		T65	12		T194	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	12		T45	2		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T51	1		T198	1		T329	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T230	10		T241	1		T36	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17431	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T155	9		T163	1		T251	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	13		T58	11		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	11		T67	16		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T41	19		T31	14		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T55	4		T163	12		T255	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T160	22		T244	10		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T159	5		T230	10		T271	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	6		T67	8		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T78	1		T244	1		T252	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T169	9		T283	1		T177	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	8		T42	11		T78	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	2		T5	11		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	3		T45	1		T152	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T149	1		T58	5		T247	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T42	13		T149	6		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T55	11		T229	5		T302	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	11		T9	15		T11	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	13		T194	14		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	9		T45	1		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T51	1		T300	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T230	8		T241	1		T36	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T155	7		T163	13		T21	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T51	1		T198	1		T165	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T45	2		T33	9		T230	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T291	1		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T328	3		T296	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T58	12		T228	11		T152	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T48	1		T51	12		T54	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T3	15		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T3	1		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	9		T61	14		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	1		T57	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	1		T35	1		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	9		T50	1		T44	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	1		T169	1		T261	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	9		T78	1		T158	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	3		T149	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T2	15		T46	4		T54	27
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	9		T55	9		T65	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	13		T60	14		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T46	1		T51	12		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	12		T9	1		T11	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	15		T55	11		T65	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	12		T159	1		T27	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T51	1		T330	17		T321	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T45	1		T230	8		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T328	2		T296	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T58	11		T228	10		T205	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	11		T67	16		T155	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T3	13		T41	19		T31	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	4		T159	11		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T160	9		T244	10		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T159	5		T230	10		T271	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	6		T67	8		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T78	17		T244	1		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T169	9		T276	11		T283	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	8		T78	1		T247	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	2		T149	5		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	3		T42	11		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	11		T55	2		T149	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T42	13		T149	6		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T247	3		T229	5		T285	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	11		T9	15		T11	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	13		T55	11		T194	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	9		T159	13		T27	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	14		T50	1		T58	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	1		T51	12		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T15	1		T153	3		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	1		T3	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T44	1		T61	1		T160	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	1		T50	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	1		T35	7		T67	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	1		T78	2		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T194	1		T162	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T3	9		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	3		T5	12		T55	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	1		T46	6		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	1		T149	2		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T42	14		T60	1		T149	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	1		T51	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	12		T9	16		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	14		T65	1		T194	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	10		T45	2		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T51	2		T198	1		T329	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T230	9		T241	2		T36	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17539	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T155	8		T163	14		T251	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	14		T58	11		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	11		T54	9		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T37	27		T38	15		T43	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	4		T55	6		T60	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	8		T61	13		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T13	8		T60	5		T61	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	13		T157	11		T161	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	10		T241	9		T21	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T261	13		T258	12		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	13		T3	8		T54	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	2		T5	8		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T46	1		T54	14		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T65	8		T158	11		T58	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T42	12		T60	13		T158	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	11		T55	10		T229	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	11		T11	8		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	14		T65	11		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	11		T45	1		T33	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T230	9		T36	2		T24	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T272	12		T238	13		T292	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T155	8		T287	5		T21	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T51	2		T198	1		T165	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T45	2		T33	1		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T291	1		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T328	3		T296	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T58	12		T228	11		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T48	1		T51	12		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T3	14		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T3	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T44	1		T61	1		T160	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	1		T57	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	1		T35	7		T67	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T50	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T156	1		T169	10		T261	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	9		T78	2		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	3		T149	6		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	2		T46	6		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	12		T55	3		T65	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T42	14		T60	1		T149	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	1		T51	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	12		T9	16		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	14		T55	12		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	10		T159	14		T27	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T165	8		T330	12		T331	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T45	1		T33	8		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T328	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T58	11		T228	10		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	11		T54	9		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T3	14		T37	27		T38	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	4		T55	6		T60	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T44	8		T61	13		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T61	10		T154	6		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	13		T157	11		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	8		T44	10		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T261	13		T276	9		T299	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	8		T158	2		T247	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T29	18		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	13		T46	1		T54	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	8		T55	8		T65	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	12		T60	13		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T51	11		T158	11		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	11		T11	8		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	14		T55	10		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	11		T27	3		T166	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22