Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23363

1

T1

28

T2

16

T3

18

auto[ADC_CTRL_FILTER_COND_OUT]

3367

1

T3

28

T5

20

T11

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20360

1

T1

5

T2

1

T3

18

auto[1]

6370

1

T1

23

T2

15

T3

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	684	1			T12	21		T14	2		T47	1
values[0]	41	1			T157	24		T256	1		T257	1
values[1]	801	1			T1	23		T2	1		T9	16
values[2]	3197	1			T3	45		T5	20		T15	1
values[3]	681	1			T2	14		T50	1		T51	23
values[4]	687	1			T55	22		T38	16		T65	12
values[5]	667	1			T2	1		T3	1		T11	28
values[6]	515	1			T46	4		T54	22		T198	1
values[7]	634	1			T1	5		T13	9		T46	7
values[8]	652	1			T11	11		T54	15		T42	26
values[9]	1095	1			T60	14		T78	2		T160	14
minimum	17076	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T1	23		T2	1		T51	12
values[1]	3184	1			T2	14		T3	45		T5	20
values[2]	652	1			T51	23		T35	7		T39	1
values[3]	728	1			T3	1		T11	28		T55	22
values[4]	658	1			T2	1		T13	5		T46	5
values[5]	480	1			T54	12		T158	12		T161	1
values[6]	745	1			T1	5		T11	11		T13	9
values[7]	669	1			T54	15		T42	26		T60	14
values[8]	901	1			T12	21		T57	1		T78	2
values[9]	196	1			T159	12		T252	16		T253	16
minimum	17652	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	12		T2	1		T51	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T154	14		T194	1		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T2	14		T3	9		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T3	15		T5	9		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T35	1		T39	1		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	12		T194	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	1		T38	16		T65	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	15		T55	11		T58	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	1		T46	4		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	5		T54	10		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T54	12		T161	1		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T158	12		T247	9		T231	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	3		T11	9		T13	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	1		T51	1		T42	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T42	13		T60	14		T19	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	15		T61	11		T154	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T57	1		T78	1		T33	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	12		T149	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T159	1		T252	1		T262	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T253	1		T256	1		T240	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17423	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T55	9		T18	1		T245	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	11		T78	17		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T194	14		T27	8		T228	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T3	8		T41	19		T67	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	13		T5	11		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	6		T45	1		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	11		T152	13		T290	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T161	13		T163	13		T229	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	13		T55	11		T58	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	1		T55	4		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	1		T247	3		T228	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T230	11		T234	11		T284	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T247	6		T231	7		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	2		T11	2		T46	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	1		T42	11		T67	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T42	13		T19	11		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	6		T236	11		T255	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T78	1		T244	1		T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	9		T149	6		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T159	11		T252	15		T262	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T253	15		T256	13		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	15		T35	1		T42	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T55	2		T330	12		T332	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	462	1			T14	2		T47	1		T46	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T12	12		T149	1		T256	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T157	12		T256	1		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	12		T2	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T55	9		T154	14		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T3	9		T15	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T3	15		T5	9		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	14		T35	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	1		T51	12		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T38	16		T65	12		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	11		T58	12		T17	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T3	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	15		T13	5		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	3		T54	12		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T54	10		T198	1		T158	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	3		T13	9		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	1		T51	1		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	9		T42	13		T61	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T54	15		T61	11		T154	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T60	14		T78	1		T33	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T160	1		T236	15		T58	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16960	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T159	11		T252	15		T262	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T12	9		T149	6		T256	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T157	12		T177	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	11		T9	15		T78	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T55	2		T194	14		T228	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T3	8		T41	19		T67	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T3	13		T5	11		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	6		T45	1		T68	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	11		T163	12		T235	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T161	13		T58	2		T234	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T55	11		T58	11		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T55	4		T160	12		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	13		T45	1		T247	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T46	1		T230	11		T21	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T247	6		T231	7		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	2		T46	3		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	1		T42	11		T67	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	2		T42	13		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T149	6		T240	10		T322	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T78	1		T244	1		T235	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T160	13		T236	11		T58	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	12		T2	1		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T154	1		T194	15		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	1		T3	9		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T3	14		T5	12		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	7		T39	1		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	12		T194	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T38	1		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	14		T55	12		T58	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T46	3		T55	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	1		T54	1		T45	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T54	1		T161	1		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T158	1		T247	7		T231	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	3		T11	3		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T50	1		T51	2		T42	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T42	14		T60	1		T19	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T54	1		T61	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T57	1		T78	2		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	10		T149	7		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T159	12		T252	16		T262	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T253	16		T256	14		T240	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17547	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T55	3		T18	1		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	11		T51	11		T44	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	13		T27	3		T69	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T2	13		T3	8		T37	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T3	14		T5	8		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	1		T33	2		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	11		T152	11		T287	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	15		T65	11		T161	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	14		T55	10		T58	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T46	2		T55	6		T44	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T13	4		T54	9		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	11		T230	10		T234	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T158	11		T247	8		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	2		T11	8		T13	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T42	11		T44	8		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	12		T60	13		T19	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T54	14		T61	10		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T33	8		T254	1		T261	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	11		T58	5		T166	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T262	4		T204	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T240	13		T165	8		T333	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T334	10		T335	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T55	8		T245	13		T322	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	504	1			T14	2		T47	1		T46	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T12	10		T149	7		T256	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T157	13		T256	1		T177	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	12		T2	1		T9	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T55	3		T154	1		T194	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T3	9		T15	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T3	14		T5	12		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T35	7		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	1		T51	12		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	1		T65	1		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T55	12		T58	12		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T3	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	14		T13	1		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	2		T54	1		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T54	1		T198	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	3		T13	1		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	1		T51	2		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	3		T42	14		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T54	1		T61	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T60	1		T78	2		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T160	14		T236	12		T58	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17076	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T262	4		T334	2		T259	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T12	11		T256	10		T235	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T157	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	11		T51	11		T44	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T55	8		T154	13		T69	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T3	8		T37	27		T43	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	14		T5	8		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	13		T45	1		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	11		T152	9		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T38	15		T65	11		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T55	10		T58	11		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	6		T44	8		T60	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	14		T13	4		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	2		T54	11		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T54	9		T158	11		T247	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	2		T13	8		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T42	11		T44	8		T227	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	8		T42	12		T61	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	14		T61	10		T154	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T60	13		T33	8		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T236	14		T58	5		T166	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22