Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23276

1

T1

28

T2

14

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T2

2

T3

18

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20432

1

T1

23

T2

2

T3

1

auto[1]

6298

1

T1

5

T2

14

T3

45

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	295	1			T244	16		T70	6		T261	5
values[0]	16	1			T156	1		T336	15		-	-
values[1]	751	1			T3	1		T48	1		T50	1
values[2]	512	1			T3	17		T46	1		T50	1
values[3]	560	1			T3	28		T46	7		T51	12
values[4]	801	1			T9	16		T13	9		T35	7
values[5]	604	1			T1	23		T2	14		T12	21
values[6]	815	1			T2	1		T11	28		T51	2
values[7]	573	1			T1	5		T55	11		T60	16
values[8]	953	1			T2	1		T5	20		T44	9
values[9]	3344	1			T11	11		T13	5		T15	1
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T3	18		T50	1		T54	12
values[1]	473	1			T46	1		T51	12		T42	26
values[2]	661	1			T3	28		T46	7		T35	7
values[3]	742	1			T9	16		T13	9		T46	4
values[4]	750	1			T1	23		T2	14		T12	21
values[5]	630	1			T1	5		T2	1		T11	28
values[6]	2866	1			T15	1		T153	3		T126	2
values[7]	960	1			T2	1		T5	20		T39	1
values[8]	990	1			T11	11		T13	5		T48	1
values[9]	209	1			T244	13		T318	1		T20	1
minimum	17751	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T50	1		T54	12		T158	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	10		T157	12		T236	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T67	1		T158	12		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	1		T51	12		T42	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	15		T45	3		T78	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	4		T35	1		T61	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	1		T46	3		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	9		T54	15		T44	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	12		T2	14		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T54	10		T55	11		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	3		T11	15		T42	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T51	1		T44	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T15	1		T153	3		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	16		T160	1		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T39	1		T60	14		T58	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	1		T5	9		T65	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	9		T13	5		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T51	12		T194	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T20	1		T285	1		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T244	3		T318	1		T319	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17461	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T161	1		T166	15		T152	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	9		T272	13		T214	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	8		T157	12		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T67	8		T159	5		T252	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T42	13		T228	10		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	13		T45	1		T78	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	3		T35	6		T194	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	15		T46	1		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T152	13		T164	7		T256	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	11		T12	9		T67	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T55	11		T149	6		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	2		T11	13		T42	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T51	1		T160	9		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T55	2		T41	19		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T160	12		T58	3		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T58	11		T166	13		T228	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	11		T78	1		T161	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	2		T55	4		T27	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T51	11		T160	13		T244	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T285	11		T279	4		T324	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T244	10		T319	10		T337	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T166	10		T234	9		T271	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T261	5		T20	1		T279	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T244	11		T70	5		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T336	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T156	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	1		T50	1		T54	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T154	13		T157	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T50	1		T158	12		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	9		T46	1		T42	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	15		T45	3		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	4		T51	12		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T38	16		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	9		T35	1		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	12		T2	14		T12	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T54	15		T55	11		T44	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	15		T42	12		T65	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T51	1		T54	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	3		T55	9		T154	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T60	16		T150	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T44	9		T60	14		T58	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T5	9		T65	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T11	9		T13	5		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T51	12		T194	1		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T279	4		T324	1		T335	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T244	5		T70	1		T319	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T336	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T255	9		T272	13		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T157	12		T236	11		T166	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T32	9		T214	2		T300	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T3	8		T42	13		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	13		T45	1		T67	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T46	3		T69	4		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	15		T45	1		T78	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	6		T194	14		T254	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	11		T12	9		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T55	11		T149	6		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	13		T42	11		T67	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	1		T160	9		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	2		T55	2		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T160	12		T58	3		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T58	11		T166	13		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	11		T78	1		T161	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T11	2		T55	4		T41	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T51	11		T160	13		T151	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	1		T54	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	10		T157	13		T236	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T67	9		T158	1		T159	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	1		T51	1		T42	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	14		T45	2		T78	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	6		T35	7		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	16		T46	2		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T54	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	12		T2	1		T12	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T54	1		T55	12		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	3		T11	14		T42	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	1		T51	2		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T15	1		T153	3		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	1		T160	13		T58	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T39	1		T60	1		T58	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T5	12		T65	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	3		T13	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T51	12		T194	1		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T20	1		T285	12		T279	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T244	11		T318	1		T319	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17565	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T161	1		T166	11		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T54	11		T158	2		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	8		T157	11		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T158	11		T238	9		T250	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T51	11		T42	12		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	14		T45	2		T78	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	1		T61	13		T69	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	2		T38	15		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	8		T54	14		T44	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	11		T2	13		T12	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	9		T55	10		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	2		T11	14		T42	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T44	8		T61	10		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T55	8		T37	27		T43	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T60	15		T58	5		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T60	13		T58	11		T166	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	8		T65	11		T161	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	8		T13	4		T55	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T51	11		T244	10		T227	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T324	1		T180	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T244	2		T319	12		T250	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T154	6		T255	8		T323	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T166	14		T152	9		T234	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T261	1		T20	1		T279	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T244	6		T70	6		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T336	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T156	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	1		T50	1		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	1		T154	1		T157	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T50	1		T158	1		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	9		T46	1		T42	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	14		T45	2		T67	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	6		T51	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	16		T38	1		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T35	7		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	12		T2	1		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	1		T55	12		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	14		T42	12		T65	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	1		T51	2		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	3		T55	3		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T60	1		T150	1		T160	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T44	1		T60	1		T58	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T5	12		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T11	3		T13	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T51	12		T194	1		T160	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T261	4		T324	1		T175	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T244	10		T319	12		T338	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T336	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T54	11		T154	6		T158	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T154	12		T157	11		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T158	11		T32	6		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	8		T42	12		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	14		T45	2		T155	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	1		T51	11		T61	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	15		T45	1		T78	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	8		T158	4		T254	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	11		T2	13		T12	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T54	14		T55	10		T44	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	14		T42	11		T65	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T54	9		T44	8		T61	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	2		T55	8		T154	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T60	15		T58	5		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	8		T60	13		T58	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	8		T65	11		T161	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T11	8		T13	4		T55	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T51	11		T151	13		T244	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22