Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23182

1

T1

5

T2

15

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3548

1

T1

23

T2

1

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20533

1

T1

5

T2

2

T3

18

auto[1]

6197

1

T1

23

T2

14

T3

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	183	1			T50	1		T57	1		T149	2
values[0]	26	1			T50	1		T303	1		T266	3
values[1]	650	1			T1	23		T48	1		T46	1
values[2]	815	1			T2	1		T3	17		T12	21
values[3]	562	1			T2	14		T11	11		T13	5
values[4]	616	1			T5	20		T46	4		T50	1
values[5]	2979	1			T1	5		T3	28		T15	1
values[6]	842	1			T54	10		T55	22		T42	26
values[7]	733	1			T13	9		T51	2		T55	11
values[8]	911	1			T11	28		T54	15		T44	11
values[9]	907	1			T2	1		T3	1		T9	16
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	641	1			T1	23		T12	21		T48	1
values[1]	741	1			T2	15		T3	17		T13	5
values[2]	543	1			T11	11		T46	4		T50	1
values[3]	2933	1			T1	5		T5	20		T15	1
values[4]	761	1			T3	28		T51	12		T44	9
values[5]	813	1			T54	10		T55	22		T42	26
values[6]	859	1			T11	28		T13	9		T51	2
values[7]	792	1			T3	1		T44	11		T61	11
values[8]	799	1			T2	1		T9	16		T50	1
values[9]	94	1			T161	31		T70	6		T240	25
minimum	17754	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	1		T46	1		T42	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	12		T12	12		T38	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	15		T3	9		T13	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	1		T46	4		T44	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	9		T50	1		T60	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	3		T159	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T1	3		T15	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	9		T51	12		T231	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	15		T45	2		T157	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T51	12		T44	9		T154	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T149	1		T68	8		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T54	10		T55	11		T42	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T51	1		T55	7		T154	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	15		T13	9		T54	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T61	11		T158	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T44	11		T154	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T54	12		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T50	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T238	10		T339	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T161	18		T70	5		T240	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17467	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T50	1		T18	4		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	11		T45	1		T247	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	11		T12	9		T67	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	8		T152	9		T235	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	3		T227	9		T252	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	2		T149	5		T58	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	1		T159	13		T27	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T1	2		T55	2		T41	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	11		T51	11		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	13		T45	1		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T58	13		T166	10		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T149	6		T68	3		T163	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T55	11		T42	13		T271	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T51	1		T55	4		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	13		T159	5		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T159	11		T236	11		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T228	3		T229	9		T19	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	15		T149	1		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T67	16		T78	1		T160	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T238	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T161	13		T70	1		T240	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	7		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T232	7		T23	1		T340	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T149	1		T160	1		T293	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T50	1		T57	1		T17	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T266	3		T306	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T50	1		T303	1		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	1		T46	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	12		T38	16		T194	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	1		T3	9		T45	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	12		T46	4		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	14		T11	9		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	1		T44	9		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T50	1		T281	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	9		T46	3		T51	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T1	3		T3	15		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T51	12		T44	9		T154	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T68	2		T163	1		T244	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T54	10		T55	11		T42	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	1		T55	7		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	9		T158	3		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T61	11		T154	14		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	15		T54	15		T44	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T54	12		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	1		T3	1		T60	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T149	1		T160	9		T297	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T17	3		T255	11		T70	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T204	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	6		T42	11		T78	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	11		T194	14		T232	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	8		T45	1		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	9		T46	3		T67	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	2		T149	5		T58	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T159	13		T27	8		T32	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T254	9		T256	13		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	11		T46	1		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T1	2		T3	13		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	13		T171	9		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T68	1		T163	13		T244	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T55	11		T42	13		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	1		T55	4		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T159	5		T230	11		T276	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T29	9		T236	11		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	13		T228	3		T229	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	15		T159	11		T166	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T67	16		T78	1		T160	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	1		T46	1		T42	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	12		T12	10		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	2		T3	9		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	1		T46	6		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	3		T50	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	2		T159	14		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	3		T15	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	12		T51	12		T231	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	14		T45	2		T157	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T51	1		T44	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T149	7		T68	8		T163	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T54	1		T55	12		T42	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	2		T55	5		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	14		T13	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T61	1		T158	1		T159	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T44	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	16		T54	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T50	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T238	10		T339	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T161	14		T70	6		T240	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17627	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T50	1		T18	2		T232	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	11		T45	2		T247	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	11		T12	11		T38	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	13		T3	8		T13	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	1		T44	8		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	8		T60	13		T58	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T46	2		T27	3		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	2		T55	8		T37	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	8		T51	11		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	14		T45	1		T157	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	11		T44	8		T154	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T68	3		T244	10		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T54	9		T55	10		T42	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	6		T154	13		T29	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	14		T13	8		T54	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T61	10		T158	11		T33	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	10		T154	12		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T54	11		T166	13		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	5		T158	4		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T238	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T161	17		T240	13		T271	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T78	13		T229	4		T241	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T18	2		T23	2		T340	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T149	2		T160	10		T293	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T50	1		T57	1		T17	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T266	1		T306	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T50	1		T303	1		T204	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T48	1		T46	1		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	12		T38	1		T194	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	1		T3	9		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	10		T46	6		T67	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T11	3		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	1		T44	1		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T50	1		T281	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	12		T46	2		T51	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	3		T3	14		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	1		T44	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T68	3		T163	14		T244	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T54	1		T55	12		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	2		T55	5		T149	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T13	1		T158	1		T159	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T61	1		T154	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	14		T54	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	16		T54	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	1		T3	1		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T286	9		T238	9		T250	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T17	11		T255	2		T271	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T266	2		T306	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T204	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	11		T78	13		T247	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	11		T38	15		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	8		T45	2		T61	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	11		T46	1		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	13		T11	8		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	8		T27	3		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T261	4		T234	12		T264	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	8		T46	2		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T1	2		T3	14		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	11		T44	8		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T244	10		T229	5		T289	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T54	9		T55	10		T42	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T55	6		T151	13		T68	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	8		T158	2		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T61	10		T154	13		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	14		T54	14		T44	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T54	11		T166	13		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T60	5		T158	4		T161	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22