Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20701

1

T1

5

T3

17

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

6029

1

T1

23

T2

16

T3

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20501

1

T1

28

T2

2

T3

18

auto[1]

6229

1

T2

14

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T46	7		T27	14		T247	11
values[0]	54	1			T261	14		T301	8		T341	17
values[1]	812	1			T1	5		T50	1		T57	1
values[2]	665	1			T2	1		T11	11		T51	12
values[3]	820	1			T5	20		T13	14		T50	1
values[4]	831	1			T1	23		T3	18		T48	2
values[5]	759	1			T2	14		T12	21		T44	18
values[6]	531	1			T3	28		T50	1		T55	22
values[7]	703	1			T2	1		T9	16		T46	4
values[8]	543	1			T46	1		T39	1		T42	26
values[9]	3256	1			T11	28		T15	1		T153	3
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	614	1			T1	5		T11	11		T50	1
values[1]	2943	1			T2	1		T13	5		T15	1
values[2]	773	1			T5	20		T13	9		T51	2
values[3]	836	1			T1	23		T3	18		T48	2
values[4]	725	1			T2	14		T3	28		T12	21
values[5]	598	1			T2	1		T50	1		T55	22
values[6]	640	1			T9	16		T46	4		T51	23
values[7]	592	1			T11	28		T46	1		T55	11
values[8]	884	1			T60	16		T61	14		T78	31
values[9]	189	1			T46	7		T154	13		T251	1
minimum	17936	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	3		T11	9		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T156	1		T227	4		T254	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	5		T54	10		T45	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1670	1			T2	1		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	9		T194	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	9		T51	1		T54	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	9		T48	1		T55	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	12		T3	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T67	1		T150	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	14		T3	15		T12	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	1		T55	11		T65	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T38	16		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	3		T51	12		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	1		T42	13		T154	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	15		T46	1		T152	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T55	9		T39	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T60	16		T29	19		T247	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T61	14		T78	14		T27	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T46	4		T154	13		T287	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T251	1		T255	3		T272	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17502	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T57	1		T67	1		T58	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	2		T11	2		T35	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T227	9		T234	14		T235	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T45	1		T159	13		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	989	1			T41	19		T31	14		T185	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T194	14		T159	11		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	11		T51	1		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	8		T55	4		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	11		T160	13		T32	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T67	16		T247	6		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	13		T12	9		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T55	11		T157	12		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	1		T256	14		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	1		T51	11		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	15		T42	13		T68	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	13		T152	9		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T55	2		T149	5		T58	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	9		T247	3		T229	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T78	17		T27	8		T255	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T46	3		T264	9		T242	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T255	11		T272	13		T279	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T67	8		T58	11		T152	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T46	4		T247	8		T287	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T27	6		T255	12		T342	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T261	14		T301	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T341	10		T343	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	3		T50	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T57	1		T67	1		T58	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	9		T51	12		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T158	3		T68	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	14		T54	10		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	9		T50	1		T54	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	9		T48	1		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T1	12		T3	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	9		T67	1		T247	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	14		T12	12		T44	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T50	1		T55	11		T65	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	15		T166	15		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	3		T51	12		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T9	1		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T46	1		T159	1		T152	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	1		T42	13		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	15		T60	16		T154	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1752	1			T15	1		T153	3		T126	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T46	3		T247	3		T262	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T27	8		T255	20		T272	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T341	7		T343	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	2		T35	6		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T67	8		T58	11		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	2		T45	1		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T68	2		T24	3		T25	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T194	14		T159	11		T160	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	11		T161	13		T228	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	8		T55	4		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	11		T51	1		T32	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T67	16		T247	6		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	9		T160	13		T252	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T55	11		T157	12		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	13		T166	10		T244	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T46	1		T51	11		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	15		T149	1		T68	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T159	5		T152	9		T19	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	13		T149	5		T58	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	13		T29	9		T229	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T55	2		T41	19		T78	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	3		T11	3		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T156	1		T227	10		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T54	1		T45	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1336	1			T2	1		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	1		T194	15		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	12		T51	2		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	9		T48	1		T55	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T1	12		T3	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T67	17		T150	1		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T3	14		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	1		T55	12		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T38	1		T149	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	2		T51	12		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	16		T42	14		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	14		T46	1		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T55	3		T39	1		T149	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	1		T29	10		T247	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T61	1		T78	18		T27	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T46	6		T154	1		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T251	1		T255	12		T272	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17634	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T57	1		T67	9		T58	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	2		T11	8		T51	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T227	3		T254	1		T234	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	4		T54	9		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1323	1			T54	14		T37	27		T43	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	8		T33	2		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	8		T54	11		T44	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	8		T55	6		T44	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	11		T60	5		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T247	8		T17	11		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	13		T3	14		T12	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T55	10		T65	11		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	15		T158	11		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	2		T51	11		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T42	12		T154	13		T158	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	14		T152	17		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	8		T58	5		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T60	15		T29	18		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T61	13		T78	13		T27	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T46	1		T154	12		T287	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T255	2		T272	12		T238	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T205	2		T230	10		T319	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T58	11		T152	11		T289	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T46	6		T247	4		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T27	11		T255	22		T342	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T261	1		T301	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T341	8		T343	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	3		T50	1		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T57	1		T67	9		T58	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	3		T51	1		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T158	1		T68	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	2		T54	1		T194	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	12		T50	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	9		T48	1		T55	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	12		T3	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	1		T67	17		T247	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T12	10		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	1		T55	12		T65	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	14		T166	11		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T46	2		T51	12		T45	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T9	16		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	1		T159	6		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	1		T42	14		T149	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	14		T60	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1461	1			T15	1		T153	3		T126	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T46	1		T247	7		T287	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T27	3		T255	10		T272	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T261	13		T301	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T341	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	2		T42	11		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T58	11		T152	11		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	8		T51	11		T45	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T158	2		T68	3		T286	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	12		T54	9		T33	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	8		T54	14		T44	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	8		T55	6		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	11		T54	11		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T44	8		T247	8		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	13		T12	11		T44	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T55	10		T65	11		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T3	14		T166	14		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	2		T51	11		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	15		T154	13		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T152	17		T18	2		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	12		T58	5		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	14		T60	15		T154	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1385	1			T55	8		T37	27		T43	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22