Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22936

1

T1

28

T2

15

T3

45

auto[ADC_CTRL_FILTER_COND_OUT]

3794

1

T2

1

T3

1

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20647

1

T1

5

T3

18

T4

20

auto[1]

6083

1

T1

23

T2

16

T3

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	405	1			T57	1		T154	7		T158	3
values[0]	99	1			T11	11		T235	18		T258	8
values[1]	755	1			T3	17		T46	1		T44	9
values[2]	595	1			T5	20		T11	28		T50	1
values[3]	745	1			T1	23		T12	21		T54	10
values[4]	598	1			T51	12		T54	15		T44	9
values[5]	587	1			T48	2		T55	11		T65	9
values[6]	924	1			T13	5		T55	22		T35	7
values[7]	602	1			T2	14		T3	1		T46	11
values[8]	2870	1			T1	5		T2	1		T3	28
values[9]	1044	1			T2	1		T13	9		T50	2
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	522	1			T3	17		T39	1		T44	9
values[1]	693	1			T5	20		T11	28		T12	21
values[2]	754	1			T1	23		T51	12		T54	10
values[3]	608	1			T54	15		T44	9		T45	3
values[4]	641	1			T48	2		T55	11		T65	9
values[5]	788	1			T13	5		T51	2		T55	22
values[6]	2924	1			T2	14		T3	1		T9	16
values[7]	620	1			T1	5		T2	1		T3	28
values[8]	1133	1			T2	1		T13	9		T50	2
values[9]	135	1			T57	1		T154	7		T158	3
minimum	17912	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	9		T39	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T44	9		T159	1		T161	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T50	1		T58	9		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	9		T11	15		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	12		T51	12		T166	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T54	10		T158	5		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T54	15		T44	9		T45	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T60	6		T150	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	1		T55	9		T65	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	1		T67	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	5		T51	1		T42	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T55	11		T35	1		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T2	14		T15	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T9	1		T46	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	3		T3	15		T46	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T60	16		T61	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	1		T13	9		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T50	1		T44	11		T60	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T57	1		T154	7		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T267	1		T269	8		T273	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17461	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	9		T154	13		T149	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T3	8		T159	11		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T159	13		T161	13		T169	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T58	3		T228	3		T276	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	11		T11	13		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	11		T166	13		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T160	9		T163	13		T271	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T45	1		T149	6		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T160	12		T69	4		T205	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T55	2		T58	11		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T67	16		T244	5		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	1		T42	11		T78	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T55	11		T35	6		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T51	11		T41	19		T42	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	15		T46	3		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	2		T3	13		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	12		T20	1		T322	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T160	13		T27	8		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T194	14		T166	10		T152	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T234	14		T259	14		T344	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T267	6		T273	13		T277	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	2		T149	5		T256	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T57	1		T154	7		T158	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T33	9		T166	15		T230	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T235	8		T274	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T11	9		T258	8		T341	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	9		T46	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T44	9		T154	13		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T50	1		T39	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	9		T11	15		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	12		T166	14		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	12		T54	10		T55	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T51	12		T54	15		T44	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T60	6		T158	5		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	1		T55	9		T65	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	1		T67	1		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	5		T42	12		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T55	11		T35	1		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	14		T46	3		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T46	4		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T1	3		T3	15		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T9	1		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T2	1		T13	9		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T50	1		T44	11		T60	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T160	13		T247	3		T253	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T166	10		T230	8		T179	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T235	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T11	2		T341	7		T270	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	8		T159	11		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T149	5		T159	13		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T58	3		T228	3		T289	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	11		T11	13		T256	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	11		T166	13		T151	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	9		T55	4		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	1		T149	6		T68	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T160	12		T163	13		T302	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T55	2		T58	11		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T67	16		T69	4		T244	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	11		T78	1		T252	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T55	11		T35	6		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	1		T51	12		T42	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T46	3		T67	8		T159	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T1	2		T3	13		T41	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	15		T155	7		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	8		T247	6		T19	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T194	14		T152	13		T171	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	9		T39	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	1		T159	14		T161	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T50	1		T58	7		T228	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	12		T11	14		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T1	12		T51	1		T166	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T54	1		T158	1		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T54	1		T44	1		T45	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T60	1		T150	1		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	1		T55	3		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	1		T67	17		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	1		T51	2		T42	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T55	12		T35	7		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T2	1		T15	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T9	16		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	3		T3	14		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T60	1		T61	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T2	1		T13	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T50	1		T44	1		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T57	1		T154	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T267	7		T269	1		T273	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17548	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	3		T154	1		T149	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	8		T17	11		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	8		T161	17		T255	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T58	5		T276	9		T289	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	8		T11	14		T12	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	11		T51	11		T166	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T54	9		T158	4		T271	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T54	14		T44	8		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T60	5		T33	2		T69	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T55	8		T65	8		T58	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T244	10		T229	10		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	4		T42	11		T65	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	10		T45	2		T78	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	13		T51	11		T37	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	1		T155	8		T229	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	2		T3	14		T46	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	15		T61	23		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	8		T38	15		T154	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T44	10		T60	13		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T154	6		T158	2		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T269	7		T273	12		T277	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T246	7		T21	1		T299	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	8		T154	12		T256	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T57	1		T154	1		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T33	1		T166	11		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T235	11		T274	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T11	3		T258	1		T341	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	9		T46	1		T159	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T44	1		T154	1		T149	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T50	1		T39	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	12		T11	14		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	12		T166	14		T151	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	10		T54	1		T55	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	1		T54	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	1		T158	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	1		T55	3		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	1		T67	17		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	1		T42	12		T78	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T55	12		T35	7		T45	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	1		T46	2		T51	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T46	6		T67	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T1	3		T3	14		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T9	16		T58	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	1		T13	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T50	1		T44	1		T60	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T154	6		T158	2		T247	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	8		T166	14		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T235	7		T274	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T11	8		T258	7		T341	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	8		T17	11		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T44	8		T154	12		T161	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T58	5		T289	7		T258	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	8		T11	14		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	11		T166	13		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	11		T54	9		T55	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T51	11		T54	14		T44	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T60	5		T158	4		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T55	8		T65	8		T58	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T33	2		T69	4		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	4		T42	11		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T55	10		T45	2		T78	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	13		T46	2		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T46	1		T255	2		T256	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T1	2		T3	14		T54	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	8		T163	10		T229	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	8		T38	15		T154	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T44	10		T60	28		T61	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22