Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	12		T2	1		T9	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T154	1		T157	13		T194	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	1		T3	9		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T3	14		T5	12		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	7		T39	1		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	12		T45	2		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T11	14		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T55	12		T65	1		T58	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T13	1		T46	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T55	5		T45	2		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	1		T161	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T44	1		T247	7		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	3		T13	1		T46	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	3		T42	12		T61	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T42	14		T60	1		T149	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T54	1		T61	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T57	1		T33	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	10		T149	9		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T78	2		T159	12		T252	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T58	7		T253	16		T240	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17514	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	11		T51	11		T55	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T154	13		T157	11		T27	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	13		T3	8		T37	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	14		T5	8		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	2		T58	2		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T51	11		T45	1		T229	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	14		T38	15		T44	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	10		T65	11		T58	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	4		T46	2		T54	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T55	6		T45	2		T158	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T54	11		T152	17		T231	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	8		T247	8		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	2		T13	8		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	8		T42	11		T61	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	12		T60	13		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T54	14		T61	10		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	8		T254	1		T261	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	11		T166	13		T256	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T262	4		T238	10		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T58	5		T240	13		T264	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T265	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T14	2		T47	1		T46	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T256	1		T257	1		T177	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T157	13		T194	15		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	12		T2	1		T9	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T154	1		T150	1		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T3	9		T15	1		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	14		T5	12		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T35	7		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	1		T51	12		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	1		T194	1		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T55	12		T65	1		T58	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	1		T3	1		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	5		T45	2		T228	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	3		T54	2		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T158	1		T247	7		T251	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	3		T13	1		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T42	12		T44	1		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T42	14		T149	6		T258	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	3		T54	1		T61	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T57	1		T60	1		T78	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T12	10		T61	1		T149	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17076	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T266	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T157	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	11		T51	11		T55	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T154	13		T69	4		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T3	8		T37	27		T43	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	14		T5	8		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	13		T33	2		T254	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	11		T45	1		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	15		T161	17		T58	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T55	10		T65	11		T58	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	14		T13	4		T44	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T55	6		T45	2		T228	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	2		T54	20		T231	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T158	11		T247	8		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	2		T13	8		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T42	11		T44	8		T212	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T42	12		T258	12		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	8		T54	14		T61	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T60	13		T33	8		T254	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T12	11		T61	10		T236	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22