Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22893

1

T1

28

T3

28

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3837

1

T2

16

T3

18

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20762

1

T1

28

T2

1

T3

46

auto[1]

5968

1

T2

15

T9

16

T13

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T290	1		T24	9		-	-
values[0]	27	1			T291	1		T178	1		T292	11
values[1]	727	1			T48	1		T51	23		T54	10
values[2]	2903	1			T2	1		T3	29		T13	5
values[3]	676	1			T50	1		T57	1		T39	1
values[4]	666	1			T13	9		T48	1		T50	1
values[5]	631	1			T3	17		T78	2		T158	3
values[6]	896	1			T1	5		T2	15		T46	7
values[7]	921	1			T1	23		T5	20		T51	12
values[8]	633	1			T9	16		T11	11		T46	5
values[9]	1134	1			T11	28		T12	21		T51	2
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	927	1			T3	28		T48	1		T50	1
values[1]	2963	1			T2	1		T3	1		T13	5
values[2]	609	1			T13	9		T50	2		T57	1
values[3]	565	1			T48	1		T35	7		T44	11
values[4]	707	1			T2	14		T3	17		T46	7
values[5]	935	1			T1	5		T2	1		T5	20
values[6]	892	1			T1	23		T11	11		T51	12
values[7]	695	1			T9	16		T46	5		T55	22
values[8]	726	1			T11	28		T12	21		T45	3
values[9]	205	1			T51	2		T198	1		T159	14
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	15		T50	1		T58	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T48	1		T51	12		T54	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T15	1		T153	3		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T3	1		T13	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T44	9		T61	14		T160	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	9		T50	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	1		T35	1		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	11		T78	1		T168	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T194	1		T162	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	14		T3	9		T46	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	3		T5	9		T55	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T54	15		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	12		T51	12		T65	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	9		T42	13		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	1		T55	11		T65	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T46	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	15		T151	14		T293	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	12		T45	2		T33	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T51	1		T198	1		T255	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T159	1		T230	10		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	13		T58	11		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T51	11		T67	16		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T41	19		T31	14		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T55	4		T163	12		T255	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T160	22		T244	10		T289	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T159	5		T230	10		T271	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	6		T67	8		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T78	1		T244	1		T252	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T169	9		T283	1		T177	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	8		T46	3		T42	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	2		T5	11		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T152	22		T172	2		T252	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	11		T149	6		T58	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	2		T42	13		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T55	11		T194	14		T247	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	15		T46	1		T27	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	13		T151	5		T284	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	9		T45	1		T166	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T51	1		T255	11		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T159	13		T230	8		T234	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T290	1		T24	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T291	1		T178	1		T292	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T294	6		T295	1		T296	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T58	12		T152	10		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T48	1		T51	12		T54	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T3	15		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T3	1		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	9		T61	14		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	1		T57	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T48	1		T35	1		T67	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	9		T50	1		T44	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	1		T169	1		T229	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	9		T78	1		T158	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	3		T149	1		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T2	15		T46	4		T54	27
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T1	12		T5	9		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T42	13		T60	14		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	1		T158	12		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T11	9		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T11	15		T51	1		T55	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T12	12		T45	2		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T24	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	1		T296	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T58	11		T205	11		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T51	11		T67	16		T155	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T3	13		T41	19		T31	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	4		T159	11		T163	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T160	9		T244	10		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	5		T230	10		T271	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T35	6		T67	8		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T78	17		T244	1		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T169	9		T229	6		T283	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	8		T78	1		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	2		T149	5		T29	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	3		T42	11		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	11		T5	11		T55	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T42	13		T149	6		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T247	3		T69	4		T229	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	15		T11	2		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	13		T51	1		T55	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	9		T45	1		T159	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	14		T50	1		T58	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T48	1		T51	12		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T15	1		T153	3		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T3	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T44	1		T61	1		T160	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	1		T50	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	1		T35	7		T67	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T44	1		T78	2		T168	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T194	1		T162	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T3	9		T46	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	3		T5	12		T55	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T54	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	12		T51	1		T65	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T11	3		T42	14		T45	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T46	1		T55	12		T65	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	16		T46	2		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	14		T151	6		T293	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	10		T45	2		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T51	2		T198	1		T255	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T159	14		T230	9		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	14		T58	11		T228	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T51	11		T54	9		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T37	27		T38	15		T43	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	4		T55	6		T60	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	8		T61	13		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	8		T60	5		T61	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T154	13		T157	11		T161	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T44	10		T241	9		T21	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T261	13		T218	1		T297	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	13		T3	8		T46	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	2		T5	8		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	14		T152	28		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	11		T51	11		T65	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	8		T42	12		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	10		T65	11		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	2		T27	3		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	14		T151	13		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	11		T45	1		T33	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T255	11		T256	15		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T230	9		T234	12		T36	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T290	1		T24	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T291	1		T178	1		T292	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T294	6		T295	1		T296	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T58	12		T152	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	1		T51	12		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T3	14		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T3	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	1		T61	1		T160	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	1		T57	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	1		T35	7		T67	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T50	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T156	1		T169	10		T229	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	9		T78	2		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	3		T149	6		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	2		T46	6		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	12		T5	12		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T42	14		T60	1		T149	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	1		T158	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	16		T11	3		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	14		T51	2		T55	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T12	10		T45	2		T159	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T24	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T292	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T58	11		T152	9		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T51	11		T54	9		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T3	14		T37	27		T38	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T55	6		T60	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T44	8		T61	13		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T61	10		T154	6		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T154	13		T157	11		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	8		T44	10		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T229	4		T298	11		T299	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	8		T158	2		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	2		T29	18		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T2	13		T46	1		T54	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	11		T5	8		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	12		T60	13		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	11		T247	7		T69	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	8		T46	2		T236	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	14		T55	10		T65	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	11		T45	1		T27	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22