Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20726

1

T1

5

T3

17

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

6004

1

T1

23

T2

16

T3

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20514

1

T1

28

T2

2

T3

18

auto[1]

6216

1

T2

14

T3

28

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T156	1		T264	19		-	-
values[0]	101	1			T261	14		T289	25		T189	23
values[1]	804	1			T1	5		T50	1		T57	1
values[2]	648	1			T2	1		T11	11		T13	5
values[3]	801	1			T13	9		T50	1		T54	10
values[4]	842	1			T1	23		T2	14		T3	1
values[5]	743	1			T3	17		T12	21		T44	18
values[6]	572	1			T3	28		T55	22		T65	12
values[7]	669	1			T2	1		T9	16		T46	4
values[8]	588	1			T46	1		T39	1		T42	26
values[9]	3436	1			T11	28		T15	1		T153	3
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1060	1			T1	5		T11	11		T51	12
values[1]	2819	1			T2	1		T13	9		T15	1
values[2]	850	1			T5	20		T13	5		T51	2
values[3]	899	1			T1	23		T3	18		T12	21
values[4]	714	1			T2	14		T3	28		T60	14
values[5]	561	1			T2	1		T50	1		T55	22
values[6]	601	1			T9	16		T46	5		T51	23
values[7]	663	1			T11	28		T55	11		T39	1
values[8]	828	1			T60	16		T154	13		T78	31
values[9]	229	1			T46	7		T27	14		T255	18
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T1	3		T11	9		T51	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T57	1		T67	1		T58	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	9		T50	1		T54	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1636	1			T2	1		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	5		T55	7		T61	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	9		T51	1		T54	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	9		T48	1		T44	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T1	12		T3	1		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T67	1		T157	12		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	14		T3	15		T60	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	1		T55	11		T65	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	1		T38	16		T44	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	3		T51	12		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T46	1		T42	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	15		T152	18		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T55	9		T39	1		T61	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T60	16		T154	13		T29	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T78	14		T162	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T46	4		T283	1		T287	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T27	6		T255	9		T70	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	2		T11	2		T35	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T67	8		T58	11		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T45	1		T159	13		T160	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	952	1			T41	19		T31	14		T185	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	4		T194	14		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	11		T51	1		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	8		T21	11		T239	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	11		T12	9		T160	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T67	16		T157	12		T247	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	13		T166	10		T244	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	11		T17	3		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T149	1		T256	14		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	1		T51	11		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	15		T42	13		T68	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	13		T152	9		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T55	2		T149	5		T58	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	9		T247	3		T229	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T78	17		T255	11		T252	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T46	3		T283	1		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T27	8		T255	9		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T156	1		T264	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T261	14		T300	1		T301	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T289	11		T189	11		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	3		T50	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T57	1		T67	1		T58	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	9		T13	5		T51	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T54	15		T158	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	9		T54	10		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T50	1		T44	11		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	1		T55	7		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	12		T2	14		T3	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	9		T44	9		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	12		T44	9		T60	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T55	11		T65	12		T157	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	15		T166	15		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	3		T50	1		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T9	1		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T161	1		T152	18		T18	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	1		T39	1		T42	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T11	15		T46	4		T60	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1772	1			T15	1		T153	3		T126	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T264	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T300	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T289	14		T189	12		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	2		T35	6		T42	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T67	8		T58	11		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	2		T45	1		T159	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T68	2		T24	3		T25	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T194	14		T159	11		T160	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T161	13		T228	3		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T55	4		T230	10		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	11		T5	11		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	8		T67	16		T247	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	9		T160	13		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	11		T157	12		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	13		T166	10		T68	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	1		T51	11		T45	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	15		T149	1		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	9		T19	11		T302	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	13		T149	5		T58	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	13		T46	3		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1135	1			T55	2		T41	19		T78	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	3		T11	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T57	1		T67	9		T58	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T50	1		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1296	1			T2	1		T15	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T55	5		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	12		T51	2		T54	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	9		T48	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	12		T3	1		T12	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T67	17		T157	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T3	14		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	1		T55	12		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T38	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	2		T51	12		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	16		T46	1		T42	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	14		T152	10		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T55	3		T39	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T60	1		T154	1		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T78	18		T162	1		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T46	6		T283	2		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T27	11		T255	10		T70	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	2		T11	8		T51	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T58	11		T152	11		T227	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	8		T54	9		T45	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1292	1			T37	27		T43	28		T62	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	4		T55	6		T61	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	8		T54	25		T44	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	8		T44	8		T257	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	11		T12	11		T60	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T157	11		T247	8		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	13		T3	14		T60	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T55	10		T65	11		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T38	15		T44	8		T158	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	2		T51	11		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	12		T154	13		T158	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	14		T152	17		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	8		T61	13		T58	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	15		T154	12		T29	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T78	13		T255	2		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T46	1		T287	5		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T27	3		T255	8		T230	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T156	1		T264	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T261	1		T300	8		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T289	15		T189	13		T221	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	3		T50	1		T35	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T57	1		T67	9		T58	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	3		T13	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T54	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	1		T54	1		T194	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T50	1		T44	1		T161	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	1		T55	5		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	12		T2	1		T3	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	9		T44	1		T67	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	10		T44	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	12		T65	1		T157	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	14		T166	11		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T46	2		T50	1		T51	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T9	16		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T161	1		T152	10		T18	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	1		T39	1		T42	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	14		T46	6		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1516	1			T15	1		T153	3		T126	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T264	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T261	13		T301	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T289	10		T189	10		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	2		T42	11		T231	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T58	11		T152	11		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	8		T13	4		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T54	14		T158	2		T68	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	8		T54	9		T229	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T44	10		T161	17		T235	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	6		T33	2		T230	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	11		T2	13		T5	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	8		T44	8		T247	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	11		T44	8		T60	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T55	10		T65	11		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T3	14		T166	14		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	2		T51	11		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	15		T154	13		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T152	17		T18	2		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	12		T58	5		T246	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	14		T46	1		T60	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1391	1			T55	8		T37	27		T43	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22