Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23045

1

T1

5

T2

15

T3

46

auto[ADC_CTRL_FILTER_COND_OUT]

3685

1

T1

23

T2

1

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20649

1

T1

5

T2

16

T3

18

auto[1]

6081

1

T1

23

T3

28

T11

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T58	1		-	-		-	-
values[0]	47	1			T50	1		T303	1		T304	21
values[1]	707	1			T1	23		T2	1		T48	1
values[2]	715	1			T3	17		T12	21		T45	4
values[3]	611	1			T2	14		T11	11		T13	5
values[4]	582	1			T5	20		T46	4		T50	1
values[5]	3000	1			T1	5		T3	28		T15	1
values[6]	842	1			T51	12		T54	10		T55	22
values[7]	770	1			T13	9		T51	2		T55	11
values[8]	837	1			T11	28		T54	15		T44	11
values[9]	1112	1			T2	1		T3	1		T9	16
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T1	23		T2	1		T12	21
values[1]	782	1			T2	14		T3	17		T13	5
values[2]	555	1			T11	11		T46	4		T60	14
values[3]	2849	1			T1	5		T5	20		T15	1
values[4]	743	1			T3	28		T51	12		T44	9
values[5]	892	1			T55	22		T42	26		T65	21
values[6]	820	1			T11	28		T13	9		T51	2
values[7]	816	1			T3	1		T44	11		T61	11
values[8]	749	1			T2	1		T9	16		T50	1
values[9]	163	1			T54	12		T70	6		T240	25
minimum	17554	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T46	1		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	12		T12	12		T38	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	14		T3	9		T13	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T46	4		T44	9		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	9		T60	14		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	3		T159	1		T27	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T1	3		T15	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	9		T50	1		T51	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	15		T44	9		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T51	12		T58	15		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T42	13		T149	1		T68	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T55	11		T65	21		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T51	1		T55	7		T154	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	15		T13	9		T54	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T3	1		T44	11		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T61	11		T159	2		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	1		T158	5		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T9	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T240	14		T214	1		T238	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T54	12		T70	5		T271	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17402	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T304	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	11		T45	1		T78	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	11		T12	9		T67	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	8		T152	9		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	3		T252	18		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	2		T149	5		T155	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T46	1		T159	13		T27	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T1	2		T55	2		T41	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	11		T51	11		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	13		T45	1		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	13		T244	1		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T42	13		T149	6		T68	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	11		T166	10		T68	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	1		T55	4		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	13		T29	9		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T236	11		T228	3		T229	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	16		T19	11		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T160	9		T166	13		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	15		T67	16		T78	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T240	11		T214	2		T238	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T70	1		T271	6		T305	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T35	7		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T58	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T50	1		T266	3		T306	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T303	1		T304	10		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T48	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	12		T38	16		T194	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	9		T45	3		T61	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	12		T67	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	14		T11	9		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	4		T44	9		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T281	1		T162	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	9		T46	3		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T1	3		T3	15		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T58	15		T244	1		T171	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T42	13		T157	12		T158	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T51	12		T54	10		T55	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	1		T55	7		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	9		T159	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T44	11		T154	27		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	15		T54	15		T61	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T39	1		T158	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T2	1		T9	1		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T304	11		T204	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	6		T42	11		T78	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	11		T194	14		T232	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	8		T45	1		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	9		T67	8		T160	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T149	5		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	3		T159	13		T27	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T254	9		T256	13		T283	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	11		T46	1		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T1	2		T3	13		T55	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T58	13		T244	1		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T42	13		T157	12		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T55	11		T166	10		T68	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T51	1		T55	4		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T159	5		T205	11		T276	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T236	11		T228	3		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	13		T29	9		T19	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T160	9		T166	13		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	15		T67	16		T78	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	1		T46	1		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	12		T12	10		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T3	9		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	6		T44	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	3		T60	1		T149	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	2		T159	14		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T1	3		T15	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	12		T50	1		T51	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	14		T44	1		T45	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T51	1		T58	15		T244	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T42	14		T149	7		T68	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T55	12		T65	2		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	2		T55	5		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	14		T13	1		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T44	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T61	1		T159	18		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	1		T158	1		T160	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	1		T9	16		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T240	12		T214	3		T238	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T54	1		T70	6		T271	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	11		T45	2		T78	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	11		T12	11		T38	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	13		T3	8		T13	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	1		T44	8		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	8		T60	13		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	2		T27	3		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	2		T55	8		T37	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	8		T51	11		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	14		T44	8		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T51	11		T58	13		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T42	12		T68	3		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T55	10		T65	19		T166	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T55	6		T154	13		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	14		T13	8		T54	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T44	10		T154	12		T158	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	10		T33	2		T19	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T158	4		T166	13		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T60	5		T161	17		T247	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T240	13		T238	9		T307	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T54	11		T271	4		T308	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T241	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T304	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T58	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T50	1		T266	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T303	1		T304	12		T204	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T48	1		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	12		T38	1		T194	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	9		T45	2		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	10		T67	9		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	1		T11	3		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	6		T44	1		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T281	1		T162	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	12		T46	2		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T1	3		T3	14		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T58	15		T244	2		T171	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T42	14		T157	13		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T51	1		T54	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T51	2		T55	5		T149	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T13	1		T159	6		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	1		T154	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	14		T54	1		T61	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	1		T39	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T2	1		T9	16		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T266	2		T306	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T304	9		T204	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T42	11		T78	13		T247	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	11		T38	15		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	8		T45	2		T61	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	11		T228	11		T235	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	13		T11	8		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	1		T44	8		T27	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T261	4		T264	9		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	8		T46	2		T51	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	2		T3	14		T55	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T58	13		T171	10		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T42	12		T157	11		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T51	11		T54	9		T55	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T55	6		T309	9		T218	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	8		T205	2		T276	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T44	10		T154	25		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	14		T54	14		T61	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T158	4		T166	13		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T54	11		T60	5		T161	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22