Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23088

1

T1

28

T2

16

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3642

1

T3

46

T5

20

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20666

1

T1

5

T2

2

T3

29

auto[1]

6064

1

T1

23

T2

14

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	224	1			T50	1		T58	12		T287	6
values[0]	4	1			T280	3		T310	1		-	-
values[1]	647	1			T2	1		T50	1		T54	12
values[2]	612	1			T9	16		T45	3		T67	17
values[3]	662	1			T51	12		T55	11		T39	1
values[4]	3101	1			T3	45		T11	39		T12	21
values[5]	736	1			T3	1		T5	20		T13	9
values[6]	667	1			T48	1		T46	5		T54	25
values[7]	761	1			T2	1		T57	1		T42	23
values[8]	758	1			T1	5		T46	7		T51	23
values[9]	1052	1			T1	23		T2	14		T13	5
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	613	1			T2	1		T50	1		T54	12
values[1]	606	1			T9	16		T45	3		T60	20
values[2]	706	1			T50	1		T51	12		T55	11
values[3]	2944	1			T3	28		T11	39		T12	21
values[4]	767	1			T3	18		T5	20		T13	9
values[5]	811	1			T48	1		T46	5		T54	25
values[6]	680	1			T2	1		T51	23		T42	23
values[7]	725	1			T1	5		T46	7		T55	22
values[8]	915	1			T1	23		T2	14		T13	5
values[9]	211	1			T51	2		T161	31		T33	9
minimum	17752	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T44	9		T67	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T50	1		T54	12		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T60	14		T161	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T45	2		T60	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	1		T51	12		T55	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	1		T42	13		T44	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T15	1		T48	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	15		T11	24		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	9		T154	7		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	10		T5	9		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	1		T46	4		T54	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	9		T57	1		T61	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	1		T61	14		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	12		T42	12		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	3		T46	4		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	11		T194	1		T281	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	12		T2	14		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T35	1		T38	16		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T51	1		T33	9		T58	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T161	18		T192	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17484	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T293	1		T259	13		T311	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T67	16		T58	11		T166	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T166	10		T244	5		T252	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T234	11		T283	1		T214	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	15		T45	1		T276	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T55	4		T149	6		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	13		T149	1		T228	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T41	19		T31	14		T185	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	13		T11	15		T12	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T159	13		T228	3		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	8		T5	11		T45	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	1		T164	7		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	2		T67	8		T27	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T232	7		T256	2		T177	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T51	11		T42	11		T78	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	2		T46	3		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T55	11		T194	14		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	11		T29	9		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	6		T149	5		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T51	1		T58	3		T288	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T161	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	1		T42	2		T198	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T259	2		T311	8		T312	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T50	1		T58	9		T287	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T313	2		T314	13		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T280	3		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T44	9		T58	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T50	1		T54	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T67	1		T161	1		T166	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T45	2		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	12		T55	7		T60	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	1		T42	13		T44	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T15	1		T48	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	24		T11	24		T12	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	9		T154	7		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T5	9		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	1		T46	4		T54	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T55	9		T61	11		T65	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T60	16		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T57	1		T42	12		T32	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	3		T46	4		T61	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	12		T55	11		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T1	12		T2	14		T13	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T35	1		T38	16		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T58	3		T297	1		T316	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T314	10		T278	14		T222	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T58	11		T244	1		T19	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T244	5		T252	15		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T67	16		T166	13		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	15		T45	1		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	4		T229	5		T284	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T42	13		T149	1		T228	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T41	19		T149	6		T31	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	21		T11	15		T12	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T159	13		T228	3		T68	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	11		T45	1		T159	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	1		T285	11		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T55	2		T67	8		T78	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T164	7		T232	7		T256	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T42	11		T32	9		T58	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	2		T46	3		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	11		T55	11		T78	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T1	11		T51	1		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	6		T149	5		T160	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T44	1		T67	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	1		T54	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T60	1		T161	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	16		T45	2		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T50	1		T51	1		T55	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	1		T42	14		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T15	1		T48	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	14		T11	17		T12	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T154	1		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	10		T5	12		T45	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	1		T46	3		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T55	3		T57	1		T61	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T61	1		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T51	12		T42	12		T78	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	3		T46	6		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	12		T194	15		T281	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	12		T2	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T35	7		T38	1		T149	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T51	2		T33	1		T58	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T161	14		T192	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17566	1			T4	20		T5	45		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T293	1		T259	3		T311	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	8		T58	11		T166	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T54	11		T166	14		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T60	13		T234	12		T245	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	1		T60	5		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T51	11		T55	6		T44	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T42	12		T44	10		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T37	27		T43	28		T62	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	14		T11	22		T12	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	8		T154	6		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	8		T5	8		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	2		T54	23		T60	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	8		T61	10		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T61	13		T256	15		T286	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	11		T42	11		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	2		T46	1		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T55	10		T171	10		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	11		T2	13		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T38	15		T152	20		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	8		T58	5		T287	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T161	17		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T230	12		T234	8		T174	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T259	12		T311	10		T312	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T50	1		T58	7		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T313	2		T314	11		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T280	3		T310	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T44	1		T58	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	1		T54	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T67	17		T161	1		T166	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	16		T45	2		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	1		T55	5		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T39	1		T42	14		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T15	1		T48	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	23		T11	17		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T154	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T5	12		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	1		T46	3		T54	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T55	3		T61	1		T65	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T60	1		T164	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T57	1		T42	12		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	3		T46	6		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T51	12		T55	12		T78	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T1	12		T2	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	7		T38	1		T149	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T58	5		T287	5		T165	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T314	12		T278	16		T317	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T44	8		T58	11		T19	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T54	11		T244	10		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T166	13		T234	12		T289	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T45	1		T33	2		T166	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T51	11		T55	6		T60	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T42	12		T44	10		T60	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T37	27		T43	28		T44	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	22		T11	22		T12	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	8		T154	6		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	8		T45	2		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T46	2		T54	23		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T55	8		T61	10		T65	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T60	15		T256	15		T21	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T42	11		T32	6		T58	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	2		T46	1		T61	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	11		T55	10		T69	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T1	11		T2	13		T13	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	15		T161	17		T152	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22