Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26730

1

T1

28

T2

16

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23369

1

T1

23

T2

14

T3

28

auto[ADC_CTRL_FILTER_COND_OUT]

3361

1

T1

5

T2

2

T3

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20483

1

T1

28

T2

2

T3

1

auto[1]

6247

1

T2

14

T3

45

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T1

15

T2

16

T3

25

auto[1]

4046

1

T1

13

T3

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T177	3		T175	12		-	-
values[0]	102	1			T48	1		T156	1		T293	1
values[1]	614	1			T46	1		T50	2		T54	12
values[2]	555	1			T3	18		T42	26		T158	12
values[3]	600	1			T3	28		T46	7		T51	12
values[4]	794	1			T1	23		T9	16		T13	9
values[5]	596	1			T2	14		T12	21		T46	4
values[6]	751	1			T2	1		T11	28		T51	2
values[7]	666	1			T1	5		T55	11		T44	9
values[8]	888	1			T5	20		T60	14		T65	12
values[9]	3643	1			T2	1		T11	11		T13	5
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	864	1			T3	18		T48	1		T50	2
values[1]	542	1			T46	1		T51	12		T42	26
values[2]	585	1			T3	28		T46	7		T35	7
values[3]	841	1			T1	23		T9	16		T13	9
values[4]	695	1			T2	14		T12	21		T50	1
values[5]	641	1			T1	5		T2	1		T11	28
values[6]	2969	1			T5	20		T15	1		T153	3
values[7]	860	1			T2	1		T39	1		T44	9
values[8]	1005	1			T11	11		T13	5		T51	23
values[9]	222	1			T48	1		T160	14		T244	13
minimum	17506	1			T4	20		T5	45		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

4227

1

T1

13

T2

13

T3

22

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T48	1		T50	2		T54	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	10		T157	12		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T158	12		T159	1		T293	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	1		T51	12		T42	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	15		T45	3		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	4		T35	1		T61	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	12		T9	1		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	9		T54	15		T38	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	14		T12	12		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T54	10		T55	11		T17	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	15		T42	12		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	3		T2	1		T44	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T15	1		T153	3		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	9		T51	1		T60	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T39	1		T60	14		T161	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T44	9		T65	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	9		T13	5		T55	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T51	12		T194	1		T151	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T48	1		T160	1		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T244	3		T318	1		T319	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	9		T166	10		T255	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	8		T157	12		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T159	5		T252	15		T300	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T42	13		T228	10		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	13		T45	1		T67	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	3		T35	6		T194	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	11		T9	15		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T149	6		T164	7		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	9		T228	19		T68	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T55	11		T17	3		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	13		T42	11		T67	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	2		T169	9		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T55	2		T41	19		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	11		T51	1		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T161	13		T58	11		T228	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T78	1		T247	3		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	2		T55	4		T27	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T51	11		T151	5		T244	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T160	13		T285	11		T279	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T244	10		T319	10		T320	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T175	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T177	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T48	1		T293	1		T223	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T156	1		T321	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	2		T54	12		T154	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	1		T154	13		T157	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T158	12		T32	7		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	10		T42	13		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	15		T45	3		T67	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	4		T51	12		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	12		T9	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	9		T54	15		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	14		T12	12		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T55	11		T44	11		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	15		T42	12		T65	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T51	1		T54	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T55	9		T154	14		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	3		T44	9		T60	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T60	14		T149	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	9		T65	12		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1775	1			T11	9		T13	5		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T2	1		T51	12		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T175	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T177	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T223	13		T322	14		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T321	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T166	10		T255	9		T323	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T157	12		T236	11		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T32	9		T272	13		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	8		T42	13		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	13		T45	1		T67	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T46	3		T69	4		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	11		T9	15		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	6		T194	14		T254	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	9		T46	1		T247	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T55	11		T149	6		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	13		T42	11		T67	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	1		T169	9		T244	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T55	2		T149	1		T229	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T160	12		T58	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T149	5		T159	11		T58	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	11		T78	1		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T11	2		T55	4		T41	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T51	11		T151	5		T244	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T42	2		T198	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T48	1		T50	2		T54	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	10		T157	13		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	1		T159	6		T293	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	1		T51	1		T42	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	14		T45	2		T67	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	6		T35	7		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T1	12		T9	16		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T54	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	1		T12	10		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T54	1		T55	12		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	14		T42	12		T67	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	3		T2	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T15	1		T153	3		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	12		T51	2		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T39	1		T60	1		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T44	1		T65	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T11	3		T13	1		T55	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T51	12		T194	1		T151	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T48	1		T160	14		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T244	11		T318	1		T319	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T54	11		T154	6		T158	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	8		T157	11		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T158	11		T238	9		T250	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	11		T42	12		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	14		T45	2		T155	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	1		T61	13		T69	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	11		T46	2		T45	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	8		T54	14		T38	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	13		T12	11		T65	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T54	9		T55	10		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	14		T42	11		T152	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	2		T44	8		T61	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T55	8		T37	27		T43	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	8		T60	15		T58	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T60	13		T161	17		T58	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	8		T65	11		T33	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	8		T13	4		T55	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	11		T151	13		T244	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T324	1		T180	14		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T244	2		T319	12		T250	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T175	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T177	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T48	1		T293	1		T223	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T156	1		T321	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	2		T54	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	1		T154	1		T157	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T158	1		T32	10		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	10		T42	14		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	14		T45	2		T67	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	6		T51	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	12		T9	16		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T54	1		T35	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	1		T12	10		T46	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	12		T44	1		T149	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	14		T42	12		T65	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T51	2		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T55	3		T154	1		T149	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	3		T44	1		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T60	1		T149	6		T159	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	12		T65	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T11	3		T13	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T2	1		T51	12		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T4	20		T5	45		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T175	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T223	14		T322	12		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T321	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T54	11		T154	6		T158	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T154	12		T157	11		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T158	11		T32	6		T272	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	8		T42	12		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	14		T45	2		T155	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	1		T51	11		T61	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	11		T45	1		T78	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	8		T54	14		T38	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	13		T12	11		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T55	10		T44	10		T17	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	14		T42	11		T65	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	9		T44	8		T61	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T55	8		T154	13		T229	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	2		T44	8		T60	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	13		T58	11		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	8		T65	11		T33	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T11	8		T13	4		T55	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T51	11		T151	13		T244	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22503

1

T1

15

T2

3

T3

24

auto[1]

auto[0]

4227

1

T1

13

T2

13

T3

22