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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.66 99.07 96.67 100.00 100.00 98.83 98.33 90.72


Total test records in report: 918
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T794 /workspace/coverage/default/9.adc_ctrl_filters_both.1335950805 Aug 08 05:45:48 PM PDT 24 Aug 08 06:07:06 PM PDT 24 548961610941 ps
T795 /workspace/coverage/default/44.adc_ctrl_filters_polled.3139397339 Aug 08 05:49:40 PM PDT 24 Aug 08 06:07:54 PM PDT 24 481925372066 ps
T796 /workspace/coverage/default/49.adc_ctrl_smoke.3671108933 Aug 08 05:50:27 PM PDT 24 Aug 08 05:50:35 PM PDT 24 5967825830 ps
T797 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3494473818 Aug 08 05:44:47 PM PDT 24 Aug 08 05:44:49 PM PDT 24 509729152 ps
T75 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2754533894 Aug 08 05:44:56 PM PDT 24 Aug 08 05:44:59 PM PDT 24 2126963857 ps
T79 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3041057884 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:39 PM PDT 24 4970481561 ps
T798 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.425490135 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:49 PM PDT 24 508814751 ps
T127 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.199881431 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:32 PM PDT 24 794732130 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1416723819 Aug 08 05:44:45 PM PDT 24 Aug 08 05:45:20 PM PDT 24 53427825211 ps
T77 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4006450116 Aug 08 05:44:44 PM PDT 24 Aug 08 05:44:49 PM PDT 24 2324672170 ps
T140 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3430886391 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:45 PM PDT 24 2118240878 ps
T82 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.863499125 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:43 PM PDT 24 545202009 ps
T141 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1603932071 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:38 PM PDT 24 461198679 ps
T142 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.717238981 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:43 PM PDT 24 4546014190 ps
T143 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.367529175 Aug 08 05:44:33 PM PDT 24 Aug 08 05:44:35 PM PDT 24 2618897664 ps
T80 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2704360888 Aug 08 05:44:24 PM PDT 24 Aug 08 05:44:27 PM PDT 24 4443277254 ps
T88 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4286518820 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:47 PM PDT 24 524110576 ps
T799 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2456839084 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:45 PM PDT 24 477358061 ps
T800 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3294697317 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:49 PM PDT 24 512490451 ps
T113 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3385242318 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:47 PM PDT 24 362566464 ps
T89 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3342377240 Aug 08 05:44:40 PM PDT 24 Aug 08 05:44:42 PM PDT 24 762274598 ps
T801 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1196772061 Aug 08 05:44:51 PM PDT 24 Aug 08 05:44:52 PM PDT 24 474975300 ps
T92 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.517616968 Aug 08 05:44:43 PM PDT 24 Aug 08 05:44:46 PM PDT 24 564022810 ps
T95 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1814717598 Aug 08 05:44:34 PM PDT 24 Aug 08 05:44:36 PM PDT 24 490537353 ps
T128 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.610454841 Aug 08 05:44:55 PM PDT 24 Aug 08 05:44:57 PM PDT 24 331227064 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2403352456 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:41 PM PDT 24 584375492 ps
T802 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.161785517 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:29 PM PDT 24 658306845 ps
T803 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1502090165 Aug 08 05:45:00 PM PDT 24 Aug 08 05:45:02 PM PDT 24 481689457 ps
T94 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2041914535 Aug 08 05:44:46 PM PDT 24 Aug 08 05:44:48 PM PDT 24 434022121 ps
T130 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3881515507 Aug 08 05:44:35 PM PDT 24 Aug 08 05:44:44 PM PDT 24 10630358829 ps
T804 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1045423663 Aug 08 05:44:52 PM PDT 24 Aug 08 05:44:53 PM PDT 24 453368499 ps
T90 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2542590513 Aug 08 05:44:43 PM PDT 24 Aug 08 05:44:45 PM PDT 24 556539195 ps
T81 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.295292227 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:35 PM PDT 24 8856808673 ps
T91 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2414230884 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:51 PM PDT 24 430355255 ps
T805 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.974166234 Aug 08 05:44:49 PM PDT 24 Aug 08 05:44:50 PM PDT 24 345066687 ps
T131 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1675123597 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:33 PM PDT 24 1520464638 ps
T806 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1839704335 Aug 08 05:44:44 PM PDT 24 Aug 08 05:44:45 PM PDT 24 429487906 ps
T807 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2019137921 Aug 08 05:44:47 PM PDT 24 Aug 08 05:44:49 PM PDT 24 436789751 ps
T144 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3125711415 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:28 PM PDT 24 489893558 ps
T808 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.935691389 Aug 08 05:44:30 PM PDT 24 Aug 08 05:44:33 PM PDT 24 1226494658 ps
T145 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1877467107 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:45 PM PDT 24 2780674442 ps
T809 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.794530495 Aug 08 05:44:53 PM PDT 24 Aug 08 05:44:56 PM PDT 24 579634438 ps
T810 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.101188908 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:39 PM PDT 24 688842784 ps
T811 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1400486388 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:44 PM PDT 24 468659338 ps
T96 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3275068722 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:38 PM PDT 24 641120236 ps
T812 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.928456114 Aug 08 05:44:49 PM PDT 24 Aug 08 05:44:50 PM PDT 24 552565677 ps
T83 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1659238988 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:57 PM PDT 24 8244375277 ps
T813 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1574624371 Aug 08 05:44:46 PM PDT 24 Aug 08 05:44:47 PM PDT 24 418714337 ps
T814 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3440612280 Aug 08 05:44:50 PM PDT 24 Aug 08 05:44:52 PM PDT 24 419883583 ps
T84 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4273844481 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:47 PM PDT 24 4202835937 ps
T99 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3023667111 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:45 PM PDT 24 8872948827 ps
T815 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1506403002 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:38 PM PDT 24 482410325 ps
T146 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2871321188 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:34 PM PDT 24 4904262767 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.727819597 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:45 PM PDT 24 2529181486 ps
T98 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1651877098 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:56 PM PDT 24 8814282513 ps
T817 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3087395288 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:29 PM PDT 24 428136271 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1515676637 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:30 PM PDT 24 514644441 ps
T97 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3706496691 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:38 PM PDT 24 315913782 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2919571496 Aug 08 05:44:47 PM PDT 24 Aug 08 05:44:49 PM PDT 24 524543132 ps
T820 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.275203715 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:39 PM PDT 24 452002459 ps
T132 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.637523093 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:42 PM PDT 24 301620790 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1500507990 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:41 PM PDT 24 844772503 ps
T822 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4212465291 Aug 08 05:44:54 PM PDT 24 Aug 08 05:44:55 PM PDT 24 519030474 ps
T823 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3583682742 Aug 08 05:44:54 PM PDT 24 Aug 08 05:44:55 PM PDT 24 407283795 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3827989564 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:27 PM PDT 24 476214369 ps
T825 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.624657464 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:38 PM PDT 24 475775568 ps
T826 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1173406910 Aug 08 05:44:49 PM PDT 24 Aug 08 05:44:50 PM PDT 24 283138167 ps
T827 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2308074462 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:43 PM PDT 24 548131115 ps
T133 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1879673164 Aug 08 05:44:24 PM PDT 24 Aug 08 05:44:25 PM PDT 24 437262968 ps
T828 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1997793673 Aug 08 05:44:40 PM PDT 24 Aug 08 05:44:41 PM PDT 24 391161626 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1228987222 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:46 PM PDT 24 4418594141 ps
T134 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3187342186 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:43 PM PDT 24 404246560 ps
T830 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1288357371 Aug 08 05:44:41 PM PDT 24 Aug 08 05:45:03 PM PDT 24 8762798644 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1162067061 Aug 08 05:44:54 PM PDT 24 Aug 08 05:44:59 PM PDT 24 8582061246 ps
T832 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3520254758 Aug 08 05:44:46 PM PDT 24 Aug 08 05:44:47 PM PDT 24 486745674 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.761075133 Aug 08 05:44:24 PM PDT 24 Aug 08 05:44:28 PM PDT 24 564732027 ps
T834 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2374477668 Aug 08 05:44:50 PM PDT 24 Aug 08 05:44:51 PM PDT 24 504009765 ps
T835 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.765976330 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:28 PM PDT 24 335215119 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2760724865 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:44 PM PDT 24 337084460 ps
T837 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2386985013 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:46 PM PDT 24 510550005 ps
T838 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2950645990 Aug 08 05:44:53 PM PDT 24 Aug 08 05:44:55 PM PDT 24 436837041 ps
T839 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.670613963 Aug 08 05:44:49 PM PDT 24 Aug 08 05:44:51 PM PDT 24 357318874 ps
T135 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.96089246 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:39 PM PDT 24 406333931 ps
T840 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.329603823 Aug 08 05:44:49 PM PDT 24 Aug 08 05:44:51 PM PDT 24 375399458 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2966415475 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:40 PM PDT 24 4413426351 ps
T842 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2688280256 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:45 PM PDT 24 612340065 ps
T136 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.284897575 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:39 PM PDT 24 435266745 ps
T100 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4035802117 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:38 PM PDT 24 4751062440 ps
T843 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.427575866 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:41 PM PDT 24 527689493 ps
T137 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1578957223 Aug 08 05:44:43 PM PDT 24 Aug 08 05:44:44 PM PDT 24 413818040 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2447652690 Aug 08 05:44:33 PM PDT 24 Aug 08 05:45:03 PM PDT 24 27123187323 ps
T138 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3345060046 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:47 PM PDT 24 10191720040 ps
T845 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4262061352 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:29 PM PDT 24 471490677 ps
T139 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.787842016 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:28 PM PDT 24 1361479225 ps
T846 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4153922123 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:46 PM PDT 24 430989994 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1411817103 Aug 08 05:44:55 PM PDT 24 Aug 08 05:44:57 PM PDT 24 431074315 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2150605664 Aug 08 05:44:41 PM PDT 24 Aug 08 05:45:02 PM PDT 24 8851029238 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.696707819 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:41 PM PDT 24 479306748 ps
T850 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.371064244 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:39 PM PDT 24 472864475 ps
T851 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3794380250 Aug 08 05:44:34 PM PDT 24 Aug 08 05:44:42 PM PDT 24 2465595395 ps
T852 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4166156131 Aug 08 05:44:30 PM PDT 24 Aug 08 05:44:32 PM PDT 24 858069351 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.162709922 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:28 PM PDT 24 770420873 ps
T854 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.231505449 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:49 PM PDT 24 307479947 ps
T855 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3496023635 Aug 08 05:44:25 PM PDT 24 Aug 08 05:44:27 PM PDT 24 447846967 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3795202454 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:29 PM PDT 24 462463760 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4281143832 Aug 08 05:44:44 PM PDT 24 Aug 08 05:44:45 PM PDT 24 353817031 ps
T858 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1761162680 Aug 08 05:44:44 PM PDT 24 Aug 08 05:44:57 PM PDT 24 4781959808 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2424758859 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:42 PM PDT 24 4630526266 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3992745396 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:43 PM PDT 24 406054715 ps
T861 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3712772166 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:41 PM PDT 24 398188902 ps
T862 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3399730645 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:38 PM PDT 24 516035107 ps
T863 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2393673156 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:28 PM PDT 24 755908150 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1326863277 Aug 08 05:44:29 PM PDT 24 Aug 08 05:44:33 PM PDT 24 4636969911 ps
T865 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2578211252 Aug 08 05:44:41 PM PDT 24 Aug 08 05:44:43 PM PDT 24 2176764156 ps
T866 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3407545715 Aug 08 05:44:47 PM PDT 24 Aug 08 05:44:48 PM PDT 24 430933964 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.972132292 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:48 PM PDT 24 3977939349 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3840649178 Aug 08 05:44:40 PM PDT 24 Aug 08 05:44:42 PM PDT 24 337238984 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3885042945 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:41 PM PDT 24 1420077690 ps
T870 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1206538283 Aug 08 05:44:55 PM PDT 24 Aug 08 05:44:56 PM PDT 24 505405153 ps
T871 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.327080462 Aug 08 05:44:35 PM PDT 24 Aug 08 05:44:36 PM PDT 24 399091293 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2796166791 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:39 PM PDT 24 499911096 ps
T873 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1365665525 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:42 PM PDT 24 2387411817 ps
T874 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2752703779 Aug 08 05:44:56 PM PDT 24 Aug 08 05:44:58 PM PDT 24 321799408 ps
T875 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4201463446 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:50 PM PDT 24 4902748244 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.476181024 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:50 PM PDT 24 517888150 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1846168834 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:38 PM PDT 24 3935931281 ps
T878 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3251792446 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:39 PM PDT 24 488340629 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.779721126 Aug 08 05:44:54 PM PDT 24 Aug 08 05:44:58 PM PDT 24 3543587517 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3974120797 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:38 PM PDT 24 582256760 ps
T101 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2656092346 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:52 PM PDT 24 8063796049 ps
T881 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3361601820 Aug 08 05:44:53 PM PDT 24 Aug 08 05:44:54 PM PDT 24 537416364 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.86174069 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:46 PM PDT 24 1305163935 ps
T883 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2431162403 Aug 08 05:44:52 PM PDT 24 Aug 08 05:44:53 PM PDT 24 458001496 ps
T884 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.770877621 Aug 08 05:44:47 PM PDT 24 Aug 08 05:44:56 PM PDT 24 2618474980 ps
T885 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3692519815 Aug 08 05:44:45 PM PDT 24 Aug 08 05:44:46 PM PDT 24 434274564 ps
T886 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3832935729 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:43 PM PDT 24 424710735 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3504254171 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:31 PM PDT 24 1242816163 ps
T888 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2249542139 Aug 08 05:44:52 PM PDT 24 Aug 08 05:44:53 PM PDT 24 335450556 ps
T889 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.364526527 Aug 08 05:44:35 PM PDT 24 Aug 08 05:44:37 PM PDT 24 434934209 ps
T890 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2463243967 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:40 PM PDT 24 447648757 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2845303040 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:28 PM PDT 24 522871809 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4043914795 Aug 08 05:44:40 PM PDT 24 Aug 08 05:44:42 PM PDT 24 358955692 ps
T893 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1412489945 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:41 PM PDT 24 501776937 ps
T894 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.205809752 Aug 08 05:44:51 PM PDT 24 Aug 08 05:44:52 PM PDT 24 341474245 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1791159689 Aug 08 05:44:42 PM PDT 24 Aug 08 05:44:43 PM PDT 24 564787225 ps
T896 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3095901113 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:40 PM PDT 24 431276987 ps
T897 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.166942718 Aug 08 05:44:50 PM PDT 24 Aug 08 05:44:52 PM PDT 24 416011081 ps
T898 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.310752775 Aug 08 05:44:40 PM PDT 24 Aug 08 05:44:41 PM PDT 24 546073276 ps
T899 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3588600126 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:45 PM PDT 24 8487520667 ps
T900 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.333984673 Aug 08 05:44:39 PM PDT 24 Aug 08 05:44:41 PM PDT 24 524386344 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2208982483 Aug 08 05:44:27 PM PDT 24 Aug 08 05:44:28 PM PDT 24 312893603 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1377347589 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:39 PM PDT 24 432222008 ps
T903 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2072819092 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:44 PM PDT 24 8157575626 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3085740940 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:40 PM PDT 24 521126494 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.642067376 Aug 08 05:44:25 PM PDT 24 Aug 08 05:44:32 PM PDT 24 8529392846 ps
T906 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3633615740 Aug 08 05:44:52 PM PDT 24 Aug 08 05:44:53 PM PDT 24 367958836 ps
T907 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2441198587 Aug 08 05:44:52 PM PDT 24 Aug 08 05:44:53 PM PDT 24 347601735 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2446503806 Aug 08 05:44:43 PM PDT 24 Aug 08 05:44:46 PM PDT 24 2026124366 ps
T909 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1726094182 Aug 08 05:44:51 PM PDT 24 Aug 08 05:44:53 PM PDT 24 513028768 ps
T910 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.906435618 Aug 08 05:44:48 PM PDT 24 Aug 08 05:44:59 PM PDT 24 5245133686 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2195172871 Aug 08 05:44:26 PM PDT 24 Aug 08 05:44:29 PM PDT 24 516177966 ps
T912 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1558553790 Aug 08 05:44:35 PM PDT 24 Aug 08 05:44:47 PM PDT 24 3758286107 ps
T913 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2143721591 Aug 08 05:44:38 PM PDT 24 Aug 08 05:44:40 PM PDT 24 765734429 ps
T914 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3078720408 Aug 08 05:44:36 PM PDT 24 Aug 08 05:44:42 PM PDT 24 2831158582 ps
T915 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.730995203 Aug 08 05:44:37 PM PDT 24 Aug 08 05:44:38 PM PDT 24 519049452 ps
T916 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3286539214 Aug 08 05:44:46 PM PDT 24 Aug 08 05:44:47 PM PDT 24 380179376 ps
T917 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.588949078 Aug 08 05:44:50 PM PDT 24 Aug 08 05:44:51 PM PDT 24 362682394 ps
T918 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3404638536 Aug 08 05:44:28 PM PDT 24 Aug 08 05:44:30 PM PDT 24 535126350 ps

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3279251188
Short name T5
Test name
Test status
Simulation time 245372696848 ps
CPU time 141.69 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:49:14 PM PDT 24
Peak memory 201460 kb
Host smart-578839fc-2e61-4ac1-b72a-1ce42c4b60e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279251188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3279251188
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1616110941
Short name T46
Test name
Test status
Simulation time 1623646378645 ps
CPU time 445.33 seconds
Started Aug 08 05:50:23 PM PDT 24
Finished Aug 08 05:57:48 PM PDT 24
Peak memory 210236 kb
Host smart-9c1c9a63-3f62-4db6-8b7b-373b0a6a8c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616110941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1616110941
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1094479195
Short name T58
Test name
Test status
Simulation time 459235221401 ps
CPU time 278.59 seconds
Started Aug 08 05:46:32 PM PDT 24
Finished Aug 08 05:51:10 PM PDT 24
Peak memory 209720 kb
Host smart-06902555-a768-41d9-8d18-f72c6b45c9c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094479195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1094479195
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3751851654
Short name T3
Test name
Test status
Simulation time 493418519659 ps
CPU time 203.21 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:52:03 PM PDT 24
Peak memory 201432 kb
Host smart-bdf87d6f-5490-4e73-8dda-38632ebc30df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751851654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3751851654
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4176713041
Short name T21
Test name
Test status
Simulation time 511314583992 ps
CPU time 277.62 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:53:17 PM PDT 24
Peak memory 209804 kb
Host smart-d0a3d4f5-7727-42d0-98f9-7c47f6fd8b64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176713041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4176713041
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1031583834
Short name T205
Test name
Test status
Simulation time 1414111821273 ps
CPU time 1094.23 seconds
Started Aug 08 05:48:15 PM PDT 24
Finished Aug 08 06:06:30 PM PDT 24
Peak memory 210020 kb
Host smart-8bd5a269-fff3-4a09-8153-678a71b6b7a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031583834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1031583834
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1847777631
Short name T55
Test name
Test status
Simulation time 538370594144 ps
CPU time 150.11 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:48:15 PM PDT 24
Peak memory 201416 kb
Host smart-bed3a06f-b12e-45ae-b205-531da215dfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847777631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1847777631
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2211294888
Short name T158
Test name
Test status
Simulation time 616569052338 ps
CPU time 358.01 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:55:29 PM PDT 24
Peak memory 201436 kb
Host smart-b47de194-f8f7-40e5-8070-c5759d79bac2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211294888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2211294888
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3048084775
Short name T244
Test name
Test status
Simulation time 555165185951 ps
CPU time 852.91 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 06:03:23 PM PDT 24
Peak memory 201436 kb
Host smart-f67708b9-bdcd-412a-8f5e-5bf7df20573c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048084775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3048084775
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.644149028
Short name T73
Test name
Test status
Simulation time 245258195053 ps
CPU time 140.02 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:50:10 PM PDT 24
Peak memory 217704 kb
Host smart-6bfb0da6-74d6-471d-9dd9-0d5c03d3ad62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644149028 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.644149028
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.784215447
Short name T234
Test name
Test status
Simulation time 523842628478 ps
CPU time 580.8 seconds
Started Aug 08 05:49:29 PM PDT 24
Finished Aug 08 05:59:10 PM PDT 24
Peak memory 201308 kb
Host smart-c1bab30f-d414-478a-9945-f1179fd83f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784215447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.784215447
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.63128625
Short name T160
Test name
Test status
Simulation time 491856721106 ps
CPU time 304.17 seconds
Started Aug 08 05:50:20 PM PDT 24
Finished Aug 08 05:55:24 PM PDT 24
Peak memory 201484 kb
Host smart-54244246-2103-4b4e-a464-492664157ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63128625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.63128625
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.517616968
Short name T92
Test name
Test status
Simulation time 564022810 ps
CPU time 2.88 seconds
Started Aug 08 05:44:43 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201704 kb
Host smart-b315463e-ce94-48ab-83fd-f4a0738565a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517616968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.517616968
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.891979569
Short name T42
Test name
Test status
Simulation time 369341267246 ps
CPU time 826.67 seconds
Started Aug 08 05:46:07 PM PDT 24
Finished Aug 08 05:59:54 PM PDT 24
Peak memory 201444 kb
Host smart-a5ca13f3-b7dc-4ab7-bc82-2ec7b6ac1d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891979569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
891979569
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1839645057
Short name T154
Test name
Test status
Simulation time 553223440637 ps
CPU time 1357.34 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 06:08:47 PM PDT 24
Peak memory 201516 kb
Host smart-e4b01b97-385d-4365-a533-ab51f7423c84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839645057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1839645057
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2528386653
Short name T26
Test name
Test status
Simulation time 421500108 ps
CPU time 1.16 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:45:53 PM PDT 24
Peak memory 201256 kb
Host smart-320e9319-36d6-4bb7-9e6b-0a1d718b7f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528386653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2528386653
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1416723819
Short name T76
Test name
Test status
Simulation time 53427825211 ps
CPU time 35.47 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:45:20 PM PDT 24
Peak memory 201544 kb
Host smart-65e11c2f-1c5b-480a-b41a-7b279db8788f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416723819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1416723819
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4041502934
Short name T33
Test name
Test status
Simulation time 432818849155 ps
CPU time 381.4 seconds
Started Aug 08 05:45:29 PM PDT 24
Finished Aug 08 05:51:51 PM PDT 24
Peak memory 201492 kb
Host smart-57a75c0f-1865-47bb-b866-ff0e3db79210
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041502934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4041502934
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4272594448
Short name T256
Test name
Test status
Simulation time 839710854297 ps
CPU time 1826.84 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 06:16:01 PM PDT 24
Peak memory 201468 kb
Host smart-4864a026-1a4e-4a7d-9841-4ab6a99e9a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272594448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4272594448
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2229071325
Short name T86
Test name
Test status
Simulation time 8387019000 ps
CPU time 18.28 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:45:42 PM PDT 24
Peak memory 218244 kb
Host smart-19490731-a9d3-49f7-b6c6-f502c50eec9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229071325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2229071325
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2310519866
Short name T152
Test name
Test status
Simulation time 511974569742 ps
CPU time 299.33 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:54:58 PM PDT 24
Peak memory 201452 kb
Host smart-3ebf3589-0f9c-441d-b6ab-60ee6012f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310519866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2310519866
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1506393329
Short name T238
Test name
Test status
Simulation time 530155371867 ps
CPU time 1236.32 seconds
Started Aug 08 05:45:46 PM PDT 24
Finished Aug 08 06:06:23 PM PDT 24
Peak memory 201472 kb
Host smart-ab11a1ea-609e-49e5-b637-eb1178ce3b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506393329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1506393329
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3361327331
Short name T15
Test name
Test status
Simulation time 165242985417 ps
CPU time 94.29 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:47:32 PM PDT 24
Peak memory 201424 kb
Host smart-b495ed42-0f86-4ad5-9c56-7901dc0a9b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361327331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3361327331
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.99104549
Short name T204
Test name
Test status
Simulation time 1780472221252 ps
CPU time 906.56 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 06:01:13 PM PDT 24
Peak memory 210080 kb
Host smart-e1495cee-5796-482d-b17f-95ab300c65ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99104549 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.99104549
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.4263910707
Short name T247
Test name
Test status
Simulation time 347560107559 ps
CPU time 238.23 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:51:03 PM PDT 24
Peak memory 201496 kb
Host smart-0c5d109d-f9dd-4d56-8ed7-c6b6962dd341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263910707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4263910707
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1405034390
Short name T11
Test name
Test status
Simulation time 326834528454 ps
CPU time 231.67 seconds
Started Aug 08 05:46:18 PM PDT 24
Finished Aug 08 05:50:10 PM PDT 24
Peak memory 201560 kb
Host smart-ff0b18ca-1b0f-458d-89e3-73503a85307e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405034390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1405034390
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.914490725
Short name T169
Test name
Test status
Simulation time 163997412539 ps
CPU time 53.35 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:46:42 PM PDT 24
Peak memory 201424 kb
Host smart-2eda197d-f3a6-417b-affd-3ed39c2e5008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914490725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.914490725
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1584971584
Short name T230
Test name
Test status
Simulation time 532410211360 ps
CPU time 684.02 seconds
Started Aug 08 05:48:50 PM PDT 24
Finished Aug 08 06:00:15 PM PDT 24
Peak memory 201424 kb
Host smart-ab372039-b34c-437b-8781-9a6b723e7bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584971584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1584971584
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.575083394
Short name T221
Test name
Test status
Simulation time 447789234318 ps
CPU time 423.71 seconds
Started Aug 08 05:49:49 PM PDT 24
Finished Aug 08 05:56:53 PM PDT 24
Peak memory 210036 kb
Host smart-82e74b4d-22b6-4088-9d87-f54ce2b7ef21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575083394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
575083394
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3023667111
Short name T99
Test name
Test status
Simulation time 8872948827 ps
CPU time 7.41 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201688 kb
Host smart-8c32aa97-34a4-4279-91e1-3e6cbe7e9813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023667111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3023667111
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2956458321
Short name T161
Test name
Test status
Simulation time 370272366154 ps
CPU time 427.94 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:53:03 PM PDT 24
Peak memory 201444 kb
Host smart-fe9c6f5c-3ae8-4ffa-aaa2-739fb2f7a3c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956458321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2956458321
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2983858642
Short name T229
Test name
Test status
Simulation time 481030171640 ps
CPU time 694.48 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 05:57:51 PM PDT 24
Peak memory 201456 kb
Host smart-4c79f9b8-689b-4bdb-a052-6f24b18850fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983858642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2983858642
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4213365260
Short name T261
Test name
Test status
Simulation time 372275067182 ps
CPU time 874.98 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 06:00:29 PM PDT 24
Peak memory 201380 kb
Host smart-30ee62d8-64f1-437d-8057-d73ddbd38be2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213365260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4213365260
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2464873821
Short name T307
Test name
Test status
Simulation time 503229409362 ps
CPU time 224.62 seconds
Started Aug 08 05:46:02 PM PDT 24
Finished Aug 08 05:49:47 PM PDT 24
Peak memory 201420 kb
Host smart-4aa1c9eb-780a-4e49-9435-a7006b106788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464873821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2464873821
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2941667530
Short name T271
Test name
Test status
Simulation time 365298377025 ps
CPU time 769.47 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 06:01:38 PM PDT 24
Peak memory 201536 kb
Host smart-3fee061d-7ee4-4641-af49-949631b7e972
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941667530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2941667530
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.757639814
Short name T277
Test name
Test status
Simulation time 538436948126 ps
CPU time 1168.13 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 06:05:26 PM PDT 24
Peak memory 201448 kb
Host smart-65391bf1-2b74-4426-90d7-c6f6012b3348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757639814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.757639814
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4057813169
Short name T280
Test name
Test status
Simulation time 61702838887 ps
CPU time 139.75 seconds
Started Aug 08 05:49:51 PM PDT 24
Finished Aug 08 05:52:11 PM PDT 24
Peak memory 201588 kb
Host smart-1228aef1-fbd1-4cab-b7b4-b390b1a3c0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057813169 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4057813169
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2339106923
Short name T336
Test name
Test status
Simulation time 552928112441 ps
CPU time 1283.24 seconds
Started Aug 08 05:50:09 PM PDT 24
Finished Aug 08 06:11:32 PM PDT 24
Peak memory 201364 kb
Host smart-0afc4b22-aa05-4936-9283-65bfe263c270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339106923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2339106923
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.84762738
Short name T278
Test name
Test status
Simulation time 336117226581 ps
CPU time 785.88 seconds
Started Aug 08 05:49:12 PM PDT 24
Finished Aug 08 06:02:18 PM PDT 24
Peak memory 201456 kb
Host smart-5e90fcf9-59d7-475c-a039-c737e1234db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84762738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.84762738
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2713547122
Short name T78
Test name
Test status
Simulation time 351069183257 ps
CPU time 56.06 seconds
Started Aug 08 05:46:08 PM PDT 24
Finished Aug 08 05:47:04 PM PDT 24
Peak memory 201316 kb
Host smart-3516fdae-f8cc-4eb2-b84e-982b6a237873
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713547122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2713547122
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1294449755
Short name T224
Test name
Test status
Simulation time 416480068674 ps
CPU time 84.17 seconds
Started Aug 08 05:47:58 PM PDT 24
Finished Aug 08 05:49:22 PM PDT 24
Peak memory 201464 kb
Host smart-3bba0d4e-f64a-4807-abb7-d475f1a2ddc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294449755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1294449755
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2414230884
Short name T91
Test name
Test status
Simulation time 430355255 ps
CPU time 2.68 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:51 PM PDT 24
Peak memory 201616 kb
Host smart-ab62875d-33cc-4b94-a67f-5a86cc4a2b36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414230884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2414230884
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.999715701
Short name T51
Test name
Test status
Simulation time 509445183230 ps
CPU time 799.36 seconds
Started Aug 08 05:45:56 PM PDT 24
Finished Aug 08 05:59:15 PM PDT 24
Peak memory 201460 kb
Host smart-de3f959a-a995-46b8-8ccf-a40dc76c1d90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999715701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.999715701
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2197180644
Short name T177
Test name
Test status
Simulation time 332182314258 ps
CPU time 57.04 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:46:49 PM PDT 24
Peak memory 201452 kb
Host smart-b90eb7c0-6028-4ed5-ba76-44ec91dc2e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197180644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2197180644
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.455403359
Short name T156
Test name
Test status
Simulation time 487075283862 ps
CPU time 128.64 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:48:41 PM PDT 24
Peak memory 201404 kb
Host smart-71a6185c-ff96-4415-9d8d-1bf10c90ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455403359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.455403359
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.300969020
Short name T266
Test name
Test status
Simulation time 357029412906 ps
CPU time 129.74 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:49:15 PM PDT 24
Peak memory 201428 kb
Host smart-1ebcec0c-b9b2-4f75-a57f-8f1721bf20b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300969020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.300969020
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3033598132
Short name T68
Test name
Test status
Simulation time 131196470134 ps
CPU time 170.87 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:48:39 PM PDT 24
Peak memory 217812 kb
Host smart-aee2da16-2ba5-440e-8689-85a5815aea7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033598132 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3033598132
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4289590848
Short name T296
Test name
Test status
Simulation time 497479188320 ps
CPU time 413.43 seconds
Started Aug 08 05:45:41 PM PDT 24
Finished Aug 08 05:52:35 PM PDT 24
Peak memory 201424 kb
Host smart-48387e6b-d2cb-49bc-81d3-b3d85d058d94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289590848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4289590848
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2403352456
Short name T129
Test name
Test status
Simulation time 584375492 ps
CPU time 1.14 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201384 kb
Host smart-648b23c6-8455-4251-bcc0-54d0caa2852c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403352456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2403352456
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1027188054
Short name T157
Test name
Test status
Simulation time 200667596505 ps
CPU time 117.53 seconds
Started Aug 08 05:46:01 PM PDT 24
Finished Aug 08 05:47:58 PM PDT 24
Peak memory 201432 kb
Host smart-b626b7e0-e3fa-4f1b-aae3-164ce7ba4a52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027188054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1027188054
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1821020487
Short name T240
Test name
Test status
Simulation time 532780659187 ps
CPU time 1292.05 seconds
Started Aug 08 05:49:00 PM PDT 24
Finished Aug 08 06:10:33 PM PDT 24
Peak memory 201436 kb
Host smart-1fa7f261-4f36-4dd5-ae63-dc3ca29e9225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821020487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1821020487
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4103330319
Short name T249
Test name
Test status
Simulation time 347896744503 ps
CPU time 724.35 seconds
Started Aug 08 05:50:18 PM PDT 24
Finished Aug 08 06:02:22 PM PDT 24
Peak memory 201352 kb
Host smart-75b89e3b-c86b-4b24-a54c-327bf7e6e2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103330319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4103330319
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3893616543
Short name T24
Test name
Test status
Simulation time 180988234171 ps
CPU time 40.32 seconds
Started Aug 08 05:50:01 PM PDT 24
Finished Aug 08 05:50:41 PM PDT 24
Peak memory 201580 kb
Host smart-18112194-710a-487a-8242-e500fd318e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893616543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3893616543
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1943119370
Short name T304
Test name
Test status
Simulation time 159419698596 ps
CPU time 378.18 seconds
Started Aug 08 05:45:32 PM PDT 24
Finished Aug 08 05:51:50 PM PDT 24
Peak memory 201528 kb
Host smart-b560a8b1-fe8c-447e-989e-9294c277d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943119370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1943119370
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.813561390
Short name T341
Test name
Test status
Simulation time 341789211586 ps
CPU time 829.4 seconds
Started Aug 08 05:45:32 PM PDT 24
Finished Aug 08 05:59:22 PM PDT 24
Peak memory 201480 kb
Host smart-7c3d2cda-5e1a-4a10-97db-8a55b2f43c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813561390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.813561390
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.149490992
Short name T270
Test name
Test status
Simulation time 355541391102 ps
CPU time 322.32 seconds
Started Aug 08 05:48:03 PM PDT 24
Finished Aug 08 05:53:26 PM PDT 24
Peak memory 201480 kb
Host smart-9496c359-e003-468e-9028-b3b8cb6f6e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149490992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.149490992
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4210669689
Short name T175
Test name
Test status
Simulation time 336780676764 ps
CPU time 103.51 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 05:49:56 PM PDT 24
Peak memory 201408 kb
Host smart-1ac9cb8b-393d-4213-a70d-6a46ff55c14d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210669689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4210669689
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3191774266
Short name T235
Test name
Test status
Simulation time 519629355033 ps
CPU time 1200.07 seconds
Started Aug 08 05:48:29 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 201456 kb
Host smart-4f884492-d586-492e-a431-533193b35516
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191774266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3191774266
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2746740137
Short name T38
Test name
Test status
Simulation time 162796956719 ps
CPU time 102.52 seconds
Started Aug 08 05:45:29 PM PDT 24
Finished Aug 08 05:47:12 PM PDT 24
Peak memory 201436 kb
Host smart-fe978a34-60ec-46e4-ae15-61532ead80da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746740137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2746740137
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.401512011
Short name T206
Test name
Test status
Simulation time 138421329150 ps
CPU time 736.32 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 05:58:40 PM PDT 24
Peak memory 201744 kb
Host smart-6cda951f-2a41-467c-b54d-62026827ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401512011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.401512011
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3730341748
Short name T288
Test name
Test status
Simulation time 818478707744 ps
CPU time 939.69 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 06:01:18 PM PDT 24
Peak memory 218192 kb
Host smart-11a721d4-5e2f-4643-8ac5-2cd505c48368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730341748 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3730341748
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3263644318
Short name T259
Test name
Test status
Simulation time 366916941846 ps
CPU time 438.95 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:53:14 PM PDT 24
Peak memory 201488 kb
Host smart-505f9da5-7061-45dd-a24b-755e1391bf4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263644318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3263644318
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2752026707
Short name T324
Test name
Test status
Simulation time 35825502061 ps
CPU time 57.56 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:47:39 PM PDT 24
Peak memory 210152 kb
Host smart-257a430c-3098-4adb-879a-3216a3a729d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752026707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2752026707
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4236394943
Short name T264
Test name
Test status
Simulation time 183718856626 ps
CPU time 234.93 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:51:00 PM PDT 24
Peak memory 201460 kb
Host smart-49cd67b9-8858-4c61-b475-c2bd82ede9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236394943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4236394943
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.283827175
Short name T321
Test name
Test status
Simulation time 332077090748 ps
CPU time 375.96 seconds
Started Aug 08 05:48:00 PM PDT 24
Finished Aug 08 05:54:16 PM PDT 24
Peak memory 201460 kb
Host smart-b73db62e-5842-4d12-bdde-f457e0277193
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283827175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.283827175
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1635861935
Short name T291
Test name
Test status
Simulation time 493485660914 ps
CPU time 308.31 seconds
Started Aug 08 05:48:38 PM PDT 24
Finished Aug 08 05:53:47 PM PDT 24
Peak memory 201432 kb
Host smart-a6e8408a-2de2-4e4e-ba78-ffdeffb4b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635861935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1635861935
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2694755792
Short name T257
Test name
Test status
Simulation time 557015698934 ps
CPU time 609.09 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:56:04 PM PDT 24
Peak memory 201456 kb
Host smart-0fa894ee-cb60-4122-b974-a672d6e669cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694755792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2694755792
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1097133886
Short name T292
Test name
Test status
Simulation time 529142328741 ps
CPU time 1176.93 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 06:05:27 PM PDT 24
Peak memory 201360 kb
Host smart-1e798954-269d-4c6f-873f-b0ea0458d955
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097133886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1097133886
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3645362341
Short name T300
Test name
Test status
Simulation time 337675786842 ps
CPU time 815.32 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:59:28 PM PDT 24
Peak memory 201460 kb
Host smart-f2917b95-b96f-4478-8b03-0776a1fc2844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645362341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3645362341
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.483592706
Short name T346
Test name
Test status
Simulation time 134941297745 ps
CPU time 410.29 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:52:43 PM PDT 24
Peak memory 201784 kb
Host smart-b6b5476d-ff91-413e-a712-e2b825b7c983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483592706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.483592706
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1254064409
Short name T165
Test name
Test status
Simulation time 386181998475 ps
CPU time 113.05 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:47:59 PM PDT 24
Peak memory 201416 kb
Host smart-d795cffd-b3c0-4f3b-a224-721b1063b0ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254064409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1254064409
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3953827854
Short name T207
Test name
Test status
Simulation time 86141521478 ps
CPU time 432.24 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:53:23 PM PDT 24
Peak memory 201908 kb
Host smart-d1fee982-da23-47e5-900a-2f6f4be056ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953827854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3953827854
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.806624892
Short name T217
Test name
Test status
Simulation time 108959804389 ps
CPU time 413.57 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:52:58 PM PDT 24
Peak memory 201732 kb
Host smart-d040c977-d412-4b32-8bdc-8135a4b6fa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806624892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.806624892
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3510526489
Short name T335
Test name
Test status
Simulation time 333638897282 ps
CPU time 764.6 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:59:18 PM PDT 24
Peak memory 201468 kb
Host smart-a23cca36-91f7-4d15-a68a-8addf3272c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510526489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3510526489
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.34396376
Short name T328
Test name
Test status
Simulation time 344307213752 ps
CPU time 55.36 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:47:28 PM PDT 24
Peak memory 201552 kb
Host smart-064436ee-713b-4478-bbb2-e5c14e753019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34396376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.34396376
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2635125906
Short name T348
Test name
Test status
Simulation time 125420251244 ps
CPU time 594.44 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:56:47 PM PDT 24
Peak memory 201852 kb
Host smart-98c5b2ad-2004-4dee-8261-aca342b86c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635125906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2635125906
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1317023055
Short name T347
Test name
Test status
Simulation time 125841354122 ps
CPU time 424.85 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:54:09 PM PDT 24
Peak memory 201816 kb
Host smart-1d4bdddd-b400-46dc-9c40-58f617542d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317023055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1317023055
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2257633544
Short name T294
Test name
Test status
Simulation time 53754781993 ps
CPU time 112.01 seconds
Started Aug 08 05:47:54 PM PDT 24
Finished Aug 08 05:49:47 PM PDT 24
Peak memory 208312 kb
Host smart-5fc4429d-ef57-473a-b617-2b152c77a904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257633544 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2257633544
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3341993593
Short name T215
Test name
Test status
Simulation time 105515302256 ps
CPU time 366.12 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:54:45 PM PDT 24
Peak memory 201792 kb
Host smart-a4e53e97-7db5-461b-ba66-cb13ef3ff7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341993593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3341993593
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3603798596
Short name T265
Test name
Test status
Simulation time 492768140867 ps
CPU time 1105.73 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 06:04:02 PM PDT 24
Peak memory 201440 kb
Host smart-2be01caf-c7a0-46c9-8ddd-3f8fd64577f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603798596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3603798596
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3778328196
Short name T241
Test name
Test status
Simulation time 353744812621 ps
CPU time 240.2 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:54:27 PM PDT 24
Peak memory 201464 kb
Host smart-5e6a9fa7-5399-4203-ba0a-47fd7ff540b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778328196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3778328196
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2393673156
Short name T863
Test name
Test status
Simulation time 755908150 ps
CPU time 1.77 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201572 kb
Host smart-73905610-ebdf-4099-bcc5-ca3b2d50c88f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393673156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2393673156
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2447652690
Short name T844
Test name
Test status
Simulation time 27123187323 ps
CPU time 30.43 seconds
Started Aug 08 05:44:33 PM PDT 24
Finished Aug 08 05:45:03 PM PDT 24
Peak memory 201536 kb
Host smart-922c90e9-d027-4f92-b34e-4372d92febe5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447652690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2447652690
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.161785517
Short name T802
Test name
Test status
Simulation time 658306845 ps
CPU time 0.87 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:29 PM PDT 24
Peak memory 201284 kb
Host smart-71c303b9-6a94-44f8-9dd9-7d330e3d0279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161785517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.161785517
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1515676637
Short name T818
Test name
Test status
Simulation time 514644441 ps
CPU time 1.3 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:30 PM PDT 24
Peak memory 201508 kb
Host smart-db061956-337e-46b1-a4b8-0fc5fade89e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515676637 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1515676637
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3496023635
Short name T855
Test name
Test status
Simulation time 447846967 ps
CPU time 1.62 seconds
Started Aug 08 05:44:25 PM PDT 24
Finished Aug 08 05:44:27 PM PDT 24
Peak memory 201320 kb
Host smart-9cf1b84d-22b9-4703-a2de-3eb8c269b51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496023635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3496023635
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.367529175
Short name T143
Test name
Test status
Simulation time 2618897664 ps
CPU time 2.36 seconds
Started Aug 08 05:44:33 PM PDT 24
Finished Aug 08 05:44:35 PM PDT 24
Peak memory 201416 kb
Host smart-c776292b-5ee7-425d-9751-8f78c23f314d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367529175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.367529175
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3706496691
Short name T97
Test name
Test status
Simulation time 315913782 ps
CPU time 1.82 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201492 kb
Host smart-0462cc96-5377-4a99-a91a-5262cfb5f2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706496691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3706496691
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.642067376
Short name T905
Test name
Test status
Simulation time 8529392846 ps
CPU time 7.04 seconds
Started Aug 08 05:44:25 PM PDT 24
Finished Aug 08 05:44:32 PM PDT 24
Peak memory 201656 kb
Host smart-1408a765-e102-4e10-87e1-83c7f1feb99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642067376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.642067376
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.199881431
Short name T127
Test name
Test status
Simulation time 794732130 ps
CPU time 3.23 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:32 PM PDT 24
Peak memory 201396 kb
Host smart-f8762bca-6c28-42b2-9764-f0f223022b76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199881431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.199881431
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3881515507
Short name T130
Test name
Test status
Simulation time 10630358829 ps
CPU time 9.15 seconds
Started Aug 08 05:44:35 PM PDT 24
Finished Aug 08 05:44:44 PM PDT 24
Peak memory 201560 kb
Host smart-1bcc8671-3782-446a-9005-4817ba5096a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881515507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3881515507
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3504254171
Short name T887
Test name
Test status
Simulation time 1242816163 ps
CPU time 3.73 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:31 PM PDT 24
Peak memory 201352 kb
Host smart-fd31809a-1632-4dd5-ad93-48b0a95f88f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504254171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3504254171
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.765976330
Short name T835
Test name
Test status
Simulation time 335215119 ps
CPU time 1.21 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201368 kb
Host smart-689cc11b-e226-4477-8a14-16cee0198d32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765976330 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.765976330
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1879673164
Short name T133
Test name
Test status
Simulation time 437262968 ps
CPU time 1.27 seconds
Started Aug 08 05:44:24 PM PDT 24
Finished Aug 08 05:44:25 PM PDT 24
Peak memory 201328 kb
Host smart-fb7af306-1fd5-4145-a839-cc0a2a505756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879673164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1879673164
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2845303040
Short name T891
Test name
Test status
Simulation time 522871809 ps
CPU time 1.65 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201356 kb
Host smart-152e8c47-ef92-4924-abbc-38627ae7d2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845303040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2845303040
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.727819597
Short name T816
Test name
Test status
Simulation time 2529181486 ps
CPU time 8.46 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201344 kb
Host smart-472abf1f-5904-4a34-b9e0-e96262c0c4ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727819597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.727819597
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3974120797
Short name T880
Test name
Test status
Simulation time 582256760 ps
CPU time 1.83 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201648 kb
Host smart-9bba5048-f312-4076-87d1-f7d579a28395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974120797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3974120797
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2704360888
Short name T80
Test name
Test status
Simulation time 4443277254 ps
CPU time 3.17 seconds
Started Aug 08 05:44:24 PM PDT 24
Finished Aug 08 05:44:27 PM PDT 24
Peak memory 201660 kb
Host smart-ef53be42-8b5e-464b-9fe5-0fb0c5c9c456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704360888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2704360888
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1997793673
Short name T828
Test name
Test status
Simulation time 391161626 ps
CPU time 1.4 seconds
Started Aug 08 05:44:40 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201520 kb
Host smart-96bf1a04-8373-4e27-a8ce-03f66d94dd7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997793673 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1997793673
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.333984673
Short name T900
Test name
Test status
Simulation time 524386344 ps
CPU time 2.1 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201404 kb
Host smart-051ecb3b-6fdc-48d0-91c8-88da531749cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333984673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.333984673
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.730995203
Short name T915
Test name
Test status
Simulation time 519049452 ps
CPU time 0.88 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201352 kb
Host smart-dbec28d5-6e0f-40b2-97d3-3004776d74d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730995203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.730995203
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.906435618
Short name T910
Test name
Test status
Simulation time 5245133686 ps
CPU time 11.45 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:59 PM PDT 24
Peak memory 201520 kb
Host smart-717b3eab-13c5-4c89-9c59-49fd67340f16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906435618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.906435618
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.696707819
Short name T849
Test name
Test status
Simulation time 479306748 ps
CPU time 2.42 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201568 kb
Host smart-003383d7-0401-42c6-95a8-f15597bb4927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696707819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.696707819
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2150605664
Short name T848
Test name
Test status
Simulation time 8851029238 ps
CPU time 21.03 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:45:02 PM PDT 24
Peak memory 201720 kb
Host smart-0c2c0d3f-8d25-44b4-a893-de7282ca0b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150605664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2150605664
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3399730645
Short name T862
Test name
Test status
Simulation time 516035107 ps
CPU time 1.45 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201088 kb
Host smart-7b6ad17d-7a47-4728-8f6f-d58b70444803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399730645 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3399730645
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.275203715
Short name T820
Test name
Test status
Simulation time 452002459 ps
CPU time 1.76 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201324 kb
Host smart-ef9104fd-1c39-48d5-8ea5-db46c212c77a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275203715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.275203715
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3095901113
Short name T896
Test name
Test status
Simulation time 431276987 ps
CPU time 1.09 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 201380 kb
Host smart-5ed0a7b0-c9c7-46a7-ba52-5eb864e794ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095901113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3095901113
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3078720408
Short name T914
Test name
Test status
Simulation time 2831158582 ps
CPU time 5.69 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201280 kb
Host smart-4cb59df4-a729-47ec-a996-5c1ebe55404a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078720408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3078720408
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2143721591
Short name T913
Test name
Test status
Simulation time 765734429 ps
CPU time 2.08 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 201696 kb
Host smart-8514549f-6d23-4422-a6fb-5839a7e6c653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143721591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2143721591
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1288357371
Short name T830
Test name
Test status
Simulation time 8762798644 ps
CPU time 21.53 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:45:03 PM PDT 24
Peak memory 201728 kb
Host smart-4c247741-6699-453f-a72a-b038b296c0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288357371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1288357371
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2308074462
Short name T827
Test name
Test status
Simulation time 548131115 ps
CPU time 1.23 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201360 kb
Host smart-76ac5980-efe6-4929-8ce6-ac777a314b39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308074462 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2308074462
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3712772166
Short name T861
Test name
Test status
Simulation time 398188902 ps
CPU time 1.66 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201356 kb
Host smart-5c57eaac-ab11-4c44-8f38-b896333d7e38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712772166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3712772166
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3832935729
Short name T886
Test name
Test status
Simulation time 424710735 ps
CPU time 0.8 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201224 kb
Host smart-53ace475-a093-40af-992f-e96cef623295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832935729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3832935729
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1558553790
Short name T912
Test name
Test status
Simulation time 3758286107 ps
CPU time 11.53 seconds
Started Aug 08 05:44:35 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201596 kb
Host smart-b964abe7-fc72-4973-95cd-29eef4966301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558553790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1558553790
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1814717598
Short name T95
Test name
Test status
Simulation time 490537353 ps
CPU time 1.64 seconds
Started Aug 08 05:44:34 PM PDT 24
Finished Aug 08 05:44:36 PM PDT 24
Peak memory 201616 kb
Host smart-278d2717-84be-4aff-8557-2e8df0fee8da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814717598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1814717598
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3588600126
Short name T899
Test name
Test status
Simulation time 8487520667 ps
CPU time 7.45 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201700 kb
Host smart-afcf46c5-6ffb-48ea-812f-ff9fba763a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588600126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3588600126
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.371064244
Short name T850
Test name
Test status
Simulation time 472864475 ps
CPU time 1.23 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201376 kb
Host smart-7955e580-a685-4b18-81cc-d12715b008c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371064244 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.371064244
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.637523093
Short name T132
Test name
Test status
Simulation time 301620790 ps
CPU time 1.35 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201360 kb
Host smart-dc26e536-37ad-439d-a51e-eddeb413f686
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637523093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.637523093
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.624657464
Short name T825
Test name
Test status
Simulation time 475775568 ps
CPU time 1.68 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201376 kb
Host smart-fb413077-f917-443a-9b28-38405bb5e7b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624657464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.624657464
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1365665525
Short name T873
Test name
Test status
Simulation time 2387411817 ps
CPU time 3.73 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201440 kb
Host smart-9be9ddf1-6507-410f-a521-b4bd2ba84b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365665525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1365665525
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2688280256
Short name T842
Test name
Test status
Simulation time 612340065 ps
CPU time 2.03 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201552 kb
Host smart-6f0d91cc-2b40-4318-a0d6-c10ec508f667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688280256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2688280256
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1659238988
Short name T83
Test name
Test status
Simulation time 8244375277 ps
CPU time 11.67 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:57 PM PDT 24
Peak memory 201596 kb
Host smart-ef93c2ec-cf23-44e6-9825-9066981f8ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659238988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1659238988
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2019137921
Short name T807
Test name
Test status
Simulation time 436789751 ps
CPU time 1.41 seconds
Started Aug 08 05:44:47 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201408 kb
Host smart-b964da6e-a839-41df-9ee5-2980b8e870a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019137921 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2019137921
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.96089246
Short name T135
Test name
Test status
Simulation time 406333931 ps
CPU time 1.04 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201396 kb
Host smart-c369e51c-6b17-4ed3-ac2c-78b63541295c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96089246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.96089246
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.427575866
Short name T843
Test name
Test status
Simulation time 527689493 ps
CPU time 1.88 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201316 kb
Host smart-604b8242-9924-448c-8b85-d3910d231079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427575866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.427575866
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2446503806
Short name T908
Test name
Test status
Simulation time 2026124366 ps
CPU time 2.95 seconds
Started Aug 08 05:44:43 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201256 kb
Host smart-a73c0dcb-48c6-4e4b-99c9-03af69c1ef66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446503806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2446503806
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2796166791
Short name T872
Test name
Test status
Simulation time 499911096 ps
CPU time 1.42 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201592 kb
Host smart-33fae69d-af14-4574-b256-be699a3c076e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796166791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2796166791
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2966415475
Short name T841
Test name
Test status
Simulation time 4413426351 ps
CPU time 3.99 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 201580 kb
Host smart-e76efee4-6a3b-46b3-a494-500542583f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966415475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2966415475
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.863499125
Short name T82
Test name
Test status
Simulation time 545202009 ps
CPU time 1.35 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201296 kb
Host smart-fa345c24-b5c4-4021-b34a-d77ec17336e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863499125 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.863499125
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2760724865
Short name T836
Test name
Test status
Simulation time 337084460 ps
CPU time 1.52 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:44 PM PDT 24
Peak memory 201316 kb
Host smart-71599b4d-5ffb-464d-aef6-b909eb96dd44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760724865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2760724865
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2463243967
Short name T890
Test name
Test status
Simulation time 447648757 ps
CPU time 1.62 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 201380 kb
Host smart-37b6331e-cf25-4290-baee-50f304ac5c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463243967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2463243967
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2578211252
Short name T865
Test name
Test status
Simulation time 2176764156 ps
CPU time 2.19 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201320 kb
Host smart-a2abd8d3-d9d2-4640-acd8-dfd2f9bba77e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578211252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2578211252
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3342377240
Short name T89
Test name
Test status
Simulation time 762274598 ps
CPU time 2.08 seconds
Started Aug 08 05:44:40 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201572 kb
Host smart-8651e838-d55c-46c5-b5c5-8238d36d7445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342377240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3342377240
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.972132292
Short name T867
Test name
Test status
Simulation time 3977939349 ps
CPU time 5.99 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:48 PM PDT 24
Peak memory 201628 kb
Host smart-4c1e2f52-3093-48e6-94f6-3c1d240a13da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972132292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.972132292
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4286518820
Short name T88
Test name
Test status
Simulation time 524110576 ps
CPU time 1.93 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201292 kb
Host smart-5a6a8ec0-abea-41b6-840c-ca44ce76790b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286518820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.4286518820
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3187342186
Short name T134
Test name
Test status
Simulation time 404246560 ps
CPU time 1.63 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201172 kb
Host smart-bbe2753f-b5bd-4a65-9bbe-b14c1fda790a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187342186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3187342186
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1377347589
Short name T902
Test name
Test status
Simulation time 432222008 ps
CPU time 1.56 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201380 kb
Host smart-6176aa24-cbc5-4d3c-8d34-e72e23775b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377347589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1377347589
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4201463446
Short name T875
Test name
Test status
Simulation time 4902748244 ps
CPU time 12.1 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:50 PM PDT 24
Peak memory 201628 kb
Host smart-ad6c96a9-86b0-448c-8594-a2003dda2b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201463446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4201463446
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2041914535
Short name T94
Test name
Test status
Simulation time 434022121 ps
CPU time 1.97 seconds
Started Aug 08 05:44:46 PM PDT 24
Finished Aug 08 05:44:48 PM PDT 24
Peak memory 201560 kb
Host smart-8c71e53e-0a0d-4b94-9d12-39d244e5d21a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041914535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2041914535
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2656092346
Short name T101
Test name
Test status
Simulation time 8063796049 ps
CPU time 12.79 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:52 PM PDT 24
Peak memory 201588 kb
Host smart-01ed498a-d0ac-4ad2-a9f1-2242b237db5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656092346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2656092346
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3385242318
Short name T113
Test name
Test status
Simulation time 362566464 ps
CPU time 1.63 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201408 kb
Host smart-8c293be1-7bf9-4c52-9dbc-9d81e2246d8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385242318 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3385242318
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.4043914795
Short name T892
Test name
Test status
Simulation time 358955692 ps
CPU time 1.12 seconds
Started Aug 08 05:44:40 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201564 kb
Host smart-da6914a4-07d1-4403-9afd-204188292a5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043914795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.4043914795
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2919571496
Short name T819
Test name
Test status
Simulation time 524543132 ps
CPU time 1.74 seconds
Started Aug 08 05:44:47 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201252 kb
Host smart-0b697014-42fa-4326-aa99-6b6ccaa610cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919571496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2919571496
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.779721126
Short name T879
Test name
Test status
Simulation time 3543587517 ps
CPU time 4.58 seconds
Started Aug 08 05:44:54 PM PDT 24
Finished Aug 08 05:44:58 PM PDT 24
Peak memory 201616 kb
Host smart-aab75a23-f81b-40d7-b61a-b0f5da8a3eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779721126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.779721126
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4273844481
Short name T84
Test name
Test status
Simulation time 4202835937 ps
CPU time 10.19 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201640 kb
Host smart-53877ebc-f490-42af-b703-ebb7adfbfdd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273844481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4273844481
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2752703779
Short name T874
Test name
Test status
Simulation time 321799408 ps
CPU time 1.12 seconds
Started Aug 08 05:44:56 PM PDT 24
Finished Aug 08 05:44:58 PM PDT 24
Peak memory 201464 kb
Host smart-8861ab89-3e66-48ef-b38d-d424a3de234a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752703779 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2752703779
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3286539214
Short name T916
Test name
Test status
Simulation time 380179376 ps
CPU time 0.99 seconds
Started Aug 08 05:44:46 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201292 kb
Host smart-95f3243d-9905-4988-a4bb-0e728cbfa047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286539214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3286539214
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1574624371
Short name T813
Test name
Test status
Simulation time 418714337 ps
CPU time 0.87 seconds
Started Aug 08 05:44:46 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201236 kb
Host smart-72cbf418-539b-4e8b-be11-e0c8f496c30d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574624371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1574624371
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2754533894
Short name T75
Test name
Test status
Simulation time 2126963857 ps
CPU time 2.42 seconds
Started Aug 08 05:44:56 PM PDT 24
Finished Aug 08 05:44:59 PM PDT 24
Peak memory 201568 kb
Host smart-04a0d02e-1981-4c75-a1f2-a12e7d2aca1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754533894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2754533894
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.794530495
Short name T809
Test name
Test status
Simulation time 579634438 ps
CPU time 3.06 seconds
Started Aug 08 05:44:53 PM PDT 24
Finished Aug 08 05:44:56 PM PDT 24
Peak memory 209880 kb
Host smart-37edca3e-72c3-4254-bdd7-52f9ce3888e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794530495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.794530495
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1162067061
Short name T831
Test name
Test status
Simulation time 8582061246 ps
CPU time 5.56 seconds
Started Aug 08 05:44:54 PM PDT 24
Finished Aug 08 05:44:59 PM PDT 24
Peak memory 201684 kb
Host smart-a179e44a-84c5-4358-8abf-08763a037e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162067061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1162067061
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.670613963
Short name T839
Test name
Test status
Simulation time 357318874 ps
CPU time 1.79 seconds
Started Aug 08 05:44:49 PM PDT 24
Finished Aug 08 05:44:51 PM PDT 24
Peak memory 201492 kb
Host smart-72810183-aabc-4725-b06a-38ace6e3811c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670613963 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.670613963
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.610454841
Short name T128
Test name
Test status
Simulation time 331227064 ps
CPU time 1.47 seconds
Started Aug 08 05:44:55 PM PDT 24
Finished Aug 08 05:44:57 PM PDT 24
Peak memory 201288 kb
Host smart-f982b949-c394-4779-befa-d83e7eebcf56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610454841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.610454841
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2441198587
Short name T907
Test name
Test status
Simulation time 347601735 ps
CPU time 0.86 seconds
Started Aug 08 05:44:52 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201328 kb
Host smart-4bfd729b-0a6f-4503-a7ca-bff6cc744bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441198587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2441198587
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.770877621
Short name T884
Test name
Test status
Simulation time 2618474980 ps
CPU time 8.6 seconds
Started Aug 08 05:44:47 PM PDT 24
Finished Aug 08 05:44:56 PM PDT 24
Peak memory 201436 kb
Host smart-1ed51920-6f86-4e6c-becc-06adcb9fdfdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770877621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.770877621
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1651877098
Short name T98
Test name
Test status
Simulation time 8814282513 ps
CPU time 7.27 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:56 PM PDT 24
Peak memory 201696 kb
Host smart-a204e17b-ba37-46c6-8f08-2e745ad82e96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651877098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1651877098
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4166156131
Short name T852
Test name
Test status
Simulation time 858069351 ps
CPU time 1.79 seconds
Started Aug 08 05:44:30 PM PDT 24
Finished Aug 08 05:44:32 PM PDT 24
Peak memory 201392 kb
Host smart-f4271643-1a05-4989-bbdb-f679eca3e12a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166156131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4166156131
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1675123597
Short name T131
Test name
Test status
Simulation time 1520464638 ps
CPU time 4.72 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:33 PM PDT 24
Peak memory 201388 kb
Host smart-4edb9d42-445d-4a81-8b15-b66ae0952609
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675123597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1675123597
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.162709922
Short name T853
Test name
Test status
Simulation time 770420873 ps
CPU time 2.35 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201224 kb
Host smart-c56d59ca-c19e-47d7-9df0-fc4b0a2592b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162709922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.162709922
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3992745396
Short name T860
Test name
Test status
Simulation time 406054715 ps
CPU time 1.76 seconds
Started Aug 08 05:44:41 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201524 kb
Host smart-a5ab1e1b-95fd-496a-af88-3076b71ce049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992745396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3992745396
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3125711415
Short name T144
Test name
Test status
Simulation time 489893558 ps
CPU time 0.96 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201340 kb
Host smart-582638b7-b825-4b94-aa9d-406b3ef6e0e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125711415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3125711415
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2208982483
Short name T901
Test name
Test status
Simulation time 312893603 ps
CPU time 0.97 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201292 kb
Host smart-e6a2f817-e291-4b37-a20c-cf4bef23d6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208982483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2208982483
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2871321188
Short name T146
Test name
Test status
Simulation time 4904262767 ps
CPU time 5.34 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:34 PM PDT 24
Peak memory 201492 kb
Host smart-3212a968-4369-4f44-a60c-77b408ef95ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871321188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2871321188
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3795202454
Short name T856
Test name
Test status
Simulation time 462463760 ps
CPU time 3.2 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:29 PM PDT 24
Peak memory 201716 kb
Host smart-6ebd9b7f-52a1-4019-ada8-119e13d9672d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795202454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3795202454
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1326863277
Short name T864
Test name
Test status
Simulation time 4636969911 ps
CPU time 4.02 seconds
Started Aug 08 05:44:29 PM PDT 24
Finished Aug 08 05:44:33 PM PDT 24
Peak memory 201596 kb
Host smart-e49999a7-6177-466a-bd7c-aa71c8795004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326863277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1326863277
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2431162403
Short name T883
Test name
Test status
Simulation time 458001496 ps
CPU time 0.81 seconds
Started Aug 08 05:44:52 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201260 kb
Host smart-a372b88f-1c9d-4f51-8fe4-02b5f2ed06bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431162403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2431162403
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.205809752
Short name T894
Test name
Test status
Simulation time 341474245 ps
CPU time 0.97 seconds
Started Aug 08 05:44:51 PM PDT 24
Finished Aug 08 05:44:52 PM PDT 24
Peak memory 201280 kb
Host smart-c102bc72-ccdb-4f21-9fb2-e247f53b4175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205809752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.205809752
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1206538283
Short name T870
Test name
Test status
Simulation time 505405153 ps
CPU time 0.9 seconds
Started Aug 08 05:44:55 PM PDT 24
Finished Aug 08 05:44:56 PM PDT 24
Peak memory 201260 kb
Host smart-20ddbdad-c54f-44c2-aebd-5cfe32226cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206538283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1206538283
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3583682742
Short name T823
Test name
Test status
Simulation time 407283795 ps
CPU time 1.61 seconds
Started Aug 08 05:44:54 PM PDT 24
Finished Aug 08 05:44:55 PM PDT 24
Peak memory 201332 kb
Host smart-37d41d2f-573f-4699-83bc-3d7b2893e699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583682742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3583682742
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1196772061
Short name T801
Test name
Test status
Simulation time 474975300 ps
CPU time 1.58 seconds
Started Aug 08 05:44:51 PM PDT 24
Finished Aug 08 05:44:52 PM PDT 24
Peak memory 201396 kb
Host smart-d9fd3359-c805-4b70-843a-50d24f951bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196772061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1196772061
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2374477668
Short name T834
Test name
Test status
Simulation time 504009765 ps
CPU time 1.23 seconds
Started Aug 08 05:44:50 PM PDT 24
Finished Aug 08 05:44:51 PM PDT 24
Peak memory 201364 kb
Host smart-c092861e-193f-480e-9f90-13fb64b7d7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374477668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2374477668
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2950645990
Short name T838
Test name
Test status
Simulation time 436837041 ps
CPU time 1.57 seconds
Started Aug 08 05:44:53 PM PDT 24
Finished Aug 08 05:44:55 PM PDT 24
Peak memory 201364 kb
Host smart-62762207-219f-44f3-bfa8-00008cbe13cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950645990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2950645990
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1173406910
Short name T826
Test name
Test status
Simulation time 283138167 ps
CPU time 1.26 seconds
Started Aug 08 05:44:49 PM PDT 24
Finished Aug 08 05:44:50 PM PDT 24
Peak memory 201296 kb
Host smart-5317b176-a720-453a-a550-c0ec63002b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173406910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1173406910
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3407545715
Short name T866
Test name
Test status
Simulation time 430933964 ps
CPU time 0.8 seconds
Started Aug 08 05:44:47 PM PDT 24
Finished Aug 08 05:44:48 PM PDT 24
Peak memory 201380 kb
Host smart-d5d7fc68-5ffd-4828-839c-8cda4c6430f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407545715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3407545715
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1502090165
Short name T803
Test name
Test status
Simulation time 481689457 ps
CPU time 1.76 seconds
Started Aug 08 05:45:00 PM PDT 24
Finished Aug 08 05:45:02 PM PDT 24
Peak memory 201276 kb
Host smart-3e854dbe-9a6a-4ba8-aa17-fb93999dcce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502090165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1502090165
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.935691389
Short name T808
Test name
Test status
Simulation time 1226494658 ps
CPU time 2.94 seconds
Started Aug 08 05:44:30 PM PDT 24
Finished Aug 08 05:44:33 PM PDT 24
Peak memory 201584 kb
Host smart-25585146-d874-4211-8723-5198c416ec63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935691389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.935691389
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3345060046
Short name T138
Test name
Test status
Simulation time 10191720040 ps
CPU time 8.05 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201576 kb
Host smart-be9df3f8-6ba1-4127-815a-ac464929f943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345060046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3345060046
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.787842016
Short name T139
Test name
Test status
Simulation time 1361479225 ps
CPU time 1.53 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201268 kb
Host smart-07bacd31-edfc-4cd4-8e41-205c80d227cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787842016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.787842016
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3087395288
Short name T817
Test name
Test status
Simulation time 428136271 ps
CPU time 1.28 seconds
Started Aug 08 05:44:27 PM PDT 24
Finished Aug 08 05:44:29 PM PDT 24
Peak memory 201496 kb
Host smart-a363f227-fc35-45af-90f8-fdb919afcc88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087395288 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3087395288
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3404638536
Short name T918
Test name
Test status
Simulation time 535126350 ps
CPU time 1.28 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:30 PM PDT 24
Peak memory 201360 kb
Host smart-80017b68-950a-44fb-a48c-956ad297f3f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404638536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3404638536
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3827989564
Short name T824
Test name
Test status
Simulation time 476214369 ps
CPU time 1.16 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:27 PM PDT 24
Peak memory 201192 kb
Host smart-9daeec74-09db-4295-8e65-a3109f8bb40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827989564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3827989564
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1846168834
Short name T877
Test name
Test status
Simulation time 3935931281 ps
CPU time 9.54 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201488 kb
Host smart-f4674323-f998-40d9-a5b5-d7d13815f85c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846168834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1846168834
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2195172871
Short name T911
Test name
Test status
Simulation time 516177966 ps
CPU time 3.4 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:29 PM PDT 24
Peak memory 201532 kb
Host smart-9ae0deb1-0af0-481f-bd6e-eb0ef5f7725d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195172871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2195172871
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4035802117
Short name T100
Test name
Test status
Simulation time 4751062440 ps
CPU time 11.52 seconds
Started Aug 08 05:44:26 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201624 kb
Host smart-5aa6d150-b905-4453-838f-934c9a2c1508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035802117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4035802117
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1726094182
Short name T909
Test name
Test status
Simulation time 513028768 ps
CPU time 1.8 seconds
Started Aug 08 05:44:51 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201280 kb
Host smart-db00e028-dcdc-4477-bf23-8ca9be3604e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726094182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1726094182
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.329603823
Short name T840
Test name
Test status
Simulation time 375399458 ps
CPU time 1.39 seconds
Started Aug 08 05:44:49 PM PDT 24
Finished Aug 08 05:44:51 PM PDT 24
Peak memory 201272 kb
Host smart-e631ffc4-fce5-42b5-9f96-bff4ab5247bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329603823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.329603823
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.166942718
Short name T897
Test name
Test status
Simulation time 416011081 ps
CPU time 1.12 seconds
Started Aug 08 05:44:50 PM PDT 24
Finished Aug 08 05:44:52 PM PDT 24
Peak memory 201384 kb
Host smart-4b62c23f-eddb-483a-a483-02d538e597e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166942718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.166942718
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3692519815
Short name T885
Test name
Test status
Simulation time 434274564 ps
CPU time 0.83 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201396 kb
Host smart-65f4c86f-ac91-425b-88d7-c15499bdc84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692519815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3692519815
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4212465291
Short name T822
Test name
Test status
Simulation time 519030474 ps
CPU time 0.94 seconds
Started Aug 08 05:44:54 PM PDT 24
Finished Aug 08 05:44:55 PM PDT 24
Peak memory 201332 kb
Host smart-afa1ef95-16c5-40dc-868b-8f4bee3601b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212465291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4212465291
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3440612280
Short name T814
Test name
Test status
Simulation time 419883583 ps
CPU time 1.13 seconds
Started Aug 08 05:44:50 PM PDT 24
Finished Aug 08 05:44:52 PM PDT 24
Peak memory 201236 kb
Host smart-7e3fb8bf-8e34-4561-be9f-b843e93a4237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440612280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3440612280
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.974166234
Short name T805
Test name
Test status
Simulation time 345066687 ps
CPU time 1.4 seconds
Started Aug 08 05:44:49 PM PDT 24
Finished Aug 08 05:44:50 PM PDT 24
Peak memory 201236 kb
Host smart-b6cfd1fe-8948-4883-ac72-98cd1c6373fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974166234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.974166234
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3294697317
Short name T800
Test name
Test status
Simulation time 512490451 ps
CPU time 0.97 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201380 kb
Host smart-b7b078dc-88e9-4d8b-859b-453f4e9cb04e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294697317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3294697317
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2249542139
Short name T888
Test name
Test status
Simulation time 335450556 ps
CPU time 0.86 seconds
Started Aug 08 05:44:52 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201288 kb
Host smart-6f3aa500-3521-42d2-93ad-e98dbc5e6448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249542139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2249542139
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1045423663
Short name T804
Test name
Test status
Simulation time 453368499 ps
CPU time 1.29 seconds
Started Aug 08 05:44:52 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201324 kb
Host smart-53318d9b-f409-40a5-be1d-bb26cd57d488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045423663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1045423663
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3885042945
Short name T869
Test name
Test status
Simulation time 1420077690 ps
CPU time 3.12 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201404 kb
Host smart-89c421a4-756d-4e06-8638-001e6ac5b9dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885042945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3885042945
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.86174069
Short name T882
Test name
Test status
Simulation time 1305163935 ps
CPU time 3.92 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201380 kb
Host smart-757da3ef-e58a-401f-a7a6-aa3b8c0b710a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86174069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_res
et.86174069
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1791159689
Short name T895
Test name
Test status
Simulation time 564787225 ps
CPU time 1.29 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 209736 kb
Host smart-54dbe06c-f433-447b-8f3c-5de8670c351b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791159689 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1791159689
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1578957223
Short name T137
Test name
Test status
Simulation time 413818040 ps
CPU time 1.19 seconds
Started Aug 08 05:44:43 PM PDT 24
Finished Aug 08 05:44:44 PM PDT 24
Peak memory 201388 kb
Host smart-49190e5f-b7f5-4132-a5fa-1123b2967349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578957223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1578957223
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4262061352
Short name T845
Test name
Test status
Simulation time 471490677 ps
CPU time 0.74 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:29 PM PDT 24
Peak memory 201312 kb
Host smart-c2d266fb-23d4-4a60-8c26-b9fe41b36eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262061352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4262061352
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.717238981
Short name T142
Test name
Test status
Simulation time 4546014190 ps
CPU time 3.75 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:43 PM PDT 24
Peak memory 201544 kb
Host smart-f6367f35-be41-44e0-9482-24f717c9e81d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717238981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.717238981
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.761075133
Short name T833
Test name
Test status
Simulation time 564732027 ps
CPU time 3.02 seconds
Started Aug 08 05:44:24 PM PDT 24
Finished Aug 08 05:44:28 PM PDT 24
Peak memory 201668 kb
Host smart-7051b22d-a606-458c-a39f-7dbfc4de113c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761075133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.761075133
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.295292227
Short name T81
Test name
Test status
Simulation time 8856808673 ps
CPU time 7.35 seconds
Started Aug 08 05:44:28 PM PDT 24
Finished Aug 08 05:44:35 PM PDT 24
Peak memory 201696 kb
Host smart-fcbdae2e-c403-475c-9ef0-94d1c85c1ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295292227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.295292227
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3633615740
Short name T906
Test name
Test status
Simulation time 367958836 ps
CPU time 0.82 seconds
Started Aug 08 05:44:52 PM PDT 24
Finished Aug 08 05:44:53 PM PDT 24
Peak memory 201236 kb
Host smart-c5efb6d5-f828-476c-a146-4007b8d25e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633615740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3633615740
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4153922123
Short name T846
Test name
Test status
Simulation time 430989994 ps
CPU time 0.87 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201304 kb
Host smart-8d36466a-41ae-4336-82dc-ef93c0beddd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153922123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4153922123
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.928456114
Short name T812
Test name
Test status
Simulation time 552565677 ps
CPU time 0.93 seconds
Started Aug 08 05:44:49 PM PDT 24
Finished Aug 08 05:44:50 PM PDT 24
Peak memory 201276 kb
Host smart-e7036765-ac71-4274-9010-ce55c8006fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928456114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.928456114
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3520254758
Short name T832
Test name
Test status
Simulation time 486745674 ps
CPU time 1.04 seconds
Started Aug 08 05:44:46 PM PDT 24
Finished Aug 08 05:44:47 PM PDT 24
Peak memory 201184 kb
Host smart-72a92566-f93e-4b70-aece-cc78cfb3bf54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520254758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3520254758
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3361601820
Short name T881
Test name
Test status
Simulation time 537416364 ps
CPU time 0.76 seconds
Started Aug 08 05:44:53 PM PDT 24
Finished Aug 08 05:44:54 PM PDT 24
Peak memory 201240 kb
Host smart-5a08e65e-2411-46ae-afea-030f9a5073a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361601820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3361601820
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1411817103
Short name T847
Test name
Test status
Simulation time 431074315 ps
CPU time 1.67 seconds
Started Aug 08 05:44:55 PM PDT 24
Finished Aug 08 05:44:57 PM PDT 24
Peak memory 201572 kb
Host smart-d4eb71a4-9caf-419c-974f-437fb3198447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411817103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1411817103
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.588949078
Short name T917
Test name
Test status
Simulation time 362682394 ps
CPU time 0.86 seconds
Started Aug 08 05:44:50 PM PDT 24
Finished Aug 08 05:44:51 PM PDT 24
Peak memory 201324 kb
Host smart-84c7cf22-8ba2-49ab-92e9-d63c2781d89c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588949078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.588949078
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3494473818
Short name T797
Test name
Test status
Simulation time 509729152 ps
CPU time 1.75 seconds
Started Aug 08 05:44:47 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201404 kb
Host smart-880f8c5a-8902-48df-a5ba-243aac9d24de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494473818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3494473818
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.231505449
Short name T854
Test name
Test status
Simulation time 307479947 ps
CPU time 0.96 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201556 kb
Host smart-6eb2ba1c-61c7-4ddf-b814-2312436c9428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231505449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.231505449
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.425490135
Short name T798
Test name
Test status
Simulation time 508814751 ps
CPU time 0.94 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201296 kb
Host smart-86558fb3-2844-4361-beed-6489ed0f080e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425490135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.425490135
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1839704335
Short name T806
Test name
Test status
Simulation time 429487906 ps
CPU time 1.25 seconds
Started Aug 08 05:44:44 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201344 kb
Host smart-0c96019d-e992-495c-83bc-4419a9af5be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839704335 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1839704335
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.284897575
Short name T136
Test name
Test status
Simulation time 435266745 ps
CPU time 1.85 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201324 kb
Host smart-08d74465-db4c-4a5f-88a7-4d73a58f9847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284897575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.284897575
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.327080462
Short name T871
Test name
Test status
Simulation time 399091293 ps
CPU time 0.86 seconds
Started Aug 08 05:44:35 PM PDT 24
Finished Aug 08 05:44:36 PM PDT 24
Peak memory 201276 kb
Host smart-4b36b849-39fd-431a-8ade-e78f8c073542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327080462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.327080462
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3794380250
Short name T851
Test name
Test status
Simulation time 2465595395 ps
CPU time 8.09 seconds
Started Aug 08 05:44:34 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201468 kb
Host smart-3ab2b6ec-34d8-483c-8b30-17d1f8ee9ae2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794380250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3794380250
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3275068722
Short name T96
Test name
Test status
Simulation time 641120236 ps
CPU time 2.29 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201680 kb
Host smart-16ab1e4d-a768-448d-a313-e4adb76e0ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275068722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3275068722
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3041057884
Short name T79
Test name
Test status
Simulation time 4970481561 ps
CPU time 2.22 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201660 kb
Host smart-67652afd-f55a-4fe1-b378-bfe6e700e200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041057884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3041057884
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.101188908
Short name T810
Test name
Test status
Simulation time 688842784 ps
CPU time 1.17 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201532 kb
Host smart-3629bf3f-766a-44bd-84fe-d7f5c7128400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101188908 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.101188908
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1603932071
Short name T141
Test name
Test status
Simulation time 461198679 ps
CPU time 0.91 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201268 kb
Host smart-3c760025-bb55-417d-a4fa-e86cd3708abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603932071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1603932071
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2456839084
Short name T799
Test name
Test status
Simulation time 477358061 ps
CPU time 0.81 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201264 kb
Host smart-35260d51-c92f-414e-a869-e03c44603ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456839084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2456839084
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1877467107
Short name T145
Test name
Test status
Simulation time 2780674442 ps
CPU time 6.16 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201292 kb
Host smart-4e6c89a4-5cc5-4ab1-b3c6-8585a3f0960d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877467107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1877467107
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3085740940
Short name T904
Test name
Test status
Simulation time 521126494 ps
CPU time 1.67 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:40 PM PDT 24
Peak memory 201600 kb
Host smart-3c33da33-beba-4f5f-a70d-8e669ce38916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085740940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3085740940
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1400486388
Short name T811
Test name
Test status
Simulation time 468659338 ps
CPU time 2 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:44 PM PDT 24
Peak memory 201488 kb
Host smart-43dd2368-7346-4d1b-8095-6310c8ec07e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400486388 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1400486388
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.364526527
Short name T889
Test name
Test status
Simulation time 434934209 ps
CPU time 1.65 seconds
Started Aug 08 05:44:35 PM PDT 24
Finished Aug 08 05:44:37 PM PDT 24
Peak memory 201344 kb
Host smart-cd83c2f6-b7c3-4a3a-82b8-6f754a63f8ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364526527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.364526527
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.476181024
Short name T876
Test name
Test status
Simulation time 517888150 ps
CPU time 1.75 seconds
Started Aug 08 05:44:48 PM PDT 24
Finished Aug 08 05:44:50 PM PDT 24
Peak memory 201236 kb
Host smart-e8f71e4c-534a-4f34-bdd4-a35a8fba3dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476181024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.476181024
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4006450116
Short name T77
Test name
Test status
Simulation time 2324672170 ps
CPU time 4.95 seconds
Started Aug 08 05:44:44 PM PDT 24
Finished Aug 08 05:44:49 PM PDT 24
Peak memory 201272 kb
Host smart-be1905cd-1326-47f9-b267-c7ef4056dfa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006450116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4006450116
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1500507990
Short name T821
Test name
Test status
Simulation time 844772503 ps
CPU time 2.1 seconds
Started Aug 08 05:44:38 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201672 kb
Host smart-74745034-9d7e-4680-a364-a2cd879a7b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500507990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1500507990
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1761162680
Short name T858
Test name
Test status
Simulation time 4781959808 ps
CPU time 13.39 seconds
Started Aug 08 05:44:44 PM PDT 24
Finished Aug 08 05:44:57 PM PDT 24
Peak memory 201532 kb
Host smart-4e9286a0-d9f0-41eb-9922-54d6cb824a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761162680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1761162680
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4281143832
Short name T857
Test name
Test status
Simulation time 353817031 ps
CPU time 1.23 seconds
Started Aug 08 05:44:44 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201516 kb
Host smart-4a062cb4-c5c0-4d7e-82e9-44bcebec19de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281143832 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4281143832
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3251792446
Short name T878
Test name
Test status
Simulation time 488340629 ps
CPU time 1.51 seconds
Started Aug 08 05:44:37 PM PDT 24
Finished Aug 08 05:44:39 PM PDT 24
Peak memory 201324 kb
Host smart-87cc9843-1f55-410e-8c12-8fafc11f2710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251792446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3251792446
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1506403002
Short name T815
Test name
Test status
Simulation time 482410325 ps
CPU time 1.73 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:38 PM PDT 24
Peak memory 201356 kb
Host smart-cb77049d-a976-475f-a278-c86cbb22d4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506403002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1506403002
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2424758859
Short name T859
Test name
Test status
Simulation time 4630526266 ps
CPU time 5.09 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201444 kb
Host smart-e9f781c4-e5a5-4c88-9af2-cffaa523ce1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424758859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2424758859
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3840649178
Short name T868
Test name
Test status
Simulation time 337238984 ps
CPU time 1.82 seconds
Started Aug 08 05:44:40 PM PDT 24
Finished Aug 08 05:44:42 PM PDT 24
Peak memory 201568 kb
Host smart-93765ad3-262b-4905-92fd-776281383d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840649178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3840649178
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1228987222
Short name T829
Test name
Test status
Simulation time 4418594141 ps
CPU time 3.6 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201524 kb
Host smart-163c42f3-2c36-4310-8f83-3e1b763e162f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228987222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1228987222
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2386985013
Short name T837
Test name
Test status
Simulation time 510550005 ps
CPU time 1.16 seconds
Started Aug 08 05:44:45 PM PDT 24
Finished Aug 08 05:44:46 PM PDT 24
Peak memory 201412 kb
Host smart-ca8459f6-a77b-44bb-a91e-e8c936ecfeae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386985013 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2386985013
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.310752775
Short name T898
Test name
Test status
Simulation time 546073276 ps
CPU time 1.12 seconds
Started Aug 08 05:44:40 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201356 kb
Host smart-b2a1aa84-40fc-4e1b-b59a-f93578029c0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310752775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.310752775
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1412489945
Short name T893
Test name
Test status
Simulation time 501776937 ps
CPU time 1.85 seconds
Started Aug 08 05:44:39 PM PDT 24
Finished Aug 08 05:44:41 PM PDT 24
Peak memory 201380 kb
Host smart-fb42748a-e4f8-4251-bca9-291ca93f8a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412489945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1412489945
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3430886391
Short name T140
Test name
Test status
Simulation time 2118240878 ps
CPU time 2.2 seconds
Started Aug 08 05:44:42 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 201264 kb
Host smart-36461da5-4245-47e1-ae2c-b6021a894d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430886391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3430886391
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2542590513
Short name T90
Test name
Test status
Simulation time 556539195 ps
CPU time 2.21 seconds
Started Aug 08 05:44:43 PM PDT 24
Finished Aug 08 05:44:45 PM PDT 24
Peak memory 217672 kb
Host smart-c0e9557d-cb54-47a1-add4-8dc219e60f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542590513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2542590513
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2072819092
Short name T903
Test name
Test status
Simulation time 8157575626 ps
CPU time 7.33 seconds
Started Aug 08 05:44:36 PM PDT 24
Finished Aug 08 05:44:44 PM PDT 24
Peak memory 201376 kb
Host smart-e4e47fea-8348-40f2-80c1-fc0ac96eeedb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072819092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2072819092
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.911729120
Short name T412
Test name
Test status
Simulation time 329466474 ps
CPU time 0.84 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:45:25 PM PDT 24
Peak memory 201280 kb
Host smart-682446ed-912b-4638-8b5a-154acf26273f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911729120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.911729120
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.771936405
Short name T299
Test name
Test status
Simulation time 350343285552 ps
CPU time 384.45 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:51:49 PM PDT 24
Peak memory 201392 kb
Host smart-b93bfaf8-fddb-4caf-b956-c6e02a41f915
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771936405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.771936405
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1019453409
Short name T164
Test name
Test status
Simulation time 162211994752 ps
CPU time 93.84 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:47:07 PM PDT 24
Peak memory 201464 kb
Host smart-2b624f53-f217-441d-84e8-e04b03ea85d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019453409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1019453409
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3139353614
Short name T571
Test name
Test status
Simulation time 159475376518 ps
CPU time 179.33 seconds
Started Aug 08 05:45:25 PM PDT 24
Finished Aug 08 05:48:24 PM PDT 24
Peak memory 201384 kb
Host smart-cb7607c9-3083-4e7c-8fb1-e03152f51ee7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139353614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3139353614
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.731759108
Short name T162
Test name
Test status
Simulation time 490125607294 ps
CPU time 591.09 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:55:21 PM PDT 24
Peak memory 201280 kb
Host smart-b03da69b-a516-4e42-9a78-e46bdd9dd959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731759108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.731759108
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4228666876
Short name T433
Test name
Test status
Simulation time 165884642414 ps
CPU time 235.15 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:49:19 PM PDT 24
Peak memory 201464 kb
Host smart-9faad3c4-b963-48de-ae50-12dce3b88730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228666876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4228666876
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3178080493
Short name T609
Test name
Test status
Simulation time 602029098206 ps
CPU time 337.08 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:51:15 PM PDT 24
Peak memory 201512 kb
Host smart-8cb7d7c3-11fa-4720-9371-7834cf17b41c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178080493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3178080493
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4206654312
Short name T754
Test name
Test status
Simulation time 100866738009 ps
CPU time 424.61 seconds
Started Aug 08 05:45:22 PM PDT 24
Finished Aug 08 05:52:27 PM PDT 24
Peak memory 201760 kb
Host smart-a58aa719-43f7-4651-b35a-7e2b87e1dcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206654312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4206654312
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3219448523
Short name T522
Test name
Test status
Simulation time 23652658813 ps
CPU time 13.47 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:45:39 PM PDT 24
Peak memory 201364 kb
Host smart-e3da9b7a-7723-4fbf-9688-dd185fea0a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219448523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3219448523
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1674344636
Short name T457
Test name
Test status
Simulation time 4238009241 ps
CPU time 10.03 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:45:34 PM PDT 24
Peak memory 201372 kb
Host smart-49a9156a-a73d-425e-a423-599659af9b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674344636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1674344636
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.901774990
Short name T366
Test name
Test status
Simulation time 5958240068 ps
CPU time 4.41 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:45:42 PM PDT 24
Peak memory 201292 kb
Host smart-69b2e83b-0599-43b9-85cd-ccdd95423d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901774990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.901774990
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4151643911
Short name T214
Test name
Test status
Simulation time 274144982021 ps
CPU time 415.74 seconds
Started Aug 08 05:45:31 PM PDT 24
Finished Aug 08 05:52:27 PM PDT 24
Peak memory 210048 kb
Host smart-7193a4e0-2f87-4666-b245-da3835b40add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151643911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4151643911
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.149930186
Short name T19
Test name
Test status
Simulation time 215067816475 ps
CPU time 70.17 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:46:43 PM PDT 24
Peak memory 201420 kb
Host smart-c81a3dcc-2aa1-4f68-81bf-dc29a5a5d0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149930186 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.149930186
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2079107194
Short name T465
Test name
Test status
Simulation time 471573111 ps
CPU time 1.07 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:45:41 PM PDT 24
Peak memory 201196 kb
Host smart-109684db-f837-4191-aac0-6cd63b384863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079107194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2079107194
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2244435836
Short name T555
Test name
Test status
Simulation time 195599493196 ps
CPU time 411.3 seconds
Started Aug 08 05:45:23 PM PDT 24
Finished Aug 08 05:52:14 PM PDT 24
Peak memory 201716 kb
Host smart-531256e4-e9af-4249-b3b6-328a46f78a78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244435836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2244435836
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3142573072
Short name T729
Test name
Test status
Simulation time 164084290267 ps
CPU time 353.79 seconds
Started Aug 08 05:45:28 PM PDT 24
Finished Aug 08 05:51:22 PM PDT 24
Peak memory 201532 kb
Host smart-3d045c5a-cec3-40a3-a486-f792fc744c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142573072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3142573072
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1335587493
Short name T450
Test name
Test status
Simulation time 331282570695 ps
CPU time 204.19 seconds
Started Aug 08 05:45:32 PM PDT 24
Finished Aug 08 05:48:56 PM PDT 24
Peak memory 201464 kb
Host smart-e1b27a8d-d7aa-4c03-a420-2e248363576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335587493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1335587493
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2472703858
Short name T668
Test name
Test status
Simulation time 326416191565 ps
CPU time 704.29 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:57:11 PM PDT 24
Peak memory 201524 kb
Host smart-89ef97b5-fa68-42f6-8fd8-b51f5ec810b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472703858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2472703858
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2614785383
Short name T721
Test name
Test status
Simulation time 488776776270 ps
CPU time 302.6 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:50:29 PM PDT 24
Peak memory 201448 kb
Host smart-7ac63778-fe57-4210-8e2a-eab4c475289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614785383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2614785383
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1594480808
Short name T658
Test name
Test status
Simulation time 330103448239 ps
CPU time 764.44 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:58:11 PM PDT 24
Peak memory 201436 kb
Host smart-abfc7e20-61fc-4561-b7ff-ff5774db86cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594480808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1594480808
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2731114654
Short name T756
Test name
Test status
Simulation time 178794741417 ps
CPU time 105.69 seconds
Started Aug 08 05:45:32 PM PDT 24
Finished Aug 08 05:47:18 PM PDT 24
Peak memory 201436 kb
Host smart-6dcc0a29-aca3-4b19-8dc2-ec8b4a4d2caf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731114654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2731114654
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2057134017
Short name T641
Test name
Test status
Simulation time 393340917473 ps
CPU time 901.39 seconds
Started Aug 08 05:45:23 PM PDT 24
Finished Aug 08 06:00:25 PM PDT 24
Peak memory 201444 kb
Host smart-ae2f121c-2101-48f2-8269-c5a85eacc2a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057134017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2057134017
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2844669416
Short name T593
Test name
Test status
Simulation time 68092899536 ps
CPU time 222.75 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:49:13 PM PDT 24
Peak memory 201904 kb
Host smart-46b43148-08d1-4cab-9e0a-2c544d95eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844669416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2844669416
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4140657253
Short name T438
Test name
Test status
Simulation time 34402220499 ps
CPU time 78.28 seconds
Started Aug 08 05:45:39 PM PDT 24
Finished Aug 08 05:46:57 PM PDT 24
Peak memory 201288 kb
Host smart-36a1dd61-805a-4a72-8060-db54e2661f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140657253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4140657253
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1966948065
Short name T471
Test name
Test status
Simulation time 5064246279 ps
CPU time 4.85 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:45:38 PM PDT 24
Peak memory 201260 kb
Host smart-e5ff1549-28f4-4a3b-a3bf-caa7f83ea2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966948065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1966948065
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1699925782
Short name T103
Test name
Test status
Simulation time 8055564666 ps
CPU time 3.08 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:45:33 PM PDT 24
Peak memory 218316 kb
Host smart-656640f0-e82d-453a-a160-d219f71b1456
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699925782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1699925782
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.107652096
Short name T767
Test name
Test status
Simulation time 6018662756 ps
CPU time 4.07 seconds
Started Aug 08 05:45:23 PM PDT 24
Finished Aug 08 05:45:27 PM PDT 24
Peak memory 201360 kb
Host smart-93f2c0b8-5b76-46f2-b31a-d98ac82169b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107652096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.107652096
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2840433742
Short name T421
Test name
Test status
Simulation time 9578661798 ps
CPU time 10.62 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:45:45 PM PDT 24
Peak memory 201336 kb
Host smart-8d83f584-59a8-4b09-a921-e6afa98cd89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840433742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2840433742
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3381383508
Short name T114
Test name
Test status
Simulation time 25387906006 ps
CPU time 52.76 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:46:23 PM PDT 24
Peak memory 209764 kb
Host smart-031e07ad-d07e-4eb1-a096-e4b8faec7464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381383508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3381383508
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4154976525
Short name T243
Test name
Test status
Simulation time 171994683421 ps
CPU time 310.43 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:51:06 PM PDT 24
Peak memory 201352 kb
Host smart-8d7bfacf-7212-4b81-b3d7-7e66a6712e71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154976525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4154976525
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1734685279
Short name T533
Test name
Test status
Simulation time 167274914173 ps
CPU time 380.99 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:52:05 PM PDT 24
Peak memory 201480 kb
Host smart-5dbbd6d6-f6e0-4a9b-a8e9-d02f2113787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734685279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1734685279
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3487636982
Short name T614
Test name
Test status
Simulation time 325515328861 ps
CPU time 462.51 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:53:33 PM PDT 24
Peak memory 201504 kb
Host smart-b5dbb74a-13f9-4134-b440-620905281d68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487636982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3487636982
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2100946860
Short name T458
Test name
Test status
Simulation time 328671456757 ps
CPU time 771.11 seconds
Started Aug 08 05:45:47 PM PDT 24
Finished Aug 08 05:58:38 PM PDT 24
Peak memory 201476 kb
Host smart-3bd18da6-2b26-4d9d-8b2b-cd9ce2176e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100946860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2100946860
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1385060954
Short name T770
Test name
Test status
Simulation time 166597706136 ps
CPU time 95.41 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:47:26 PM PDT 24
Peak memory 201396 kb
Host smart-ed2cd90b-c207-43a3-a72e-e002f9d439f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385060954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1385060954
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.379532050
Short name T580
Test name
Test status
Simulation time 205583041665 ps
CPU time 104.81 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:47:34 PM PDT 24
Peak memory 201424 kb
Host smart-63592dd0-34b5-42a0-9914-614b3acd7b35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379532050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.379532050
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2324710746
Short name T590
Test name
Test status
Simulation time 121592047163 ps
CPU time 409.26 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:52:44 PM PDT 24
Peak memory 201760 kb
Host smart-5c66e027-decd-4218-a359-c0e17b2eb9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324710746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2324710746
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1053799476
Short name T448
Test name
Test status
Simulation time 30703543468 ps
CPU time 19.78 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:46:08 PM PDT 24
Peak memory 201392 kb
Host smart-195eaba7-2c6c-4d72-adc0-9d1c3ccbf333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053799476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1053799476
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3456052285
Short name T186
Test name
Test status
Simulation time 3303178299 ps
CPU time 2.67 seconds
Started Aug 08 05:45:46 PM PDT 24
Finished Aug 08 05:45:49 PM PDT 24
Peak memory 201384 kb
Host smart-0b3c3258-2a58-46f3-9173-d213ca1e1c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456052285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3456052285
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3738949524
Short name T454
Test name
Test status
Simulation time 6055651087 ps
CPU time 13.56 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:46:06 PM PDT 24
Peak memory 201332 kb
Host smart-840a7333-7644-4377-be4b-96ebad070297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738949524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3738949524
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3770042449
Short name T325
Test name
Test status
Simulation time 192668686869 ps
CPU time 421.28 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:52:59 PM PDT 24
Peak memory 201524 kb
Host smart-e9392522-4a0c-4551-b065-95d549451e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770042449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3770042449
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.89456673
Short name T116
Test name
Test status
Simulation time 71214735570 ps
CPU time 126.73 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:47:59 PM PDT 24
Peak memory 210148 kb
Host smart-f71ce47a-753f-4147-ad81-2586569db3a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89456673 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.89456673
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3348776650
Short name T392
Test name
Test status
Simulation time 416043113 ps
CPU time 0.88 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:45:53 PM PDT 24
Peak memory 201232 kb
Host smart-aa4e89fd-3dfc-4d58-911d-3d431f8bbc60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348776650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3348776650
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1306497543
Short name T276
Test name
Test status
Simulation time 382119239071 ps
CPU time 203.35 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:49:16 PM PDT 24
Peak memory 201344 kb
Host smart-8ed22571-6ed0-489d-8fe5-b4bf4d278a9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306497543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1306497543
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2338323187
Short name T686
Test name
Test status
Simulation time 162142073717 ps
CPU time 100.98 seconds
Started Aug 08 05:45:46 PM PDT 24
Finished Aug 08 05:47:27 PM PDT 24
Peak memory 201464 kb
Host smart-5a1d2e65-b01a-430b-ac33-a6ee8ebbfefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338323187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2338323187
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4169458574
Short name T523
Test name
Test status
Simulation time 327378880225 ps
CPU time 699.98 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:57:28 PM PDT 24
Peak memory 201536 kb
Host smart-f7b3e917-f534-42a8-b63d-ed6448babf7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169458574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4169458574
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.77131520
Short name T657
Test name
Test status
Simulation time 481658262619 ps
CPU time 921.37 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 06:01:13 PM PDT 24
Peak memory 201456 kb
Host smart-0dd015dd-3800-41a8-8896-1e70a655e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77131520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.77131520
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3070786500
Short name T167
Test name
Test status
Simulation time 164640759436 ps
CPU time 91.71 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:47:26 PM PDT 24
Peak memory 201448 kb
Host smart-1a74e823-de82-465d-8a98-104569d082c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070786500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3070786500
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2813402887
Short name T717
Test name
Test status
Simulation time 409573347216 ps
CPU time 269.62 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:50:20 PM PDT 24
Peak memory 201392 kb
Host smart-c711e9c3-83f0-454c-a943-3f4ee6421280
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813402887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2813402887
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2961671408
Short name T727
Test name
Test status
Simulation time 100183879559 ps
CPU time 342.27 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:51:36 PM PDT 24
Peak memory 201808 kb
Host smart-f02dad33-ad55-4ee8-9aab-fe796b2b73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961671408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2961671408
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.238076431
Short name T619
Test name
Test status
Simulation time 38286484869 ps
CPU time 81.16 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:47:16 PM PDT 24
Peak memory 201396 kb
Host smart-b7d04bff-ec4e-469d-93ad-e272cd837920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238076431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.238076431
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.141362925
Short name T362
Test name
Test status
Simulation time 4845479297 ps
CPU time 6.68 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:46:01 PM PDT 24
Peak memory 201316 kb
Host smart-65b3c7f5-06ff-4dec-8d6e-7cd498e9b073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141362925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.141362925
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2127258002
Short name T396
Test name
Test status
Simulation time 5940031329 ps
CPU time 7.62 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:45:57 PM PDT 24
Peak memory 201316 kb
Host smart-4db50090-d98b-439f-b05b-1bc81a321320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127258002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2127258002
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3896854261
Short name T793
Test name
Test status
Simulation time 309872662289 ps
CPU time 624.84 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:56:19 PM PDT 24
Peak memory 210216 kb
Host smart-1bf14c1f-f276-40a4-86fd-917866ed6fcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896854261 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3896854261
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.642142615
Short name T93
Test name
Test status
Simulation time 488137263 ps
CPU time 1.18 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:45:53 PM PDT 24
Peak memory 201176 kb
Host smart-9e27c1f7-49dc-42bc-8b18-c7e3eac99679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642142615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.642142615
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4252919156
Short name T643
Test name
Test status
Simulation time 161597993103 ps
CPU time 347.83 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:51:39 PM PDT 24
Peak memory 201472 kb
Host smart-e3d0b880-c226-4bf3-85a0-4e876ed6c976
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252919156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4252919156
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1389736532
Short name T322
Test name
Test status
Simulation time 480058311432 ps
CPU time 1115.32 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 201540 kb
Host smart-17fba19b-175a-4d1a-8f3b-0eebe4ac1c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389736532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1389736532
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3998781704
Short name T777
Test name
Test status
Simulation time 338452853624 ps
CPU time 210.24 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:49:20 PM PDT 24
Peak memory 201372 kb
Host smart-a0b2d987-fd5e-43a4-b779-03026c2077fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998781704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3998781704
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4025681291
Short name T422
Test name
Test status
Simulation time 333785898148 ps
CPU time 208.22 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:49:20 PM PDT 24
Peak memory 201420 kb
Host smart-962005fd-6720-4c64-a75a-269134633255
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025681291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4025681291
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.482103851
Short name T469
Test name
Test status
Simulation time 332922029897 ps
CPU time 428.25 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:53:03 PM PDT 24
Peak memory 201452 kb
Host smart-595eec2b-e0c7-4732-a613-3c1b1c17805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482103851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.482103851
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3243488714
Short name T505
Test name
Test status
Simulation time 487871472267 ps
CPU time 1132.35 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 201432 kb
Host smart-580d5708-7bed-411d-aeb4-38cb5286c3b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243488714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3243488714
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3627123872
Short name T269
Test name
Test status
Simulation time 346153080770 ps
CPU time 400.86 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:52:40 PM PDT 24
Peak memory 201472 kb
Host smart-d02491af-83f2-4a12-8a7a-e7b41c500af5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627123872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3627123872
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1749853724
Short name T791
Test name
Test status
Simulation time 198711000188 ps
CPU time 417.48 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:52:52 PM PDT 24
Peak memory 201392 kb
Host smart-45c89b11-1ff1-4bdd-8447-45a2e5f8101b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749853724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1749853724
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.346968737
Short name T509
Test name
Test status
Simulation time 37748947896 ps
CPU time 11.38 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:46:07 PM PDT 24
Peak memory 201400 kb
Host smart-6dd2a993-6603-4ab1-b180-a997aa45f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346968737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.346968737
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2457325326
Short name T534
Test name
Test status
Simulation time 3356605900 ps
CPU time 8.09 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:46:01 PM PDT 24
Peak memory 201372 kb
Host smart-02d6949a-b149-4297-97ae-cc7f97df7561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457325326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2457325326
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2024764075
Short name T689
Test name
Test status
Simulation time 5893565083 ps
CPU time 8.19 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:45:58 PM PDT 24
Peak memory 201332 kb
Host smart-0c5c16f5-6c4c-4ab7-8142-c79d377fae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024764075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2024764075
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1242313921
Short name T733
Test name
Test status
Simulation time 488473704810 ps
CPU time 299.33 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:50:55 PM PDT 24
Peak memory 201412 kb
Host smart-9ca42b09-27ca-4efc-98a6-ea6ff2aef901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242313921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1242313921
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4220464037
Short name T66
Test name
Test status
Simulation time 374126985 ps
CPU time 0.85 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:45:53 PM PDT 24
Peak memory 201272 kb
Host smart-fac9a888-b252-466d-9cf1-d39227e6ef88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220464037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4220464037
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1019264535
Short name T1
Test name
Test status
Simulation time 383646816269 ps
CPU time 160.63 seconds
Started Aug 08 05:45:56 PM PDT 24
Finished Aug 08 05:48:37 PM PDT 24
Peak memory 201444 kb
Host smart-0b05c06f-b076-4bc6-aefb-6859207ae805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019264535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1019264535
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2171226776
Short name T190
Test name
Test status
Simulation time 332094884069 ps
CPU time 79.73 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:47:12 PM PDT 24
Peak memory 201440 kb
Host smart-ff469c16-2f07-420b-a605-4fab18b7a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171226776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2171226776
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1664902203
Short name T520
Test name
Test status
Simulation time 331950422162 ps
CPU time 208.06 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:49:16 PM PDT 24
Peak memory 201496 kb
Host smart-ee021a46-1b14-49df-9efe-ae40fb4468d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664902203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1664902203
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.571270724
Short name T115
Test name
Test status
Simulation time 482050396217 ps
CPU time 568.69 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:55:19 PM PDT 24
Peak memory 201516 kb
Host smart-24be4023-39af-48c2-be4f-f10598e7d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571270724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.571270724
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3062415475
Short name T526
Test name
Test status
Simulation time 490709694260 ps
CPU time 1183.33 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 06:05:35 PM PDT 24
Peak memory 201452 kb
Host smart-dd9f34a9-e560-4885-b59b-3e6ba7f08461
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062415475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3062415475
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4028551986
Short name T309
Test name
Test status
Simulation time 162766171326 ps
CPU time 137.22 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:48:06 PM PDT 24
Peak memory 201368 kb
Host smart-9e51de79-a28b-44a7-b9ec-01c5bcd7ea10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028551986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4028551986
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1549865522
Short name T369
Test name
Test status
Simulation time 191814001184 ps
CPU time 439.32 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:53:08 PM PDT 24
Peak memory 201496 kb
Host smart-96170b09-e1e9-4c6d-8495-fb5630ec5da0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549865522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1549865522
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1339470029
Short name T639
Test name
Test status
Simulation time 107914111152 ps
CPU time 554.25 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:55:08 PM PDT 24
Peak memory 201592 kb
Host smart-49e7d59d-7a55-4125-a727-453484865b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339470029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1339470029
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3136583714
Short name T531
Test name
Test status
Simulation time 39807154910 ps
CPU time 90.56 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:47:26 PM PDT 24
Peak memory 201392 kb
Host smart-ed8d0433-f08a-4ee9-a548-37c2877a3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136583714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3136583714
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1264596802
Short name T467
Test name
Test status
Simulation time 3588434005 ps
CPU time 8.44 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:45:58 PM PDT 24
Peak memory 201372 kb
Host smart-5fdbe475-880f-479b-9b4d-6e8a38a0c4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264596802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1264596802
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3029127043
Short name T695
Test name
Test status
Simulation time 5904118669 ps
CPU time 7.87 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:45:58 PM PDT 24
Peak memory 201340 kb
Host smart-92bd6abe-8c0c-4bdf-84e4-d029291b362f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029127043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3029127043
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1251799079
Short name T730
Test name
Test status
Simulation time 199255356606 ps
CPU time 133.1 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:48:04 PM PDT 24
Peak memory 216484 kb
Host smart-48d74f83-d440-4cec-ac8f-a75b4ead9c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251799079 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1251799079
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3847750488
Short name T537
Test name
Test status
Simulation time 385945889 ps
CPU time 1.43 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 05:46:00 PM PDT 24
Peak memory 201240 kb
Host smart-15e57c91-5c3d-452c-a30a-a2b9df1ce24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847750488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3847750488
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2136034600
Short name T687
Test name
Test status
Simulation time 188378889818 ps
CPU time 105.3 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:47:50 PM PDT 24
Peak memory 201500 kb
Host smart-59fb15c9-b8f9-442b-ab93-b348233f3fa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136034600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2136034600
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.36164614
Short name T512
Test name
Test status
Simulation time 189597394438 ps
CPU time 120.5 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:47:59 PM PDT 24
Peak memory 201508 kb
Host smart-2c09d113-e994-448e-85d7-84d3a483bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36164614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.36164614
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3510588866
Short name T188
Test name
Test status
Simulation time 167903974793 ps
CPU time 101.63 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:47:39 PM PDT 24
Peak memory 201536 kb
Host smart-7c8657e9-717a-47e8-a538-8a9986b8b2a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510588866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3510588866
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2195116117
Short name T430
Test name
Test status
Simulation time 163362368619 ps
CPU time 392.56 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:52:25 PM PDT 24
Peak memory 201464 kb
Host smart-c5dec35e-d939-4ca6-ae7b-c8da60775540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195116117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2195116117
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2026403468
Short name T774
Test name
Test status
Simulation time 328721599192 ps
CPU time 187.97 seconds
Started Aug 08 05:45:56 PM PDT 24
Finished Aug 08 05:49:04 PM PDT 24
Peak memory 201456 kb
Host smart-8b1383f3-aed3-4e71-a2a0-9736b3cc4dcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026403468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2026403468
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.123059593
Short name T61
Test name
Test status
Simulation time 378756638468 ps
CPU time 448.81 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:53:39 PM PDT 24
Peak memory 201376 kb
Host smart-6d5a9294-180b-4242-9392-fad58ef11230
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123059593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.123059593
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.924174840
Short name T527
Test name
Test status
Simulation time 602914236243 ps
CPU time 1334.51 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 06:08:13 PM PDT 24
Peak memory 201696 kb
Host smart-da0ce732-ec13-4729-a835-842d86146a07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924174840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.924174840
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.766697118
Short name T208
Test name
Test status
Simulation time 103726622708 ps
CPU time 502.18 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:54:16 PM PDT 24
Peak memory 201760 kb
Host smart-db1f2e7f-8013-4de4-81f4-68e0cadf23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766697118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.766697118
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2873952344
Short name T378
Test name
Test status
Simulation time 42513224801 ps
CPU time 74.64 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:47:14 PM PDT 24
Peak memory 201360 kb
Host smart-d802772e-ae30-49a9-b7bb-b6e37759f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873952344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2873952344
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1170511155
Short name T381
Test name
Test status
Simulation time 3284954497 ps
CPU time 5.75 seconds
Started Aug 08 05:45:54 PM PDT 24
Finished Aug 08 05:46:00 PM PDT 24
Peak memory 201312 kb
Host smart-3798dff7-0e91-4494-9878-84c687d563b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170511155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1170511155
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4222532808
Short name T784
Test name
Test status
Simulation time 5777660411 ps
CPU time 14.76 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:46:14 PM PDT 24
Peak memory 201380 kb
Host smart-d64106be-7a5e-45e8-b795-cca7ab24fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222532808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4222532808
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1208145495
Short name T766
Test name
Test status
Simulation time 136874907740 ps
CPU time 650.82 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:56:44 PM PDT 24
Peak memory 210932 kb
Host smart-a7790645-b780-402e-b084-45d960e9753b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208145495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1208145495
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3179806994
Short name T762
Test name
Test status
Simulation time 278000856348 ps
CPU time 88.33 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:47:38 PM PDT 24
Peak memory 210076 kb
Host smart-4daf43a4-02de-4169-91e1-5d1824a18d9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179806994 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3179806994
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1525907475
Short name T610
Test name
Test status
Simulation time 374258586 ps
CPU time 1.11 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:45:58 PM PDT 24
Peak memory 201208 kb
Host smart-d75d830e-6a84-4991-8599-dc12b72d8d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525907475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1525907475
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.384702473
Short name T726
Test name
Test status
Simulation time 504433489620 ps
CPU time 516.33 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:54:47 PM PDT 24
Peak memory 201308 kb
Host smart-1b6564dd-5ce2-477f-a72e-099a0e6a5633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384702473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.384702473
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.471143636
Short name T233
Test name
Test status
Simulation time 162291978393 ps
CPU time 198.16 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 05:49:16 PM PDT 24
Peak memory 201428 kb
Host smart-c70b379c-a438-4b0b-894a-0bab700396c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471143636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.471143636
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3450839810
Short name T611
Test name
Test status
Simulation time 499150467468 ps
CPU time 228.55 seconds
Started Aug 08 05:46:00 PM PDT 24
Finished Aug 08 05:49:49 PM PDT 24
Peak memory 201476 kb
Host smart-cdf47838-c36d-4052-9805-4b020ee2e51c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450839810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3450839810
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1409308873
Short name T293
Test name
Test status
Simulation time 494258929239 ps
CPU time 1030.74 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 06:03:03 PM PDT 24
Peak memory 201440 kb
Host smart-fe3d753b-fa62-4339-8192-cbedfba7ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409308873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1409308873
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.760445184
Short name T13
Test name
Test status
Simulation time 476041299548 ps
CPU time 297.94 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:50:57 PM PDT 24
Peak memory 201456 kb
Host smart-923cc132-dab8-415d-899b-ebd5233c0c65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760445184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.760445184
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.651681227
Short name T365
Test name
Test status
Simulation time 206676122631 ps
CPU time 507.93 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:54:25 PM PDT 24
Peak memory 201500 kb
Host smart-23fa84f0-e21f-4af5-87f0-a34581f54b3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651681227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.651681227
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3133753635
Short name T210
Test name
Test status
Simulation time 77145923844 ps
CPU time 278.4 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:50:36 PM PDT 24
Peak memory 201800 kb
Host smart-9287b80d-90d6-438e-bf0f-fcb04a060f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133753635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3133753635
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2611858655
Short name T477
Test name
Test status
Simulation time 39456657419 ps
CPU time 81.87 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:47:15 PM PDT 24
Peak memory 201388 kb
Host smart-29ab4720-f48e-4bf1-96ef-c8c72b6207a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611858655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2611858655
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.340677717
Short name T360
Test name
Test status
Simulation time 4384128113 ps
CPU time 3.28 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:46:01 PM PDT 24
Peak memory 201352 kb
Host smart-97458f52-3ecd-4f4d-a139-45934462c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340677717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.340677717
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3684257223
Short name T735
Test name
Test status
Simulation time 5719067826 ps
CPU time 12.94 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 05:46:11 PM PDT 24
Peak memory 201332 kb
Host smart-4d374a70-64b5-485b-bec2-b0696529c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684257223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3684257223
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2811605902
Short name T227
Test name
Test status
Simulation time 307916666459 ps
CPU time 673.74 seconds
Started Aug 08 05:45:59 PM PDT 24
Finished Aug 08 05:57:13 PM PDT 24
Peak memory 201440 kb
Host smart-1c6b3ffc-4c17-4730-b785-cd36a5e0bc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811605902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2811605902
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1418155613
Short name T757
Test name
Test status
Simulation time 2694578340 ps
CPU time 6.72 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:46:18 PM PDT 24
Peak memory 201464 kb
Host smart-78a95f22-4e86-4854-a912-3c5d1d32c1d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418155613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1418155613
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3260755567
Short name T478
Test name
Test status
Simulation time 369377913 ps
CPU time 0.69 seconds
Started Aug 08 05:46:01 PM PDT 24
Finished Aug 08 05:46:01 PM PDT 24
Peak memory 201164 kb
Host smart-43bf6175-da8c-450c-a0b5-5df128ad37a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260755567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3260755567
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1803286985
Short name T117
Test name
Test status
Simulation time 165056170941 ps
CPU time 382.59 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:52:33 PM PDT 24
Peak memory 201360 kb
Host smart-32ec1d5c-d8f2-4500-a2cb-9c10378a8588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803286985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1803286985
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3089443258
Short name T485
Test name
Test status
Simulation time 161063860810 ps
CPU time 202.61 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:49:19 PM PDT 24
Peak memory 201484 kb
Host smart-624e64b2-898a-4f91-ba0e-77bc9b1162f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089443258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3089443258
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3937587608
Short name T251
Test name
Test status
Simulation time 324658164803 ps
CPU time 694.58 seconds
Started Aug 08 05:46:07 PM PDT 24
Finished Aug 08 05:57:42 PM PDT 24
Peak memory 201304 kb
Host smart-97d7bbdc-0d53-4381-a1b4-da588dc66d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937587608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3937587608
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3453118282
Short name T384
Test name
Test status
Simulation time 491243203769 ps
CPU time 350.15 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:52:01 PM PDT 24
Peak memory 201300 kb
Host smart-9dc6c772-bcfc-4ea8-a266-96320023c28b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453118282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3453118282
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.904026611
Short name T182
Test name
Test status
Simulation time 377147873522 ps
CPU time 130.03 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:48:05 PM PDT 24
Peak memory 201468 kb
Host smart-20706bae-5aab-40ee-bb79-e79fd098f175
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904026611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.904026611
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3135833667
Short name T638
Test name
Test status
Simulation time 591803638288 ps
CPU time 712.71 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:57:50 PM PDT 24
Peak memory 201448 kb
Host smart-dec4a24d-e5ad-4624-b7e9-a03258148176
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135833667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3135833667
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.103287944
Short name T747
Test name
Test status
Simulation time 105781253632 ps
CPU time 322.79 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:51:33 PM PDT 24
Peak memory 201680 kb
Host smart-50d27230-54b6-4a40-aee9-35fae791442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103287944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.103287944
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2634817187
Short name T470
Test name
Test status
Simulation time 30552887113 ps
CPU time 36.71 seconds
Started Aug 08 05:45:53 PM PDT 24
Finished Aug 08 05:46:30 PM PDT 24
Peak memory 201336 kb
Host smart-088e1fd4-4ff8-4f86-9e5d-163ff8d0db18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634817187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2634817187
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2300590428
Short name T8
Test name
Test status
Simulation time 3062277861 ps
CPU time 2.37 seconds
Started Aug 08 05:45:56 PM PDT 24
Finished Aug 08 05:45:58 PM PDT 24
Peak memory 201356 kb
Host smart-986213e9-2b33-4504-bc96-c00474a86e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300590428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2300590428
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3335310796
Short name T709
Test name
Test status
Simulation time 6125430514 ps
CPU time 1.56 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:45:53 PM PDT 24
Peak memory 201340 kb
Host smart-cc6b8652-3f18-4240-884d-35033c18fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335310796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3335310796
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1637525123
Short name T35
Test name
Test status
Simulation time 168509108885 ps
CPU time 396.37 seconds
Started Aug 08 05:45:58 PM PDT 24
Finished Aug 08 05:52:35 PM PDT 24
Peak memory 201432 kb
Host smart-f28e45b5-aae3-4d96-b2a3-d908b8802be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637525123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1637525123
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.51912580
Short name T732
Test name
Test status
Simulation time 290107349 ps
CPU time 1.31 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:46:12 PM PDT 24
Peak memory 201260 kb
Host smart-a0a6d007-26f6-4458-999b-21d74b08f55b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51912580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.51912580
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3581514697
Short name T599
Test name
Test status
Simulation time 333752223795 ps
CPU time 394.96 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 05:52:45 PM PDT 24
Peak memory 201464 kb
Host smart-5763d8e5-bd31-4594-b97f-99a8f3ac565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581514697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3581514697
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2986670850
Short name T546
Test name
Test status
Simulation time 492503871716 ps
CPU time 330.23 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:51:36 PM PDT 24
Peak memory 201476 kb
Host smart-e9fb9031-8ee3-4cef-a4ed-d497028a2568
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986670850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2986670850
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4095855064
Short name T481
Test name
Test status
Simulation time 486253740345 ps
CPU time 197.68 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:49:28 PM PDT 24
Peak memory 201376 kb
Host smart-e6900940-627c-423e-b188-093c3b229323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095855064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4095855064
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3274711196
Short name T376
Test name
Test status
Simulation time 161514941598 ps
CPU time 199.46 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:49:26 PM PDT 24
Peak memory 201416 kb
Host smart-65ce7a17-cd00-4a41-994d-a18f10724903
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274711196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3274711196
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3353299452
Short name T184
Test name
Test status
Simulation time 412261428697 ps
CPU time 871.89 seconds
Started Aug 08 05:46:07 PM PDT 24
Finished Aug 08 06:00:39 PM PDT 24
Peak memory 201456 kb
Host smart-09eaa945-ba07-4842-afe9-108f71c4aed2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353299452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3353299452
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3034356787
Short name T6
Test name
Test status
Simulation time 28508838329 ps
CPU time 18.35 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:46:22 PM PDT 24
Peak memory 201396 kb
Host smart-67c4e79d-469a-4a85-b2b5-48b0dceade3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034356787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3034356787
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1423077924
Short name T121
Test name
Test status
Simulation time 3884570814 ps
CPU time 9.55 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:46:13 PM PDT 24
Peak memory 201324 kb
Host smart-c351f115-72d8-42e7-b517-02133c4af2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423077924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1423077924
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1281436239
Short name T781
Test name
Test status
Simulation time 5793798650 ps
CPU time 4.25 seconds
Started Aug 08 05:46:01 PM PDT 24
Finished Aug 08 05:46:05 PM PDT 24
Peak memory 201404 kb
Host smart-40f16b5b-b055-4d77-9ce0-f514b6507df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281436239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1281436239
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2974470356
Short name T623
Test name
Test status
Simulation time 266052424678 ps
CPU time 326.21 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:51:32 PM PDT 24
Peak memory 216120 kb
Host smart-09af4cae-6a77-4299-96ba-c0c74f7defa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974470356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2974470356
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.30343927
Short name T449
Test name
Test status
Simulation time 445707389 ps
CPU time 0.84 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:46:11 PM PDT 24
Peak memory 201164 kb
Host smart-68c4e8d7-45d6-4fe0-895b-2aeb4a1b1d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.30343927
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2517336273
Short name T314
Test name
Test status
Simulation time 161465555423 ps
CPU time 339.42 seconds
Started Aug 08 05:46:12 PM PDT 24
Finished Aug 08 05:51:52 PM PDT 24
Peak memory 201520 kb
Host smart-47e1b9b7-cedb-4109-a903-24903dfed76f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517336273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2517336273
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1541846116
Short name T542
Test name
Test status
Simulation time 171097929354 ps
CPU time 372 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 05:52:21 PM PDT 24
Peak memory 201484 kb
Host smart-3f76935c-f371-4ced-82c3-a35df82aabee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541846116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1541846116
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2500799217
Short name T267
Test name
Test status
Simulation time 333812470531 ps
CPU time 634.52 seconds
Started Aug 08 05:46:02 PM PDT 24
Finished Aug 08 05:56:37 PM PDT 24
Peak memory 201396 kb
Host smart-f0e2c916-00b5-49aa-840e-22f229d8e526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500799217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2500799217
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1289442646
Short name T524
Test name
Test status
Simulation time 331260927430 ps
CPU time 203.28 seconds
Started Aug 08 05:46:05 PM PDT 24
Finished Aug 08 05:49:29 PM PDT 24
Peak memory 201428 kb
Host smart-fd78bae8-bdc0-4479-afbf-186a9aa92e8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289442646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1289442646
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.61892619
Short name T585
Test name
Test status
Simulation time 161901418163 ps
CPU time 379.7 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:52:24 PM PDT 24
Peak memory 201568 kb
Host smart-4be5f298-52f7-4f32-8bc2-9999ec52b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61892619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.61892619
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4283675935
Short name T370
Test name
Test status
Simulation time 168870865669 ps
CPU time 395.17 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:52:38 PM PDT 24
Peak memory 201456 kb
Host smart-67522898-431e-45df-92c9-380a13326313
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283675935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.4283675935
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3065996969
Short name T602
Test name
Test status
Simulation time 227308289802 ps
CPU time 258.1 seconds
Started Aug 08 05:46:08 PM PDT 24
Finished Aug 08 05:50:26 PM PDT 24
Peak memory 201416 kb
Host smart-aca643c9-38fe-45a1-ba5c-1f734cdfe9b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065996969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3065996969
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2992546468
Short name T409
Test name
Test status
Simulation time 405670028622 ps
CPU time 231.87 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:49:55 PM PDT 24
Peak memory 201348 kb
Host smart-db652bc0-a774-4fa9-8c34-aa4234820527
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992546468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2992546468
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1227930235
Short name T720
Test name
Test status
Simulation time 46445237533 ps
CPU time 21.41 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:46:37 PM PDT 24
Peak memory 201396 kb
Host smart-1bf01844-b492-459a-84cd-29731459b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227930235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1227930235
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1510737144
Short name T753
Test name
Test status
Simulation time 5071056169 ps
CPU time 12.26 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:46:16 PM PDT 24
Peak memory 201280 kb
Host smart-39364fa5-5d0a-4511-8644-1f9e567b6501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510737144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1510737144
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.410322874
Short name T455
Test name
Test status
Simulation time 5831612522 ps
CPU time 4.16 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:46:10 PM PDT 24
Peak memory 201392 kb
Host smart-9bc99cd7-f798-4793-97c9-650fd6f66aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410322874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.410322874
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2026462658
Short name T262
Test name
Test status
Simulation time 185082618576 ps
CPU time 50 seconds
Started Aug 08 05:46:05 PM PDT 24
Finished Aug 08 05:46:55 PM PDT 24
Peak memory 201452 kb
Host smart-d5f4e63a-b46d-4a0e-96b3-3f4689f3dbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026462658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2026462658
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1724762251
Short name T123
Test name
Test status
Simulation time 51180476892 ps
CPU time 146.4 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 05:48:36 PM PDT 24
Peak memory 210112 kb
Host smart-c0411cfc-8211-4f09-8345-f52056df69c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724762251 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1724762251
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2253742380
Short name T196
Test name
Test status
Simulation time 525065212 ps
CPU time 0.92 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:46:04 PM PDT 24
Peak memory 201264 kb
Host smart-beaf9fa1-a7ec-4c56-bff6-2cb1359e1d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253742380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2253742380
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1211689684
Short name T740
Test name
Test status
Simulation time 330650528863 ps
CPU time 183.25 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:49:09 PM PDT 24
Peak memory 201480 kb
Host smart-d8810c1c-ac03-4408-a81d-6486efbde2c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211689684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1211689684
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.832839958
Short name T166
Test name
Test status
Simulation time 356945634544 ps
CPU time 239.05 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:50:05 PM PDT 24
Peak memory 201428 kb
Host smart-3038120f-21f8-491a-8d74-903641f13d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832839958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.832839958
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2514732615
Short name T492
Test name
Test status
Simulation time 158487091967 ps
CPU time 99.71 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:47:44 PM PDT 24
Peak memory 201480 kb
Host smart-3466f94e-3824-4ba2-8b03-30bcae968a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514732615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2514732615
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1414133639
Short name T456
Test name
Test status
Simulation time 323748384001 ps
CPU time 763.01 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:58:50 PM PDT 24
Peak memory 201460 kb
Host smart-bd21a88c-e5e5-45fa-9367-a7df40bf4c63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414133639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1414133639
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1907690213
Short name T303
Test name
Test status
Simulation time 490113188033 ps
CPU time 1184.5 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 06:05:58 PM PDT 24
Peak memory 201456 kb
Host smart-5a8e8c8a-be62-4bf9-a1f9-864154be1feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907690213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1907690213
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3512907686
Short name T495
Test name
Test status
Simulation time 158033044344 ps
CPU time 334.5 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:51:38 PM PDT 24
Peak memory 201412 kb
Host smart-6e3ebd7f-d163-4358-ad5a-f51508004292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512907686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3512907686
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3001604013
Short name T331
Test name
Test status
Simulation time 181246144115 ps
CPU time 215.55 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:49:42 PM PDT 24
Peak memory 201460 kb
Host smart-c60ffa45-59f5-41e4-b37c-f1d2ec1bd43d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001604013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3001604013
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3695627861
Short name T728
Test name
Test status
Simulation time 195547584618 ps
CPU time 442.98 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 05:53:32 PM PDT 24
Peak memory 201472 kb
Host smart-57b0df82-bbb6-44c7-8dad-5fea1d39e291
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695627861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3695627861
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1332842623
Short name T779
Test name
Test status
Simulation time 121163707846 ps
CPU time 638.44 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:56:50 PM PDT 24
Peak memory 201748 kb
Host smart-7ef813cd-259f-476c-9e54-a04dd4f1a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332842623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1332842623
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2311386768
Short name T459
Test name
Test status
Simulation time 37885581835 ps
CPU time 90.57 seconds
Started Aug 08 05:46:05 PM PDT 24
Finished Aug 08 05:47:35 PM PDT 24
Peak memory 201400 kb
Host smart-7266ed46-f54d-4000-9edc-f7745c097ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311386768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2311386768
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4102877455
Short name T413
Test name
Test status
Simulation time 3284385984 ps
CPU time 8 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:46:15 PM PDT 24
Peak memory 201332 kb
Host smart-260578ee-3244-4aa4-b8f3-20bc83fc201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102877455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4102877455
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2034431381
Short name T780
Test name
Test status
Simulation time 6126107432 ps
CPU time 15.6 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:46:26 PM PDT 24
Peak memory 201360 kb
Host smart-ff0cf454-6fc3-45fa-a353-1f62af2947c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034431381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2034431381
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3597947196
Short name T333
Test name
Test status
Simulation time 192909385418 ps
CPU time 118.41 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:48:09 PM PDT 24
Peak memory 201524 kb
Host smart-ac04b2d2-6e47-447e-a88d-2e9b0eb12732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597947196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3597947196
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.162849670
Short name T22
Test name
Test status
Simulation time 245452910231 ps
CPU time 142.18 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:48:25 PM PDT 24
Peak memory 209936 kb
Host smart-86ee7bfa-32bf-4ef4-9022-65f07d1352e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162849670 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.162849670
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.932702076
Short name T615
Test name
Test status
Simulation time 374914131 ps
CPU time 1.56 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:45:31 PM PDT 24
Peak memory 201064 kb
Host smart-0c4ce69d-65cb-4a5d-9552-a95c59aaef47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932702076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.932702076
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.485392157
Short name T330
Test name
Test status
Simulation time 368279266567 ps
CPU time 441.98 seconds
Started Aug 08 05:45:31 PM PDT 24
Finished Aug 08 05:52:53 PM PDT 24
Peak memory 201500 kb
Host smart-65aeaa7d-7838-4f54-9779-c5251ccb04ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485392157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.485392157
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1960537101
Short name T260
Test name
Test status
Simulation time 485590408837 ps
CPU time 272.03 seconds
Started Aug 08 05:45:25 PM PDT 24
Finished Aug 08 05:49:58 PM PDT 24
Peak memory 201432 kb
Host smart-112a02c5-5ec7-47a9-9668-843ac2d190bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960537101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1960537101
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1789308426
Short name T372
Test name
Test status
Simulation time 334909670948 ps
CPU time 194.65 seconds
Started Aug 08 05:45:28 PM PDT 24
Finished Aug 08 05:48:43 PM PDT 24
Peak memory 201532 kb
Host smart-8fc2fba1-d653-40ab-b072-66e4e089227e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789308426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1789308426
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.562703686
Short name T168
Test name
Test status
Simulation time 323682161858 ps
CPU time 306.82 seconds
Started Aug 08 05:45:25 PM PDT 24
Finished Aug 08 05:50:32 PM PDT 24
Peak memory 201548 kb
Host smart-8434d0f4-7032-464f-ba2b-532cb878abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562703686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.562703686
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.470633731
Short name T419
Test name
Test status
Simulation time 165402439135 ps
CPU time 94.73 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:46:59 PM PDT 24
Peak memory 201392 kb
Host smart-b849f8bd-2076-426b-9e64-44fc60d85e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470633731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.470633731
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2153188674
Short name T445
Test name
Test status
Simulation time 179178496187 ps
CPU time 362.73 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:51:27 PM PDT 24
Peak memory 201400 kb
Host smart-5374adad-4566-410b-b035-091c017e9493
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153188674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2153188674
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1809896485
Short name T682
Test name
Test status
Simulation time 417843642985 ps
CPU time 973.64 seconds
Started Aug 08 05:45:29 PM PDT 24
Finished Aug 08 06:01:43 PM PDT 24
Peak memory 201368 kb
Host smart-0e399378-9612-4735-ab6b-ccc19c46dbdb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809896485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1809896485
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2554304133
Short name T345
Test name
Test status
Simulation time 64244390906 ps
CPU time 253.64 seconds
Started Aug 08 05:45:23 PM PDT 24
Finished Aug 08 05:49:37 PM PDT 24
Peak memory 201720 kb
Host smart-34110800-2ddb-4bc1-b000-faca1e3ae44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554304133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2554304133
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1255838469
Short name T482
Test name
Test status
Simulation time 36193893930 ps
CPU time 91.09 seconds
Started Aug 08 05:45:25 PM PDT 24
Finished Aug 08 05:46:56 PM PDT 24
Peak memory 201396 kb
Host smart-6bf3a07d-fbde-4a49-9d99-163b60c9242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255838469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1255838469
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.797778275
Short name T496
Test name
Test status
Simulation time 2895956238 ps
CPU time 4.17 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:45:28 PM PDT 24
Peak memory 201384 kb
Host smart-105118ce-cf4f-4c16-9bb5-a11a10b4ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797778275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.797778275
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3407291903
Short name T85
Test name
Test status
Simulation time 4423831681 ps
CPU time 1.8 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:45:28 PM PDT 24
Peak memory 217040 kb
Host smart-21b37a59-c523-4d54-8b99-7c610ddf5051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407291903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3407291903
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1325641354
Short name T595
Test name
Test status
Simulation time 5601257570 ps
CPU time 6.85 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:45:40 PM PDT 24
Peak memory 201380 kb
Host smart-2afaf447-cc0a-4097-8393-87605a3399b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325641354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1325641354
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1800498261
Short name T124
Test name
Test status
Simulation time 136519095059 ps
CPU time 217.86 seconds
Started Aug 08 05:45:27 PM PDT 24
Finished Aug 08 05:49:05 PM PDT 24
Peak memory 211272 kb
Host smart-7033d87a-4809-41d7-8752-c5d75a961835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800498261 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1800498261
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.904514860
Short name T474
Test name
Test status
Simulation time 364666207 ps
CPU time 1.48 seconds
Started Aug 08 05:46:06 PM PDT 24
Finished Aug 08 05:46:08 PM PDT 24
Peak memory 201196 kb
Host smart-34398c91-061a-425a-941a-1512feac7c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904514860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.904514860
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.821517
Short name T268
Test name
Test status
Simulation time 170448978113 ps
CPU time 5.8 seconds
Started Aug 08 05:46:05 PM PDT 24
Finished Aug 08 05:46:11 PM PDT 24
Peak memory 200560 kb
Host smart-2a6473af-ffdf-4272-93b8-05ae9624c5bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gati
ng_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.821517
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.884985350
Short name T337
Test name
Test status
Simulation time 557237642752 ps
CPU time 429.73 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:53:21 PM PDT 24
Peak memory 201536 kb
Host smart-e92d2ea8-4e27-498c-88e8-aa71999856fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884985350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.884985350
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1309259435
Short name T650
Test name
Test status
Simulation time 332398672906 ps
CPU time 749.92 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:58:44 PM PDT 24
Peak memory 201432 kb
Host smart-9a3ad093-596f-472e-a433-efabf57238ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309259435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1309259435
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3365203469
Short name T108
Test name
Test status
Simulation time 494333955825 ps
CPU time 293.09 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:50:58 PM PDT 24
Peak memory 201444 kb
Host smart-279ced99-7e54-41c7-be89-c27705d2054e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365203469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3365203469
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.105893847
Short name T226
Test name
Test status
Simulation time 332159642527 ps
CPU time 786.41 seconds
Started Aug 08 05:46:08 PM PDT 24
Finished Aug 08 05:59:15 PM PDT 24
Peak memory 201448 kb
Host smart-f6d3e20f-5bd1-4b17-9dfb-4c5d8d3d3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105893847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.105893847
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.702852305
Short name T541
Test name
Test status
Simulation time 330127394942 ps
CPU time 416.53 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:53:08 PM PDT 24
Peak memory 201468 kb
Host smart-4706f4e0-3a64-4ef0-9dff-7557fe9ee6f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=702852305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.702852305
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.941503262
Short name T651
Test name
Test status
Simulation time 203730260328 ps
CPU time 37.2 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:46:51 PM PDT 24
Peak memory 201424 kb
Host smart-72b489ed-c91d-4dd5-815d-d8b8ea00165f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941503262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.941503262
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2662932932
Short name T694
Test name
Test status
Simulation time 124453699402 ps
CPU time 463.04 seconds
Started Aug 08 05:46:09 PM PDT 24
Finished Aug 08 05:53:52 PM PDT 24
Peak memory 201808 kb
Host smart-be803842-5bfe-41f4-833d-69dd55e4d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662932932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2662932932
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.143988218
Short name T195
Test name
Test status
Simulation time 31339219664 ps
CPU time 33.05 seconds
Started Aug 08 05:46:16 PM PDT 24
Finished Aug 08 05:46:49 PM PDT 24
Peak memory 201344 kb
Host smart-90cf422e-172a-4971-a002-cffda871cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143988218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.143988218
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1349321009
Short name T352
Test name
Test status
Simulation time 4635193146 ps
CPU time 11.15 seconds
Started Aug 08 05:46:08 PM PDT 24
Finished Aug 08 05:46:20 PM PDT 24
Peak memory 201276 kb
Host smart-6da8e086-0723-455e-be33-c75452606134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349321009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1349321009
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2755778102
Short name T201
Test name
Test status
Simulation time 5686779510 ps
CPU time 4.03 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:46:08 PM PDT 24
Peak memory 201328 kb
Host smart-b4477928-26b5-4d1d-a68a-e1026acd56a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755778102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2755778102
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2168117504
Short name T36
Test name
Test status
Simulation time 179558046928 ps
CPU time 197.34 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:49:28 PM PDT 24
Peak memory 201464 kb
Host smart-94cff4bc-3d1c-4a1f-84b2-4fbff4b681a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168117504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2168117504
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4285226495
Short name T242
Test name
Test status
Simulation time 77835639755 ps
CPU time 67.5 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:47:11 PM PDT 24
Peak memory 210056 kb
Host smart-8e4b7c7e-cd87-4ad1-a399-5141c7a01036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285226495 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4285226495
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1441408641
Short name T503
Test name
Test status
Simulation time 336500486 ps
CPU time 1.02 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:46:16 PM PDT 24
Peak memory 201252 kb
Host smart-3aaee6b3-9527-412e-ae7d-9c166f90fe0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441408641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1441408641
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1729659587
Short name T606
Test name
Test status
Simulation time 161331926610 ps
CPU time 359.54 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:52:13 PM PDT 24
Peak memory 201480 kb
Host smart-1d472a8b-708d-4388-b765-623d7d98082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729659587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1729659587
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3470296575
Short name T285
Test name
Test status
Simulation time 322264303537 ps
CPU time 681.78 seconds
Started Aug 08 05:46:03 PM PDT 24
Finished Aug 08 05:57:25 PM PDT 24
Peak memory 201512 kb
Host smart-e2b5d2a7-1381-4647-a302-2ff38d753ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470296575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3470296575
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1823812492
Short name T379
Test name
Test status
Simulation time 326600704815 ps
CPU time 184.84 seconds
Started Aug 08 05:46:11 PM PDT 24
Finished Aug 08 05:49:16 PM PDT 24
Peak memory 201464 kb
Host smart-af083362-57f1-4884-adfd-af6e8fa537aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823812492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1823812492
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.268167812
Short name T318
Test name
Test status
Simulation time 165743423379 ps
CPU time 183.88 seconds
Started Aug 08 05:46:10 PM PDT 24
Finished Aug 08 05:49:15 PM PDT 24
Peak memory 201480 kb
Host smart-aead3731-7348-478e-962b-9096406f47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268167812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.268167812
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3058071605
Short name T572
Test name
Test status
Simulation time 492115370250 ps
CPU time 304.52 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:51:17 PM PDT 24
Peak memory 201416 kb
Host smart-07e5de19-cdc5-4153-b9d2-da637cc91b4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058071605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3058071605
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2453984612
Short name T181
Test name
Test status
Simulation time 358089127873 ps
CPU time 161.38 seconds
Started Aug 08 05:46:05 PM PDT 24
Finished Aug 08 05:48:47 PM PDT 24
Peak memory 200448 kb
Host smart-168977eb-79e4-4bef-84e4-ce4e2934f4de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453984612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2453984612
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3125381241
Short name T566
Test name
Test status
Simulation time 401871726689 ps
CPU time 486.95 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:54:11 PM PDT 24
Peak memory 201432 kb
Host smart-127caf3c-65bb-4def-b670-0d72af9ab47c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125381241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3125381241
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.764089477
Short name T500
Test name
Test status
Simulation time 92482078665 ps
CPU time 482.28 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:54:17 PM PDT 24
Peak memory 201880 kb
Host smart-7d268784-3a52-4ed3-8dcb-014387007682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764089477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.764089477
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2394532853
Short name T187
Test name
Test status
Simulation time 30889729639 ps
CPU time 74.87 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 05:47:32 PM PDT 24
Peak memory 201364 kb
Host smart-07eb19ec-0973-4fb5-84a8-23fae4d7bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394532853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2394532853
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3660995549
Short name T417
Test name
Test status
Simulation time 4639366772 ps
CPU time 11.47 seconds
Started Aug 08 05:46:18 PM PDT 24
Finished Aug 08 05:46:30 PM PDT 24
Peak memory 201388 kb
Host smart-bd6df5b9-662f-48b3-b5f6-37de017c0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660995549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3660995549
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1226931108
Short name T4
Test name
Test status
Simulation time 5889021682 ps
CPU time 13.67 seconds
Started Aug 08 05:46:04 PM PDT 24
Finished Aug 08 05:46:18 PM PDT 24
Peak memory 201284 kb
Host smart-93eee084-c049-4cc9-9c51-8cfa147cf093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226931108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1226931108
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1700952289
Short name T290
Test name
Test status
Simulation time 435081424132 ps
CPU time 508.56 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 05:54:46 PM PDT 24
Peak memory 201780 kb
Host smart-3ba1c85f-3f8a-444e-8e08-77518fb77549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700952289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1700952289
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2570919005
Short name T27
Test name
Test status
Simulation time 249940351679 ps
CPU time 73.9 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:47:29 PM PDT 24
Peak memory 209844 kb
Host smart-955d27d5-2728-4b4a-b66c-d6c929270d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570919005 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2570919005
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2771172304
Short name T40
Test name
Test status
Simulation time 356341746 ps
CPU time 0.8 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 05:46:18 PM PDT 24
Peak memory 201176 kb
Host smart-edd0ecb5-20a7-4a79-9a5e-1d9f477dca58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771172304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2771172304
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2071224294
Short name T557
Test name
Test status
Simulation time 199167542151 ps
CPU time 135.87 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:48:29 PM PDT 24
Peak memory 201456 kb
Host smart-ca4319b8-dc49-4895-a8c8-d045a201506f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071224294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2071224294
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1008084987
Short name T575
Test name
Test status
Simulation time 327540150043 ps
CPU time 719.23 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:58:13 PM PDT 24
Peak memory 201484 kb
Host smart-0c1800f7-6c25-4066-ae61-e5e5f6fe7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008084987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1008084987
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.399941065
Short name T414
Test name
Test status
Simulation time 498370046129 ps
CPU time 1160.03 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 201696 kb
Host smart-5cd1bc2a-7682-436c-86b8-9165ef3f62ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=399941065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.399941065
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2242168917
Short name T601
Test name
Test status
Simulation time 334359290411 ps
CPU time 349.66 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:52:04 PM PDT 24
Peak memory 201576 kb
Host smart-dfd8cbad-7109-4e0d-bd8b-50813e74d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242168917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2242168917
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3168683066
Short name T616
Test name
Test status
Simulation time 331071207861 ps
CPU time 743.52 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 05:58:40 PM PDT 24
Peak memory 201428 kb
Host smart-b518e29f-1334-4ace-a83e-a948ab52a14b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168683066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3168683066
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2382302837
Short name T60
Test name
Test status
Simulation time 535895908891 ps
CPU time 241.65 seconds
Started Aug 08 05:46:16 PM PDT 24
Finished Aug 08 05:50:18 PM PDT 24
Peak memory 201420 kb
Host smart-438afaca-d2fc-4065-b4c6-1d1a0ee205ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382302837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2382302837
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2826920620
Short name T786
Test name
Test status
Simulation time 597301692190 ps
CPU time 928.02 seconds
Started Aug 08 05:46:17 PM PDT 24
Finished Aug 08 06:01:45 PM PDT 24
Peak memory 201464 kb
Host smart-f0426877-b93f-4550-8e1d-52810e93e060
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826920620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2826920620
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3340732039
Short name T711
Test name
Test status
Simulation time 116202917621 ps
CPU time 432.54 seconds
Started Aug 08 05:46:13 PM PDT 24
Finished Aug 08 05:53:25 PM PDT 24
Peak memory 201788 kb
Host smart-949f6121-3344-4a1a-80c0-d5d24c76099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340732039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3340732039
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.301253855
Short name T617
Test name
Test status
Simulation time 24530064919 ps
CPU time 59.79 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:47:15 PM PDT 24
Peak memory 201332 kb
Host smart-f396b616-88bc-48e5-8d70-bfad02dcfc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301253855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.301253855
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3076516202
Short name T704
Test name
Test status
Simulation time 4648677110 ps
CPU time 12.17 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:46:26 PM PDT 24
Peak memory 201312 kb
Host smart-d41201ff-c781-40fd-b1ad-4d59a756eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076516202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3076516202
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3518994128
Short name T518
Test name
Test status
Simulation time 5885355500 ps
CPU time 3.36 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:46:17 PM PDT 24
Peak memory 201376 kb
Host smart-7cb1cdf7-1438-4236-bd9a-0835f346d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518994128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3518994128
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.551761884
Short name T738
Test name
Test status
Simulation time 237324308104 ps
CPU time 304.81 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:51:20 PM PDT 24
Peak memory 210028 kb
Host smart-30ee7f92-6434-4590-a30b-b8b22b191033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551761884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
551761884
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3875238861
Short name T539
Test name
Test status
Simulation time 54085409437 ps
CPU time 37.05 seconds
Started Aug 08 05:46:16 PM PDT 24
Finished Aug 08 05:46:53 PM PDT 24
Peak memory 209856 kb
Host smart-9094ec90-fdd6-4303-835f-9fa10431d0ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875238861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3875238861
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.735677583
Short name T420
Test name
Test status
Simulation time 359052236 ps
CPU time 1.43 seconds
Started Aug 08 05:46:21 PM PDT 24
Finished Aug 08 05:46:23 PM PDT 24
Peak memory 201188 kb
Host smart-ab40150a-2545-42fd-984f-9a09b376bc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735677583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.735677583
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.649730919
Short name T338
Test name
Test status
Simulation time 187773780225 ps
CPU time 404.16 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 05:53:08 PM PDT 24
Peak memory 201432 kb
Host smart-b20a2803-bd23-43c5-a282-e044d511939a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649730919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.649730919
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1001138585
Short name T289
Test name
Test status
Simulation time 570845417358 ps
CPU time 413.46 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 05:53:18 PM PDT 24
Peak memory 201476 kb
Host smart-81c5b803-fcaf-491c-9291-bf8f85dc7a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001138585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1001138585
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1961334072
Short name T748
Test name
Test status
Simulation time 164796691252 ps
CPU time 40.87 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 05:47:07 PM PDT 24
Peak memory 201464 kb
Host smart-183d7be8-ce4e-4017-948b-38ae5321cf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961334072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1961334072
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2380592853
Short name T31
Test name
Test status
Simulation time 491511279715 ps
CPU time 399.44 seconds
Started Aug 08 05:46:22 PM PDT 24
Finished Aug 08 05:53:02 PM PDT 24
Peak memory 201468 kb
Host smart-b07082d8-6d95-4268-86d7-2aecff1978b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380592853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2380592853
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.509984616
Short name T202
Test name
Test status
Simulation time 327666096661 ps
CPU time 132.79 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:48:28 PM PDT 24
Peak memory 201452 kb
Host smart-e706b95a-6283-4abf-a7b2-4eb5b6f79193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509984616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.509984616
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1662128659
Short name T514
Test name
Test status
Simulation time 332514141993 ps
CPU time 357.84 seconds
Started Aug 08 05:46:15 PM PDT 24
Finished Aug 08 05:52:13 PM PDT 24
Peak memory 201456 kb
Host smart-80029783-733d-4a94-91cb-89b75cd441f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662128659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1662128659
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2845400179
Short name T480
Test name
Test status
Simulation time 221169793001 ps
CPU time 126.25 seconds
Started Aug 08 05:46:23 PM PDT 24
Finished Aug 08 05:48:29 PM PDT 24
Peak memory 201464 kb
Host smart-303746eb-915c-4a65-9847-c4ef46b57414
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845400179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2845400179
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4090810459
Short name T37
Test name
Test status
Simulation time 385224710014 ps
CPU time 966.99 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 06:02:31 PM PDT 24
Peak memory 201384 kb
Host smart-80d2ac89-347d-4b17-91b7-515872b0b2fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090810459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.4090810459
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3817317105
Short name T350
Test name
Test status
Simulation time 134353390637 ps
CPU time 490.77 seconds
Started Aug 08 05:46:27 PM PDT 24
Finished Aug 08 05:54:38 PM PDT 24
Peak memory 201732 kb
Host smart-6ea188f7-3191-49aa-92a1-74ce1b1e8724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817317105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3817317105
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3143875953
Short name T550
Test name
Test status
Simulation time 32392878018 ps
CPU time 18.78 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 05:46:44 PM PDT 24
Peak memory 201304 kb
Host smart-3bba83dd-41ab-4d0c-be5f-e2f002a7ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143875953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3143875953
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1966152140
Short name T424
Test name
Test status
Simulation time 4924269901 ps
CPU time 3.58 seconds
Started Aug 08 05:46:25 PM PDT 24
Finished Aug 08 05:46:29 PM PDT 24
Peak memory 201372 kb
Host smart-5d7bc3f4-e113-4c89-9b66-a25ddfd4f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966152140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1966152140
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2198471349
Short name T426
Test name
Test status
Simulation time 5704378842 ps
CPU time 13.3 seconds
Started Aug 08 05:46:14 PM PDT 24
Finished Aug 08 05:46:28 PM PDT 24
Peak memory 201344 kb
Host smart-2189be0e-b55b-4aff-abe1-85df31389fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198471349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2198471349
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.823812315
Short name T578
Test name
Test status
Simulation time 36154307026 ps
CPU time 19.41 seconds
Started Aug 08 05:46:23 PM PDT 24
Finished Aug 08 05:46:43 PM PDT 24
Peak memory 201356 kb
Host smart-c2dceeb9-5980-4e37-99f3-1982df96ed81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823812315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
823812315
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1808178170
Short name T218
Test name
Test status
Simulation time 72967166170 ps
CPU time 122.81 seconds
Started Aug 08 05:46:22 PM PDT 24
Finished Aug 08 05:48:25 PM PDT 24
Peak memory 217564 kb
Host smart-432e74f3-f77f-45d3-8cb4-7a40dd96ed61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808178170 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1808178170
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.751141407
Short name T183
Test name
Test status
Simulation time 478072527 ps
CPU time 0.88 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:46:34 PM PDT 24
Peak memory 201176 kb
Host smart-e6f68ac2-0e42-43e2-b829-9f11a57ca3ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751141407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.751141407
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2736773074
Short name T273
Test name
Test status
Simulation time 166405869747 ps
CPU time 381.12 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 05:52:47 PM PDT 24
Peak memory 201560 kb
Host smart-f5e1be84-c69a-433c-93cc-d5ef100bff59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736773074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2736773074
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3612100363
Short name T570
Test name
Test status
Simulation time 190230565702 ps
CPU time 411.39 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 05:53:18 PM PDT 24
Peak memory 201420 kb
Host smart-6b18d403-a00a-4cde-9bf2-be4825092347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612100363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3612100363
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1556880192
Short name T684
Test name
Test status
Simulation time 319174836962 ps
CPU time 770.26 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 05:59:14 PM PDT 24
Peak memory 201372 kb
Host smart-c5602d16-4d20-4ab3-8a45-b9090958dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556880192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1556880192
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.534698758
Short name T507
Test name
Test status
Simulation time 332340643505 ps
CPU time 769.99 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 05:59:16 PM PDT 24
Peak memory 201488 kb
Host smart-7d553d88-94e5-4ad1-8582-2d0c3fbda59b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534698758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.534698758
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1716191994
Short name T150
Test name
Test status
Simulation time 329110942628 ps
CPU time 357.89 seconds
Started Aug 08 05:46:27 PM PDT 24
Finished Aug 08 05:52:25 PM PDT 24
Peak memory 201384 kb
Host smart-f0b1db07-541f-4501-b627-72c7b49a233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716191994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1716191994
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1593653832
Short name T769
Test name
Test status
Simulation time 495915063763 ps
CPU time 1139.04 seconds
Started Aug 08 05:46:26 PM PDT 24
Finished Aug 08 06:05:25 PM PDT 24
Peak memory 201484 kb
Host smart-ad662f6a-7136-454a-bcb5-90bf03946c59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593653832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1593653832
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.767321168
Short name T258
Test name
Test status
Simulation time 532491197972 ps
CPU time 1232.36 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 06:06:56 PM PDT 24
Peak memory 201460 kb
Host smart-0deba2f5-e0f0-4a6f-a36f-b8b862f4c484
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767321168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.767321168
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.823179891
Short name T120
Test name
Test status
Simulation time 192994754379 ps
CPU time 473.17 seconds
Started Aug 08 05:46:25 PM PDT 24
Finished Aug 08 05:54:18 PM PDT 24
Peak memory 201464 kb
Host smart-929d72db-cd18-4b24-86ca-37c7cdf1fffa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823179891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.823179891
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.238700909
Short name T759
Test name
Test status
Simulation time 35942783153 ps
CPU time 83.63 seconds
Started Aug 08 05:46:23 PM PDT 24
Finished Aug 08 05:47:46 PM PDT 24
Peak memory 201376 kb
Host smart-3935616b-20f0-40f9-aaa3-148b754106a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238700909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.238700909
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.854786111
Short name T664
Test name
Test status
Simulation time 4889332549 ps
CPU time 6.02 seconds
Started Aug 08 05:46:23 PM PDT 24
Finished Aug 08 05:46:29 PM PDT 24
Peak memory 201276 kb
Host smart-ce0d00ac-eef1-4a47-b411-f156e9e41653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854786111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.854786111
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.880697144
Short name T722
Test name
Test status
Simulation time 6041071663 ps
CPU time 9.26 seconds
Started Aug 08 05:46:24 PM PDT 24
Finished Aug 08 05:46:33 PM PDT 24
Peak memory 201360 kb
Host smart-9c78582c-0cba-45e2-904e-836a256ed671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880697144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.880697144
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.239808264
Short name T581
Test name
Test status
Simulation time 397046249947 ps
CPU time 1207.95 seconds
Started Aug 08 05:46:31 PM PDT 24
Finished Aug 08 06:06:39 PM PDT 24
Peak memory 201888 kb
Host smart-06ddf7bd-882d-4a9b-94c0-35f5df8c142f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239808264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
239808264
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2271817968
Short name T20
Test name
Test status
Simulation time 137206961693 ps
CPU time 146.7 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:49:00 PM PDT 24
Peak memory 209800 kb
Host smart-86fc538b-4e35-44ea-acbe-6def76cd5b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271817968 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2271817968
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.112383903
Short name T472
Test name
Test status
Simulation time 353551401 ps
CPU time 0.81 seconds
Started Aug 08 05:46:34 PM PDT 24
Finished Aug 08 05:46:35 PM PDT 24
Peak memory 201252 kb
Host smart-ca7ec033-1add-4349-89e0-c6736d9ae8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112383903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.112383903
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1247780519
Short name T545
Test name
Test status
Simulation time 171423804455 ps
CPU time 66.5 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:47:40 PM PDT 24
Peak memory 201488 kb
Host smart-1193cbe9-2347-4ec5-8a5f-8b4e694bc945
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247780519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1247780519
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2832770825
Short name T764
Test name
Test status
Simulation time 163143101613 ps
CPU time 103.66 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:48:17 PM PDT 24
Peak memory 201532 kb
Host smart-9fcde8d2-a0ca-4676-ac10-2203b874bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832770825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2832770825
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3681299191
Short name T385
Test name
Test status
Simulation time 326507442582 ps
CPU time 685.25 seconds
Started Aug 08 05:46:32 PM PDT 24
Finished Aug 08 05:57:58 PM PDT 24
Peak memory 201472 kb
Host smart-d0cf7d28-2606-445c-a9b5-38399341334d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681299191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3681299191
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2394246421
Short name T282
Test name
Test status
Simulation time 160678552440 ps
CPU time 174.57 seconds
Started Aug 08 05:46:32 PM PDT 24
Finished Aug 08 05:49:27 PM PDT 24
Peak memory 201432 kb
Host smart-fa25d2b2-404e-4e0e-8163-f4d2d0af8828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394246421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2394246421
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.532078113
Short name T461
Test name
Test status
Simulation time 323718299954 ps
CPU time 615.83 seconds
Started Aug 08 05:46:31 PM PDT 24
Finished Aug 08 05:56:47 PM PDT 24
Peak memory 201424 kb
Host smart-aab2051f-fa56-4024-a602-af73d4e615e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=532078113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.532078113
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1941361021
Short name T106
Test name
Test status
Simulation time 363745864244 ps
CPU time 852.32 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 06:00:46 PM PDT 24
Peak memory 201444 kb
Host smart-96d7a9c5-1b3d-4dc6-9ddd-c6dbab6e6fc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941361021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1941361021
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.329233191
Short name T506
Test name
Test status
Simulation time 398825207839 ps
CPU time 860.18 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 06:00:54 PM PDT 24
Peak memory 201408 kb
Host smart-9a302521-28f7-4ae2-82d5-abbaa636763b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329233191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.329233191
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1438181096
Short name T447
Test name
Test status
Simulation time 133855171909 ps
CPU time 453.62 seconds
Started Aug 08 05:46:31 PM PDT 24
Finished Aug 08 05:54:05 PM PDT 24
Peak memory 202028 kb
Host smart-cf8547a4-f0be-4385-8f3e-c2d1e1925381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438181096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1438181096
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.834400966
Short name T783
Test name
Test status
Simulation time 34884597713 ps
CPU time 15.97 seconds
Started Aug 08 05:46:32 PM PDT 24
Finished Aug 08 05:46:49 PM PDT 24
Peak memory 201396 kb
Host smart-ad5ee8c3-fd37-40f3-8d37-ea6e07cf2478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834400966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.834400966
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2826552119
Short name T654
Test name
Test status
Simulation time 4355029050 ps
CPU time 5.59 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:46:38 PM PDT 24
Peak memory 201372 kb
Host smart-97409caa-abf8-4450-adaf-d5b6174f01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826552119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2826552119
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3281898804
Short name T559
Test name
Test status
Simulation time 5775113571 ps
CPU time 3.95 seconds
Started Aug 08 05:46:32 PM PDT 24
Finished Aug 08 05:46:36 PM PDT 24
Peak memory 201356 kb
Host smart-8e18d646-8811-4a87-8774-9211e8bfca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281898804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3281898804
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4168155982
Short name T660
Test name
Test status
Simulation time 375510457 ps
CPU time 1.49 seconds
Started Aug 08 05:46:48 PM PDT 24
Finished Aug 08 05:46:50 PM PDT 24
Peak memory 201180 kb
Host smart-8dbffbc1-279b-4b05-8f0d-1479b5359dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168155982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4168155982
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2796191591
Short name T189
Test name
Test status
Simulation time 348387779557 ps
CPU time 179.12 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:49:41 PM PDT 24
Peak memory 201400 kb
Host smart-f9a8a227-12d3-429a-bda0-02b5d1652f9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796191591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2796191591
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2328515749
Short name T305
Test name
Test status
Simulation time 332115661169 ps
CPU time 760.66 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:59:23 PM PDT 24
Peak memory 201484 kb
Host smart-4f0601a1-0fbc-430e-90d1-cc64ed3befc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328515749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2328515749
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2450202189
Short name T253
Test name
Test status
Simulation time 327674015843 ps
CPU time 198.48 seconds
Started Aug 08 05:46:40 PM PDT 24
Finished Aug 08 05:49:58 PM PDT 24
Peak memory 201488 kb
Host smart-2ab5d10e-f22c-4af5-b101-43b97bcd804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450202189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2450202189
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1423556149
Short name T645
Test name
Test status
Simulation time 495367944182 ps
CPU time 292.33 seconds
Started Aug 08 05:46:50 PM PDT 24
Finished Aug 08 05:51:42 PM PDT 24
Peak memory 201424 kb
Host smart-241b1657-895f-412f-81bb-712ccf6f7684
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423556149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1423556149
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2627745970
Short name T357
Test name
Test status
Simulation time 326655083837 ps
CPU time 141.52 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:48:54 PM PDT 24
Peak memory 201396 kb
Host smart-3d7e8af1-417b-4f2a-812a-6bd79d30aec1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627745970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2627745970
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3265830763
Short name T287
Test name
Test status
Simulation time 343077322697 ps
CPU time 218.22 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:50:21 PM PDT 24
Peak memory 201416 kb
Host smart-49676fae-e023-4c8f-910a-717b02dbd205
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265830763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3265830763
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3256023355
Short name T373
Test name
Test status
Simulation time 610290430214 ps
CPU time 1381.07 seconds
Started Aug 08 05:46:48 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 201368 kb
Host smart-647e917e-d6f6-4446-878b-61dbfcc7c2ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256023355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3256023355
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3267858440
Short name T209
Test name
Test status
Simulation time 139197584173 ps
CPU time 557.25 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:55:59 PM PDT 24
Peak memory 201760 kb
Host smart-0e0c4d96-1e31-4d64-801f-1734756f66b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267858440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3267858440
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2880047784
Short name T10
Test name
Test status
Simulation time 24283585090 ps
CPU time 14.57 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:46:56 PM PDT 24
Peak memory 201360 kb
Host smart-6026e1a3-7b93-4393-8f6e-a25f629b87d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880047784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2880047784
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3279707239
Short name T356
Test name
Test status
Simulation time 4316447090 ps
CPU time 2.46 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:46:43 PM PDT 24
Peak memory 201348 kb
Host smart-5516fc12-ad3a-4450-b240-3a7cc52d9194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279707239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3279707239
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2419340811
Short name T640
Test name
Test status
Simulation time 5698257972 ps
CPU time 13.51 seconds
Started Aug 08 05:46:33 PM PDT 24
Finished Aug 08 05:46:47 PM PDT 24
Peak memory 201272 kb
Host smart-898be8ab-a8b8-4fff-8510-02a8ac0699d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419340811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2419340811
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3439826737
Short name T198
Test name
Test status
Simulation time 173398113572 ps
CPU time 94.37 seconds
Started Aug 08 05:46:50 PM PDT 24
Finished Aug 08 05:48:24 PM PDT 24
Peak memory 201412 kb
Host smart-52669f64-da0f-41f8-a393-5c2315e935b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439826737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3439826737
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2311646843
Short name T597
Test name
Test status
Simulation time 282475238 ps
CPU time 1.23 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:46:55 PM PDT 24
Peak memory 201264 kb
Host smart-8f9b747d-9ec6-42ef-8af0-7ce64312dbc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311646843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2311646843
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.254787840
Short name T327
Test name
Test status
Simulation time 520048166404 ps
CPU time 366.45 seconds
Started Aug 08 05:46:51 PM PDT 24
Finished Aug 08 05:52:58 PM PDT 24
Peak memory 201400 kb
Host smart-039aaf8d-c743-437b-b2b8-fc7d91dcf12d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254787840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.254787840
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2165172615
Short name T443
Test name
Test status
Simulation time 166072009709 ps
CPU time 202.62 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:50:15 PM PDT 24
Peak memory 201476 kb
Host smart-7ce19be5-2cb8-43e7-8a51-102098f199b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165172615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2165172615
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3392518488
Short name T775
Test name
Test status
Simulation time 165356950704 ps
CPU time 67.04 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:47:49 PM PDT 24
Peak memory 201556 kb
Host smart-e36a1f3b-ae2e-49b8-b974-5ba66f469eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392518488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3392518488
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1207413101
Short name T466
Test name
Test status
Simulation time 493413043200 ps
CPU time 414.72 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:53:36 PM PDT 24
Peak memory 201532 kb
Host smart-df84f27b-2609-4553-b7b4-d5d55b664253
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207413101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1207413101
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2922730142
Short name T326
Test name
Test status
Simulation time 489498515974 ps
CPU time 176.95 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:49:38 PM PDT 24
Peak memory 201484 kb
Host smart-e43d61bf-6513-4b49-9c93-9a7ba6ab670b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922730142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2922730142
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.960899245
Short name T203
Test name
Test status
Simulation time 503287875097 ps
CPU time 296.8 seconds
Started Aug 08 05:46:42 PM PDT 24
Finished Aug 08 05:51:38 PM PDT 24
Peak memory 201456 kb
Host smart-0f697fae-b698-487c-a5e4-f82bbef9241c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=960899245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.960899245
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1268479395
Short name T274
Test name
Test status
Simulation time 173143189933 ps
CPU time 49.58 seconds
Started Aug 08 05:46:41 PM PDT 24
Finished Aug 08 05:47:31 PM PDT 24
Peak memory 201424 kb
Host smart-9a127397-826c-405f-afc6-def980a7eeb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268479395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1268479395
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4266593809
Short name T197
Test name
Test status
Simulation time 613391959990 ps
CPU time 768.35 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:59:40 PM PDT 24
Peak memory 201412 kb
Host smart-22fd7258-41b4-455a-ac47-cd5678109b81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266593809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4266593809
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1040985808
Short name T437
Test name
Test status
Simulation time 33631399426 ps
CPU time 19.67 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:47:11 PM PDT 24
Peak memory 201392 kb
Host smart-00af3c25-83f2-41ee-8221-98415ea0324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040985808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1040985808
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2688776918
Short name T380
Test name
Test status
Simulation time 4515675827 ps
CPU time 11.05 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:47:04 PM PDT 24
Peak memory 201372 kb
Host smart-bdf37289-736a-4edf-b542-ee37f31133e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688776918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2688776918
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1824208337
Short name T460
Test name
Test status
Simulation time 6038818023 ps
CPU time 14.4 seconds
Started Aug 08 05:46:40 PM PDT 24
Finished Aug 08 05:46:55 PM PDT 24
Peak memory 201360 kb
Host smart-f36c11b4-b179-4ec2-9c32-47c2089ae501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824208337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1824208337
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2336419379
Short name T17
Test name
Test status
Simulation time 292703619107 ps
CPU time 159.86 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:49:33 PM PDT 24
Peak memory 209804 kb
Host smart-80b4b79a-cae5-494f-a552-771919722d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336419379 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2336419379
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3115977183
Short name T389
Test name
Test status
Simulation time 404846744 ps
CPU time 1.1 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:47:05 PM PDT 24
Peak memory 201256 kb
Host smart-5ab050b6-5908-4498-8018-44ad935e6851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115977183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3115977183
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1435310157
Short name T693
Test name
Test status
Simulation time 342724360326 ps
CPU time 664.33 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:58:09 PM PDT 24
Peak memory 201464 kb
Host smart-a0a41b2e-7be2-4461-bf4b-4e88f730a81b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435310157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1435310157
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2337544662
Short name T179
Test name
Test status
Simulation time 322427452107 ps
CPU time 202.01 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:50:15 PM PDT 24
Peak memory 201380 kb
Host smart-fdfad055-84f6-4b56-804a-6ea5d5eb6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337544662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2337544662
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3931723446
Short name T625
Test name
Test status
Simulation time 164113281520 ps
CPU time 226.86 seconds
Started Aug 08 05:46:51 PM PDT 24
Finished Aug 08 05:50:38 PM PDT 24
Peak memory 201468 kb
Host smart-26a21a8c-3a8e-4a9a-825f-d5009e140706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931723446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3931723446
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1280691356
Short name T173
Test name
Test status
Simulation time 493342247573 ps
CPU time 315.13 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:52:07 PM PDT 24
Peak memory 201432 kb
Host smart-40e16a4b-496d-4cc4-935d-184f1aa36e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280691356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1280691356
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1465557569
Short name T453
Test name
Test status
Simulation time 335440941376 ps
CPU time 704.27 seconds
Started Aug 08 05:46:51 PM PDT 24
Finished Aug 08 05:58:35 PM PDT 24
Peak memory 201432 kb
Host smart-2a901fad-38b4-48f5-9fdb-618c8be0659b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465557569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1465557569
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4148681479
Short name T723
Test name
Test status
Simulation time 432675756639 ps
CPU time 462 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:54:35 PM PDT 24
Peak memory 201368 kb
Host smart-c7652357-4e94-47fa-ace9-5d3c87811798
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148681479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4148681479
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2009884863
Short name T62
Test name
Test status
Simulation time 194842046959 ps
CPU time 113.04 seconds
Started Aug 08 05:46:52 PM PDT 24
Finished Aug 08 05:48:46 PM PDT 24
Peak memory 201524 kb
Host smart-7f25208e-3c88-4d22-a6c1-28ff81732ce1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009884863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2009884863
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1798615632
Short name T110
Test name
Test status
Simulation time 39996927062 ps
CPU time 13.5 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:47:18 PM PDT 24
Peak memory 201360 kb
Host smart-23ae60cd-6bcc-4e3c-96fb-ff83446a88bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798615632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1798615632
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1627265677
Short name T558
Test name
Test status
Simulation time 3772530275 ps
CPU time 2.75 seconds
Started Aug 08 05:47:07 PM PDT 24
Finished Aug 08 05:47:10 PM PDT 24
Peak memory 199888 kb
Host smart-22269f54-9d79-4f4d-84ce-a03e2b145114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627265677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1627265677
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.776745685
Short name T382
Test name
Test status
Simulation time 5942433088 ps
CPU time 7.44 seconds
Started Aug 08 05:46:53 PM PDT 24
Finished Aug 08 05:47:01 PM PDT 24
Peak memory 199884 kb
Host smart-0e5ab78c-848d-4db4-b0cf-8a092ad1d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776745685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.776745685
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1277232503
Short name T624
Test name
Test status
Simulation time 237488596488 ps
CPU time 145.03 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:49:30 PM PDT 24
Peak memory 201484 kb
Host smart-d0855b6f-c198-45b2-8b25-2bc8d715168d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277232503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1277232503
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.871281181
Short name T313
Test name
Test status
Simulation time 74812952491 ps
CPU time 44.44 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:47:50 PM PDT 24
Peak memory 201516 kb
Host smart-2e901769-ee5a-4e34-b3ca-6b750b6d6bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871281181 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.871281181
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1900963446
Short name T363
Test name
Test status
Simulation time 288721581 ps
CPU time 1.28 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:47:44 PM PDT 24
Peak memory 201232 kb
Host smart-ebd9ae25-70d9-403a-8b4d-79f0f8fe0eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900963446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1900963446
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3354297677
Short name T319
Test name
Test status
Simulation time 167241936030 ps
CPU time 193.08 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:50:17 PM PDT 24
Peak memory 201496 kb
Host smart-f66ee095-8fd2-4a66-bce8-c9b6a41d70d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354297677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3354297677
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3239001882
Short name T344
Test name
Test status
Simulation time 163664756358 ps
CPU time 357.93 seconds
Started Aug 08 05:47:07 PM PDT 24
Finished Aug 08 05:53:05 PM PDT 24
Peak memory 201412 kb
Host smart-6a54e389-4e26-4ec3-8c13-e94f989c14d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239001882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3239001882
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1105966803
Short name T680
Test name
Test status
Simulation time 325229322725 ps
CPU time 357.55 seconds
Started Aug 08 05:47:07 PM PDT 24
Finished Aug 08 05:53:05 PM PDT 24
Peak memory 199968 kb
Host smart-a95c3150-adf1-4cc2-bbde-7a6c355ec851
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105966803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1105966803
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1875450636
Short name T561
Test name
Test status
Simulation time 482544410400 ps
CPU time 1144.26 seconds
Started Aug 08 05:47:03 PM PDT 24
Finished Aug 08 06:06:08 PM PDT 24
Peak memory 201444 kb
Host smart-2620e5af-edb9-43c3-ad38-2c6c54c2dfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875450636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1875450636
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3690606808
Short name T431
Test name
Test status
Simulation time 327744530064 ps
CPU time 370.76 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:53:15 PM PDT 24
Peak memory 201432 kb
Host smart-6df11d12-18aa-4393-8128-f14bfebb20ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690606808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3690606808
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3144934679
Short name T627
Test name
Test status
Simulation time 594112816812 ps
CPU time 1430.01 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 06:10:55 PM PDT 24
Peak memory 201452 kb
Host smart-92e65165-75bf-45fd-a155-6c48df28052b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144934679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3144934679
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2572951526
Short name T483
Test name
Test status
Simulation time 120816291861 ps
CPU time 639.65 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:58:22 PM PDT 24
Peak memory 201772 kb
Host smart-cbdfe95b-fabf-40fc-ad75-faa1b3e328b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572951526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2572951526
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1550052280
Short name T435
Test name
Test status
Simulation time 34666116744 ps
CPU time 55 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:48:00 PM PDT 24
Peak memory 201384 kb
Host smart-0e6196b5-a63b-47fe-9404-f71d1f8cf0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550052280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1550052280
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1220683927
Short name T407
Test name
Test status
Simulation time 4389718946 ps
CPU time 5.84 seconds
Started Aug 08 05:47:05 PM PDT 24
Finished Aug 08 05:47:11 PM PDT 24
Peak memory 201292 kb
Host smart-d6c39ebb-c039-4d95-a7a9-2d175aeeb451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220683927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1220683927
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2790628344
Short name T499
Test name
Test status
Simulation time 6167772812 ps
CPU time 4.25 seconds
Started Aug 08 05:47:04 PM PDT 24
Finished Aug 08 05:47:09 PM PDT 24
Peak memory 201332 kb
Host smart-3b318770-8528-4b43-be64-82791b7f8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790628344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2790628344
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1188763572
Short name T670
Test name
Test status
Simulation time 207718749496 ps
CPU time 495.45 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:55:58 PM PDT 24
Peak memory 201496 kb
Host smart-d7483e1f-e1bd-46f4-a8ae-ea2fba3d8f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188763572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1188763572
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.327099708
Short name T212
Test name
Test status
Simulation time 388662685758 ps
CPU time 615.48 seconds
Started Aug 08 05:47:44 PM PDT 24
Finished Aug 08 05:58:00 PM PDT 24
Peak memory 210100 kb
Host smart-15d4b864-e237-4de1-8c98-bdd6c53af6d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327099708 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.327099708
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.688985984
Short name T725
Test name
Test status
Simulation time 421936535 ps
CPU time 1.56 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:45:39 PM PDT 24
Peak memory 201236 kb
Host smart-4329a191-ba30-4cbf-90b1-7a862164b6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688985984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.688985984
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.945948772
Short name T631
Test name
Test status
Simulation time 361213504690 ps
CPU time 729.62 seconds
Started Aug 08 05:45:30 PM PDT 24
Finished Aug 08 05:57:40 PM PDT 24
Peak memory 201508 kb
Host smart-2365f7a8-d0d2-4d2d-850e-b90e59c32c92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945948772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.945948772
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3981487606
Short name T343
Test name
Test status
Simulation time 323337346510 ps
CPU time 822.88 seconds
Started Aug 08 05:45:31 PM PDT 24
Finished Aug 08 05:59:14 PM PDT 24
Peak memory 201428 kb
Host smart-cec9bdbb-728e-4329-8c5b-564dc495014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981487606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3981487606
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3913942718
Short name T653
Test name
Test status
Simulation time 164745404430 ps
CPU time 398.89 seconds
Started Aug 08 05:45:27 PM PDT 24
Finished Aug 08 05:52:06 PM PDT 24
Peak memory 201480 kb
Host smart-014ea6f7-09d3-4068-b788-215bb858f60c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913942718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3913942718
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3116069803
Short name T635
Test name
Test status
Simulation time 333900222372 ps
CPU time 211.57 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:48:58 PM PDT 24
Peak memory 201436 kb
Host smart-56ee2ca6-906f-44d2-937a-039e30561b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116069803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3116069803
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2953574346
Short name T551
Test name
Test status
Simulation time 494067151177 ps
CPU time 243.24 seconds
Started Aug 08 05:45:32 PM PDT 24
Finished Aug 08 05:49:35 PM PDT 24
Peak memory 201436 kb
Host smart-2ae048b5-909d-4cf3-8113-c26c275cf530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953574346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2953574346
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3928240094
Short name T543
Test name
Test status
Simulation time 382494541950 ps
CPU time 899.05 seconds
Started Aug 08 05:45:31 PM PDT 24
Finished Aug 08 06:00:30 PM PDT 24
Peak memory 201480 kb
Host smart-bf3d273a-9db0-4eb7-b039-90a31a2a6de0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928240094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3928240094
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1552961525
Short name T441
Test name
Test status
Simulation time 417963991541 ps
CPU time 486.03 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:53:41 PM PDT 24
Peak memory 201460 kb
Host smart-805e5fd7-1902-4908-b38f-7f53ad8fe5ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552961525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1552961525
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.690659357
Short name T750
Test name
Test status
Simulation time 68227035629 ps
CPU time 218.23 seconds
Started Aug 08 05:45:24 PM PDT 24
Finished Aug 08 05:49:02 PM PDT 24
Peak memory 201840 kb
Host smart-87c193f9-5875-4096-bfb4-b15d83769fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690659357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.690659357
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.216926296
Short name T646
Test name
Test status
Simulation time 35393555463 ps
CPU time 86.31 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:47:02 PM PDT 24
Peak memory 201396 kb
Host smart-0fbadd04-8cf3-4dad-8360-cd5ba16776c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216926296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.216926296
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.432255908
Short name T487
Test name
Test status
Simulation time 5298723711 ps
CPU time 7.13 seconds
Started Aug 08 05:45:27 PM PDT 24
Finished Aug 08 05:45:34 PM PDT 24
Peak memory 201392 kb
Host smart-73b14be8-68f2-41ad-8b11-7ef9291ef119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432255908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.432255908
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.852842107
Short name T102
Test name
Test status
Simulation time 7978032534 ps
CPU time 5.54 seconds
Started Aug 08 05:45:27 PM PDT 24
Finished Aug 08 05:45:33 PM PDT 24
Peak memory 217136 kb
Host smart-8e31b64b-a4bb-4131-bb85-89183f7a70ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852842107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.852842107
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2218485859
Short name T416
Test name
Test status
Simulation time 5656488293 ps
CPU time 13.08 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:48 PM PDT 24
Peak memory 201384 kb
Host smart-9e71d684-1948-4ba6-a7c3-02c266e63e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218485859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2218485859
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3891078488
Short name T661
Test name
Test status
Simulation time 686751992102 ps
CPU time 2225.93 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 06:22:39 PM PDT 24
Peak memory 209992 kb
Host smart-f19ea44a-7185-4800-b5e0-b0c854095396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891078488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3891078488
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.826962552
Short name T263
Test name
Test status
Simulation time 258351042265 ps
CPU time 286.26 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:50:19 PM PDT 24
Peak memory 217416 kb
Host smart-142eaa7f-7a4c-43f7-ab90-df636ed31660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826962552 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.826962552
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.618553897
Short name T692
Test name
Test status
Simulation time 540955994 ps
CPU time 0.9 seconds
Started Aug 08 05:47:44 PM PDT 24
Finished Aug 08 05:47:45 PM PDT 24
Peak memory 201096 kb
Host smart-9a071fe2-1c71-4ccf-8915-74e93de42775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618553897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.618553897
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3799146929
Short name T302
Test name
Test status
Simulation time 165749341364 ps
CPU time 349.86 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:53:32 PM PDT 24
Peak memory 201436 kb
Host smart-193742c2-2c2c-41be-9874-78c9e75b0d33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799146929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3799146929
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3446708803
Short name T272
Test name
Test status
Simulation time 164581504984 ps
CPU time 407.69 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:54:30 PM PDT 24
Peak memory 201428 kb
Host smart-7f435a3a-f06f-4b6b-b005-5e36cc78b171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446708803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3446708803
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3312504617
Short name T275
Test name
Test status
Simulation time 490773557701 ps
CPU time 296.54 seconds
Started Aug 08 05:47:43 PM PDT 24
Finished Aug 08 05:52:39 PM PDT 24
Peak memory 201408 kb
Host smart-c5988d37-437d-41bf-ad0b-efa8b9040a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312504617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3312504617
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1679192029
Short name T710
Test name
Test status
Simulation time 167408789849 ps
CPU time 372.67 seconds
Started Aug 08 05:47:43 PM PDT 24
Finished Aug 08 05:53:56 PM PDT 24
Peak memory 201340 kb
Host smart-40c029f8-fde9-40c1-9cc4-81713ef4b8d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679192029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1679192029
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2342841618
Short name T724
Test name
Test status
Simulation time 162103159754 ps
CPU time 358.47 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:53:41 PM PDT 24
Peak memory 201436 kb
Host smart-7cd464e8-1c6e-4e0e-b2a1-22cd9c994b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342841618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2342841618
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4159104434
Short name T126
Test name
Test status
Simulation time 325584722622 ps
CPU time 202.39 seconds
Started Aug 08 05:47:43 PM PDT 24
Finished Aug 08 05:51:06 PM PDT 24
Peak memory 201500 kb
Host smart-613941bd-7c2a-475b-aa78-07f262202e87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159104434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4159104434
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.935842447
Short name T245
Test name
Test status
Simulation time 415330943473 ps
CPU time 467.34 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:55:30 PM PDT 24
Peak memory 201396 kb
Host smart-e51bac91-1eca-420f-b43e-f434b369d59b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935842447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.935842447
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1560131880
Short name T361
Test name
Test status
Simulation time 402777006220 ps
CPU time 539.6 seconds
Started Aug 08 05:47:41 PM PDT 24
Finished Aug 08 05:56:41 PM PDT 24
Peak memory 201456 kb
Host smart-584659f1-6dc8-46fe-9d41-71ebdb25b893
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560131880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1560131880
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2478528400
Short name T219
Test name
Test status
Simulation time 80467327158 ps
CPU time 327.68 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:53:13 PM PDT 24
Peak memory 201816 kb
Host smart-938c1d05-1566-4674-a31d-1e867e740890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478528400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2478528400
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4252749110
Short name T656
Test name
Test status
Simulation time 32049039600 ps
CPU time 35.36 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:48:18 PM PDT 24
Peak memory 201396 kb
Host smart-95d77a63-a33b-48ae-8fe2-9f0530982ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252749110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4252749110
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3359796847
Short name T364
Test name
Test status
Simulation time 5354680382 ps
CPU time 3.48 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:47:45 PM PDT 24
Peak memory 201336 kb
Host smart-2fda795a-7875-4937-855d-83bfa06382ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359796847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3359796847
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.825292978
Short name T368
Test name
Test status
Simulation time 5730169428 ps
CPU time 14.76 seconds
Started Aug 08 05:47:42 PM PDT 24
Finished Aug 08 05:47:57 PM PDT 24
Peak memory 201384 kb
Host smart-31696b26-4ba5-4bb2-a5f3-49e6a7cf7198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825292978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.825292978
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1274251281
Short name T706
Test name
Test status
Simulation time 168326054292 ps
CPU time 161.04 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:50:26 PM PDT 24
Peak memory 201444 kb
Host smart-a579f868-2dd3-4ca8-9d9d-b40e7b1b185e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274251281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1274251281
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3706218654
Short name T45
Test name
Test status
Simulation time 46522728760 ps
CPU time 105.02 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:49:30 PM PDT 24
Peak memory 210092 kb
Host smart-63e09377-6362-4525-837b-4301bb988975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706218654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3706218654
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3790497383
Short name T607
Test name
Test status
Simulation time 416838012 ps
CPU time 0.74 seconds
Started Aug 08 05:47:47 PM PDT 24
Finished Aug 08 05:47:48 PM PDT 24
Peak memory 201424 kb
Host smart-0bef35f7-5cbc-429f-829f-643d5bc29b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790497383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3790497383
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3274391633
Short name T594
Test name
Test status
Simulation time 344626284757 ps
CPU time 708.24 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:59:34 PM PDT 24
Peak memory 201404 kb
Host smart-4384853a-5671-444c-9ddd-9ab0febdd79a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274391633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3274391633
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.923234345
Short name T255
Test name
Test status
Simulation time 557642798326 ps
CPU time 1264.99 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 06:08:56 PM PDT 24
Peak memory 201568 kb
Host smart-5d6e4d32-8335-4492-8afa-99f0fafbed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923234345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.923234345
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1431635900
Short name T232
Test name
Test status
Simulation time 166422386607 ps
CPU time 393.97 seconds
Started Aug 08 05:47:46 PM PDT 24
Finished Aug 08 05:54:20 PM PDT 24
Peak memory 201376 kb
Host smart-b1e1ca68-359d-462e-87a3-55812e405078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431635900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1431635900
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1569866611
Short name T582
Test name
Test status
Simulation time 162256597138 ps
CPU time 91.04 seconds
Started Aug 08 05:47:46 PM PDT 24
Finished Aug 08 05:49:17 PM PDT 24
Peak memory 201472 kb
Host smart-d2b247a8-97db-406a-9f74-48c3240c9613
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569866611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1569866611
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2104283765
Short name T50
Test name
Test status
Simulation time 492574159730 ps
CPU time 582.65 seconds
Started Aug 08 05:47:46 PM PDT 24
Finished Aug 08 05:57:28 PM PDT 24
Peak memory 201468 kb
Host smart-bd7a3522-5f63-4289-9c60-df598ac1e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104283765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2104283765
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1174233383
Short name T49
Test name
Test status
Simulation time 162972344051 ps
CPU time 355.83 seconds
Started Aug 08 05:47:46 PM PDT 24
Finished Aug 08 05:53:42 PM PDT 24
Peak memory 201400 kb
Host smart-5b0b4def-be2a-4575-9ef7-44874f2638df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174233383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1174233383
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2334258698
Short name T731
Test name
Test status
Simulation time 618869365164 ps
CPU time 1409.87 seconds
Started Aug 08 05:47:46 PM PDT 24
Finished Aug 08 06:11:16 PM PDT 24
Peak memory 201516 kb
Host smart-1ed130f3-1078-4700-8e1a-8f0cda460b42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334258698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2334258698
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.675059179
Short name T553
Test name
Test status
Simulation time 391119568093 ps
CPU time 215.23 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:51:21 PM PDT 24
Peak memory 201460 kb
Host smart-c2e71249-2477-41f2-8e42-9a03f9a571a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675059179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.675059179
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2975000724
Short name T491
Test name
Test status
Simulation time 80734781472 ps
CPU time 236.69 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:51:47 PM PDT 24
Peak memory 201732 kb
Host smart-4ffcda52-45a5-4ef5-abdb-cf5c8774db30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975000724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2975000724
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.205986740
Short name T672
Test name
Test status
Simulation time 22894829322 ps
CPU time 14.22 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:48:05 PM PDT 24
Peak memory 201348 kb
Host smart-2021bf9d-fe65-478f-bba5-d7e6bf22d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205986740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.205986740
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.213190396
Short name T554
Test name
Test status
Simulation time 4526566380 ps
CPU time 11.11 seconds
Started Aug 08 05:47:49 PM PDT 24
Finished Aug 08 05:48:01 PM PDT 24
Peak memory 201348 kb
Host smart-783b5454-30d1-4158-9b41-3a5b8cc684de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213190396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.213190396
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1911769968
Short name T647
Test name
Test status
Simulation time 6278740317 ps
CPU time 1.94 seconds
Started Aug 08 05:47:45 PM PDT 24
Finished Aug 08 05:47:47 PM PDT 24
Peak memory 201380 kb
Host smart-a606e7e5-cc19-4195-8b16-0a7c9f998d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911769968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1911769968
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1563247031
Short name T765
Test name
Test status
Simulation time 526478477819 ps
CPU time 551.77 seconds
Started Aug 08 05:47:48 PM PDT 24
Finished Aug 08 05:57:00 PM PDT 24
Peak memory 201424 kb
Host smart-305243cc-4544-4bd8-8d3f-029f1aa20813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563247031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1563247031
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3332286854
Short name T671
Test name
Test status
Simulation time 474211255 ps
CPU time 1.72 seconds
Started Aug 08 05:47:53 PM PDT 24
Finished Aug 08 05:47:54 PM PDT 24
Peak memory 201252 kb
Host smart-02b0353a-29cc-4c8e-855d-e166c57ef9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332286854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3332286854
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1039562200
Short name T151
Test name
Test status
Simulation time 168523352908 ps
CPU time 378.17 seconds
Started Aug 08 05:47:47 PM PDT 24
Finished Aug 08 05:54:06 PM PDT 24
Peak memory 201528 kb
Host smart-6ba269f2-54ac-4984-b2bb-9a484889f97b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039562200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1039562200
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.113227533
Short name T239
Test name
Test status
Simulation time 518974699197 ps
CPU time 303 seconds
Started Aug 08 05:47:54 PM PDT 24
Finished Aug 08 05:52:57 PM PDT 24
Peak memory 201400 kb
Host smart-d0af0741-626f-4628-9230-81c9196e4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113227533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.113227533
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4082594772
Short name T320
Test name
Test status
Simulation time 488551290316 ps
CPU time 455.73 seconds
Started Aug 08 05:47:49 PM PDT 24
Finished Aug 08 05:55:25 PM PDT 24
Peak memory 201428 kb
Host smart-2a08a96c-4d2e-444e-8c33-84a1197bcec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082594772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4082594772
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4259206777
Short name T642
Test name
Test status
Simulation time 166094252926 ps
CPU time 204.79 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:51:15 PM PDT 24
Peak memory 201496 kb
Host smart-e211ec70-605f-4b7a-a123-9ce32ac1bb19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259206777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4259206777
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1183394396
Short name T329
Test name
Test status
Simulation time 334890732006 ps
CPU time 391.36 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:54:22 PM PDT 24
Peak memory 201468 kb
Host smart-fc5276cd-9db4-4f94-a1e1-bedff6ac15b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183394396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1183394396
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2069936971
Short name T734
Test name
Test status
Simulation time 501826871129 ps
CPU time 349.2 seconds
Started Aug 08 05:47:49 PM PDT 24
Finished Aug 08 05:53:39 PM PDT 24
Peak memory 201484 kb
Host smart-6bedaa49-001a-4591-8286-5020fcc5c623
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069936971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2069936971
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1120808697
Short name T2
Test name
Test status
Simulation time 660388896548 ps
CPU time 821.4 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 06:01:32 PM PDT 24
Peak memory 201468 kb
Host smart-87a45cde-1ad6-4e13-aaf7-5de5743eedcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120808697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1120808697
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.833098607
Short name T763
Test name
Test status
Simulation time 596500689237 ps
CPU time 242.63 seconds
Started Aug 08 05:47:50 PM PDT 24
Finished Aug 08 05:51:53 PM PDT 24
Peak memory 201340 kb
Host smart-3d5615ce-a64e-49f4-84e1-5d9dbc5a71d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833098607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.833098607
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1890867455
Short name T351
Test name
Test status
Simulation time 127787605497 ps
CPU time 676.55 seconds
Started Aug 08 05:47:54 PM PDT 24
Finished Aug 08 05:59:11 PM PDT 24
Peak memory 201848 kb
Host smart-61462748-0095-40b5-a6fe-b4bc9a5efcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890867455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1890867455
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3559780507
Short name T629
Test name
Test status
Simulation time 33879638386 ps
CPU time 78.71 seconds
Started Aug 08 05:47:53 PM PDT 24
Finished Aug 08 05:49:12 PM PDT 24
Peak memory 201332 kb
Host smart-97b7e963-8b07-4975-88a8-e7c630751f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559780507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3559780507
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2502348187
Short name T502
Test name
Test status
Simulation time 5192222972 ps
CPU time 3.85 seconds
Started Aug 08 05:47:52 PM PDT 24
Finished Aug 08 05:47:56 PM PDT 24
Peak memory 201356 kb
Host smart-a448631b-ccc4-4ff9-a48a-bdb90e11fa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502348187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2502348187
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.4183958030
Short name T648
Test name
Test status
Simulation time 5939574033 ps
CPU time 7.31 seconds
Started Aug 08 05:47:51 PM PDT 24
Finished Aug 08 05:47:58 PM PDT 24
Peak memory 201360 kb
Host smart-42aa513b-92e4-4431-899b-36293f98c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183958030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4183958030
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1196175570
Short name T122
Test name
Test status
Simulation time 331374995 ps
CPU time 0.84 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:48:03 PM PDT 24
Peak memory 201256 kb
Host smart-f710dec3-769d-462c-ac5a-dbf3f7326026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196175570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1196175570
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.379915204
Short name T112
Test name
Test status
Simulation time 494338235110 ps
CPU time 202.16 seconds
Started Aug 08 05:47:55 PM PDT 24
Finished Aug 08 05:51:17 PM PDT 24
Peak memory 199972 kb
Host smart-f04cd0c5-3172-47b1-a1c5-995f7393ab21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379915204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.379915204
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3322645592
Short name T778
Test name
Test status
Simulation time 169013659639 ps
CPU time 363.33 seconds
Started Aug 08 05:47:52 PM PDT 24
Finished Aug 08 05:53:55 PM PDT 24
Peak memory 201444 kb
Host smart-c6d56d4d-9115-499a-985a-43e9acfc2933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322645592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3322645592
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3958174545
Short name T552
Test name
Test status
Simulation time 488368139324 ps
CPU time 1141.25 seconds
Started Aug 08 05:47:57 PM PDT 24
Finished Aug 08 06:06:59 PM PDT 24
Peak memory 201460 kb
Host smart-e52d5b72-bc7d-4242-9ee5-022cad02354e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958174545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3958174545
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.550178998
Short name T48
Test name
Test status
Simulation time 331681247148 ps
CPU time 414.17 seconds
Started Aug 08 05:47:53 PM PDT 24
Finished Aug 08 05:54:47 PM PDT 24
Peak memory 201476 kb
Host smart-cdb2cdcf-a3df-4d49-8047-37c291256655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550178998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.550178998
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.856815373
Short name T535
Test name
Test status
Simulation time 162901093915 ps
CPU time 70.24 seconds
Started Aug 08 05:47:54 PM PDT 24
Finished Aug 08 05:49:04 PM PDT 24
Peak memory 201632 kb
Host smart-f0025fca-339c-4b60-8a4e-c3129dbd2c1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=856815373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.856815373
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.804193087
Short name T54
Test name
Test status
Simulation time 543109609436 ps
CPU time 1221.98 seconds
Started Aug 08 05:47:53 PM PDT 24
Finished Aug 08 06:08:15 PM PDT 24
Peak memory 201372 kb
Host smart-0b199062-7789-4ac2-a666-742021e05d10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804193087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.804193087
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2251157782
Short name T401
Test name
Test status
Simulation time 601966809276 ps
CPU time 1419.15 seconds
Started Aug 08 05:47:55 PM PDT 24
Finished Aug 08 06:11:34 PM PDT 24
Peak memory 201484 kb
Host smart-97d529d6-5f8d-4d3e-b8da-72250c0e228d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251157782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2251157782
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2675219707
Short name T14
Test name
Test status
Simulation time 123946500818 ps
CPU time 421.66 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:55:04 PM PDT 24
Peak memory 201812 kb
Host smart-ea0f9b1c-f268-4e7c-8105-fb9ddf495f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675219707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2675219707
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.187253636
Short name T390
Test name
Test status
Simulation time 37471107662 ps
CPU time 90.41 seconds
Started Aug 08 05:48:03 PM PDT 24
Finished Aug 08 05:49:33 PM PDT 24
Peak memory 201344 kb
Host smart-df633460-f913-4040-bf72-760827c66fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187253636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.187253636
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4184131910
Short name T147
Test name
Test status
Simulation time 3498827866 ps
CPU time 7.74 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:48:10 PM PDT 24
Peak memory 201352 kb
Host smart-23b0e4a8-723c-4390-b713-cab5282ea277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184131910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4184131910
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2101952047
Short name T111
Test name
Test status
Simulation time 5965075934 ps
CPU time 13.51 seconds
Started Aug 08 05:47:54 PM PDT 24
Finished Aug 08 05:48:08 PM PDT 24
Peak memory 201332 kb
Host smart-18ad47eb-7179-4934-b952-cec30c587156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101952047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2101952047
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.44632434
Short name T163
Test name
Test status
Simulation time 500218693249 ps
CPU time 587.44 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:57:55 PM PDT 24
Peak memory 201536 kb
Host smart-d0f11193-dc93-45b3-b40e-b207acd3648d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44632434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.44632434
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2429009537
Short name T23
Test name
Test status
Simulation time 140478533948 ps
CPU time 210.49 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:51:32 PM PDT 24
Peak memory 210100 kb
Host smart-f7031b4b-77cb-4e67-8ae2-5018e1894c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429009537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2429009537
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2151257739
Short name T415
Test name
Test status
Simulation time 510571386 ps
CPU time 1.7 seconds
Started Aug 08 05:48:05 PM PDT 24
Finished Aug 08 05:48:07 PM PDT 24
Peak memory 201204 kb
Host smart-13a5af05-ea33-4167-815d-78163091d4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151257739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2151257739
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.700750194
Short name T32
Test name
Test status
Simulation time 210663586694 ps
CPU time 249.55 seconds
Started Aug 08 05:48:00 PM PDT 24
Finished Aug 08 05:52:10 PM PDT 24
Peak memory 201396 kb
Host smart-4bfc7155-f22b-42f0-ac38-c33e1f4ad734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700750194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.700750194
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2756369981
Short name T665
Test name
Test status
Simulation time 165182627175 ps
CPU time 228 seconds
Started Aug 08 05:48:01 PM PDT 24
Finished Aug 08 05:51:49 PM PDT 24
Peak memory 201484 kb
Host smart-c0d927ea-8643-4e49-808f-37cab367e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756369981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2756369981
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1655912985
Short name T508
Test name
Test status
Simulation time 165585894929 ps
CPU time 107.94 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:49:55 PM PDT 24
Peak memory 201508 kb
Host smart-8d56d789-7172-4d12-ab34-7030589e39bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655912985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1655912985
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3271768019
Short name T504
Test name
Test status
Simulation time 160658901089 ps
CPU time 61.64 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:49:09 PM PDT 24
Peak memory 201468 kb
Host smart-792244fe-be7e-4fd3-acf2-c846918b8b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271768019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3271768019
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.106986172
Short name T153
Test name
Test status
Simulation time 490621594610 ps
CPU time 594.93 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:57:57 PM PDT 24
Peak memory 201472 kb
Host smart-162c0bda-4439-4e73-a606-f10c045a3da0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=106986172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.106986172
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.4213364333
Short name T286
Test name
Test status
Simulation time 388931616113 ps
CPU time 848.23 seconds
Started Aug 08 05:48:03 PM PDT 24
Finished Aug 08 06:02:11 PM PDT 24
Peak memory 201436 kb
Host smart-77a24bf0-35cd-4c3e-aabf-2315a1debb3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213364333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.4213364333
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3637687369
Short name T170
Test name
Test status
Simulation time 595970140490 ps
CPU time 361.46 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:54:03 PM PDT 24
Peak memory 201416 kb
Host smart-7d0fa319-131b-41c6-b830-50dd894898e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637687369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3637687369
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2221918826
Short name T719
Test name
Test status
Simulation time 91719860750 ps
CPU time 300.3 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:53:07 PM PDT 24
Peak memory 201832 kb
Host smart-b0843590-7fe7-4fc2-a46d-69c92323d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221918826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2221918826
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.120673585
Short name T200
Test name
Test status
Simulation time 35193827344 ps
CPU time 37.82 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:48:40 PM PDT 24
Peak memory 201396 kb
Host smart-dfce11f4-57be-4f48-93e0-e6984db7f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120673585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.120673585
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.49634059
Short name T353
Test name
Test status
Simulation time 4480397896 ps
CPU time 2.73 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:48:05 PM PDT 24
Peak memory 201396 kb
Host smart-57950630-f7dd-4df5-8aec-bd35a38b5f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49634059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.49634059
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1166360992
Short name T371
Test name
Test status
Simulation time 5971174131 ps
CPU time 7.64 seconds
Started Aug 08 05:48:02 PM PDT 24
Finished Aug 08 05:48:09 PM PDT 24
Peak memory 201340 kb
Host smart-eb18c83f-768a-49c0-a94e-2c63e5939ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166360992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1166360992
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1196762839
Short name T528
Test name
Test status
Simulation time 435111150029 ps
CPU time 581.25 seconds
Started Aug 08 05:48:05 PM PDT 24
Finished Aug 08 05:57:46 PM PDT 24
Peak memory 201868 kb
Host smart-c27ce882-8d67-4d05-80f1-a8b0d39ecf71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196762839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1196762839
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1324088324
Short name T697
Test name
Test status
Simulation time 50155139363 ps
CPU time 32.2 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:48:39 PM PDT 24
Peak memory 209860 kb
Host smart-88a7d1f6-acdc-4047-9c0f-ef1380b34078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324088324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1324088324
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.261755429
Short name T406
Test name
Test status
Simulation time 351491084 ps
CPU time 0.76 seconds
Started Aug 08 05:48:11 PM PDT 24
Finished Aug 08 05:48:11 PM PDT 24
Peak memory 201188 kb
Host smart-534cb2d2-0adf-4292-ba46-f1518ae00551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261755429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.261755429
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3404361767
Short name T311
Test name
Test status
Simulation time 592897251587 ps
CPU time 293.33 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:53:00 PM PDT 24
Peak memory 201468 kb
Host smart-52e8e05e-6469-41a3-b3a8-f7e634c78f12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404361767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3404361767
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.408683496
Short name T339
Test name
Test status
Simulation time 508057345475 ps
CPU time 881.55 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 06:02:48 PM PDT 24
Peak memory 201484 kb
Host smart-42219ef1-ed41-4d5b-9ce9-1fbf30c220af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408683496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.408683496
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.533253858
Short name T681
Test name
Test status
Simulation time 488212711215 ps
CPU time 291.12 seconds
Started Aug 08 05:48:04 PM PDT 24
Finished Aug 08 05:52:56 PM PDT 24
Peak memory 201488 kb
Host smart-5b82733a-6bae-491a-98cb-12ad4b064e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533253858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.533253858
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1501227782
Short name T564
Test name
Test status
Simulation time 157899296994 ps
CPU time 79.99 seconds
Started Aug 08 05:48:05 PM PDT 24
Finished Aug 08 05:49:25 PM PDT 24
Peak memory 201532 kb
Host smart-caf42286-3b89-43a2-8248-99ad274799b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501227782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1501227782
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1560292694
Short name T463
Test name
Test status
Simulation time 159926314779 ps
CPU time 190.88 seconds
Started Aug 08 05:48:04 PM PDT 24
Finished Aug 08 05:51:15 PM PDT 24
Peak memory 201460 kb
Host smart-0813e90d-3dfa-4fb0-8c72-4595a907a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560292694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1560292694
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4173571652
Short name T659
Test name
Test status
Simulation time 165793199592 ps
CPU time 390.44 seconds
Started Aug 08 05:48:06 PM PDT 24
Finished Aug 08 05:54:36 PM PDT 24
Peak memory 201476 kb
Host smart-cde14102-d431-4cd3-abf2-4fd465d677f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173571652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4173571652
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2928681570
Short name T751
Test name
Test status
Simulation time 556885339103 ps
CPU time 314.1 seconds
Started Aug 08 05:48:07 PM PDT 24
Finished Aug 08 05:53:21 PM PDT 24
Peak memory 201424 kb
Host smart-6f07af77-881e-458c-87f6-04dce463a512
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928681570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2928681570
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4215925366
Short name T418
Test name
Test status
Simulation time 204399521274 ps
CPU time 252.88 seconds
Started Aug 08 05:48:06 PM PDT 24
Finished Aug 08 05:52:20 PM PDT 24
Peak memory 201408 kb
Host smart-cd7a830a-ef47-4518-8154-213f48efbb27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215925366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4215925366
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3127864291
Short name T349
Test name
Test status
Simulation time 93995686001 ps
CPU time 301.27 seconds
Started Aug 08 05:48:15 PM PDT 24
Finished Aug 08 05:53:16 PM PDT 24
Peak memory 201820 kb
Host smart-2b206f99-b076-4cc6-b435-c0a157884313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127864291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3127864291
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3217774829
Short name T34
Test name
Test status
Simulation time 28838298392 ps
CPU time 35.15 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 05:48:48 PM PDT 24
Peak memory 201352 kb
Host smart-e01cacf5-0814-4511-85ed-08a91afb6d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217774829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3217774829
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4093189072
Short name T475
Test name
Test status
Simulation time 2910264734 ps
CPU time 1.25 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 05:48:13 PM PDT 24
Peak memory 201392 kb
Host smart-89c6eba2-368c-460c-a679-d2c0af8477d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093189072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4093189072
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.707365685
Short name T125
Test name
Test status
Simulation time 5906628782 ps
CPU time 15.06 seconds
Started Aug 08 05:48:05 PM PDT 24
Finished Aug 08 05:48:20 PM PDT 24
Peak memory 201364 kb
Host smart-ed5b0a37-0019-494c-b90b-aa40b6c77a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707365685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.707365685
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.911844672
Short name T16
Test name
Test status
Simulation time 98758903179 ps
CPU time 301.92 seconds
Started Aug 08 05:48:16 PM PDT 24
Finished Aug 08 05:53:18 PM PDT 24
Peak memory 210168 kb
Host smart-dc7a6acb-4d22-4c6c-8930-594e61be8eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911844672 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.911844672
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4241294724
Short name T565
Test name
Test status
Simulation time 419406715 ps
CPU time 1.06 seconds
Started Aug 08 05:48:20 PM PDT 24
Finished Aug 08 05:48:21 PM PDT 24
Peak memory 201272 kb
Host smart-46c7fbef-d3de-4ddd-882b-70707781abc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241294724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4241294724
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2633336578
Short name T29
Test name
Test status
Simulation time 183817554510 ps
CPU time 414.66 seconds
Started Aug 08 05:48:20 PM PDT 24
Finished Aug 08 05:55:15 PM PDT 24
Peak memory 201444 kb
Host smart-ec1a3407-995f-4eaa-bd3b-54192c96f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633336578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2633336578
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2575813359
Short name T579
Test name
Test status
Simulation time 320293615537 ps
CPU time 765.64 seconds
Started Aug 08 05:48:13 PM PDT 24
Finished Aug 08 06:00:59 PM PDT 24
Peak memory 201388 kb
Host smart-357026f5-58ec-4666-a9f3-ce3522420b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575813359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2575813359
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.137397935
Short name T383
Test name
Test status
Simulation time 500901966326 ps
CPU time 1108.26 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 06:06:41 PM PDT 24
Peak memory 201456 kb
Host smart-b5a93934-fb41-48c9-a767-dd418880e406
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=137397935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.137397935
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3836881416
Short name T191
Test name
Test status
Simulation time 328101317329 ps
CPU time 191.78 seconds
Started Aug 08 05:48:15 PM PDT 24
Finished Aug 08 05:51:27 PM PDT 24
Peak memory 201444 kb
Host smart-0121cac1-f9cc-40ae-9dd4-087deb929a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836881416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3836881416
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4700514
Short name T59
Test name
Test status
Simulation time 491063117029 ps
CPU time 96.59 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 05:49:48 PM PDT 24
Peak memory 201428 kb
Host smart-3daa1762-1952-4623-a4a5-c09b9d6b2f2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4700514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.4700514
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2239125154
Short name T788
Test name
Test status
Simulation time 171197909761 ps
CPU time 90.46 seconds
Started Aug 08 05:48:14 PM PDT 24
Finished Aug 08 05:49:45 PM PDT 24
Peak memory 201448 kb
Host smart-3b6a1c1b-80c0-4be8-80e4-dad336c57cc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239125154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2239125154
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.850087521
Short name T745
Test name
Test status
Simulation time 384048151473 ps
CPU time 808.02 seconds
Started Aug 08 05:48:13 PM PDT 24
Finished Aug 08 06:01:41 PM PDT 24
Peak memory 201396 kb
Host smart-d008f5d9-4140-43ba-aaef-80aede07b338
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850087521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.850087521
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3030028372
Short name T47
Test name
Test status
Simulation time 113903804251 ps
CPU time 458.43 seconds
Started Aug 08 05:48:25 PM PDT 24
Finished Aug 08 05:56:04 PM PDT 24
Peak memory 201832 kb
Host smart-947019f1-2395-4c07-a0b5-c252af96a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030028372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3030028372
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2569998290
Short name T119
Test name
Test status
Simulation time 42493649512 ps
CPU time 26.12 seconds
Started Aug 08 05:48:20 PM PDT 24
Finished Aug 08 05:48:46 PM PDT 24
Peak memory 201216 kb
Host smart-fcaa91bb-05f5-46f5-94ec-19d83523d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569998290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2569998290
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1455604742
Short name T713
Test name
Test status
Simulation time 3237558641 ps
CPU time 2.55 seconds
Started Aug 08 05:48:19 PM PDT 24
Finished Aug 08 05:48:22 PM PDT 24
Peak memory 201292 kb
Host smart-32c5d3f9-85c6-42ad-a18e-14eed19a00d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455604742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1455604742
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.876687267
Short name T679
Test name
Test status
Simulation time 5864089021 ps
CPU time 15.13 seconds
Started Aug 08 05:48:12 PM PDT 24
Finished Aug 08 05:48:27 PM PDT 24
Peak memory 201248 kb
Host smart-ed8cec07-33d6-4bab-9826-ef02aa90ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876687267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.876687267
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1682674258
Short name T9
Test name
Test status
Simulation time 163379260211 ps
CPU time 95.35 seconds
Started Aug 08 05:48:19 PM PDT 24
Finished Aug 08 05:49:55 PM PDT 24
Peak memory 201480 kb
Host smart-6e3d5c8b-a7b8-4ca9-a01b-e5244fea1c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682674258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1682674258
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1406332608
Short name T744
Test name
Test status
Simulation time 19420453777 ps
CPU time 35.99 seconds
Started Aug 08 05:48:20 PM PDT 24
Finished Aug 08 05:48:56 PM PDT 24
Peak memory 209784 kb
Host smart-4fad345d-1351-4125-b230-7f142a3e883e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406332608 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1406332608
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3522378107
Short name T736
Test name
Test status
Simulation time 442880225 ps
CPU time 1.61 seconds
Started Aug 08 05:48:31 PM PDT 24
Finished Aug 08 05:48:32 PM PDT 24
Peak memory 201264 kb
Host smart-62c2d498-2fc4-41cb-b5a3-28982ddeee36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522378107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3522378107
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3758906228
Short name T171
Test name
Test status
Simulation time 173835901202 ps
CPU time 36.58 seconds
Started Aug 08 05:48:32 PM PDT 24
Finished Aug 08 05:49:09 PM PDT 24
Peak memory 201468 kb
Host smart-f8c539f8-aabc-4eb7-bbfc-63045e616c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758906228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3758906228
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1303837028
Short name T279
Test name
Test status
Simulation time 485165252597 ps
CPU time 1165.22 seconds
Started Aug 08 05:48:19 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 201368 kb
Host smart-2890b174-d643-41d0-ad95-5baba2dff949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303837028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1303837028
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1991388801
Short name T394
Test name
Test status
Simulation time 497742570211 ps
CPU time 382.04 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:54:52 PM PDT 24
Peak memory 201420 kb
Host smart-ab3c290d-a05f-4270-977e-f3f0e888ef03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991388801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1991388801
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.924459136
Short name T192
Test name
Test status
Simulation time 493592004085 ps
CPU time 253.37 seconds
Started Aug 08 05:48:19 PM PDT 24
Finished Aug 08 05:52:32 PM PDT 24
Peak memory 201436 kb
Host smart-67af82af-c09e-4e6f-9320-9e8752cb1138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924459136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.924459136
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.436526555
Short name T64
Test name
Test status
Simulation time 326112155546 ps
CPU time 173.18 seconds
Started Aug 08 05:48:21 PM PDT 24
Finished Aug 08 05:51:14 PM PDT 24
Peak memory 201380 kb
Host smart-a676ffde-2cce-4283-9c98-535af633f8e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=436526555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.436526555
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.889997804
Short name T317
Test name
Test status
Simulation time 167367692264 ps
CPU time 390.93 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:55:01 PM PDT 24
Peak memory 201460 kb
Host smart-7234a5d1-d8e4-4b26-97bf-1e4445b9aacf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889997804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.889997804
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3746185247
Short name T787
Test name
Test status
Simulation time 201334556958 ps
CPU time 496.44 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:56:46 PM PDT 24
Peak memory 201408 kb
Host smart-d268091c-f58a-419f-ad2a-09eb38be2571
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746185247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3746185247
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.944992018
Short name T758
Test name
Test status
Simulation time 101200811660 ps
CPU time 407.25 seconds
Started Aug 08 05:48:32 PM PDT 24
Finished Aug 08 05:55:19 PM PDT 24
Peak memory 201852 kb
Host smart-f8d95677-9cff-418e-8480-0a63196ffb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944992018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.944992018
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3458499250
Short name T549
Test name
Test status
Simulation time 34040273852 ps
CPU time 19.74 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:48:50 PM PDT 24
Peak memory 201360 kb
Host smart-020a8735-d533-4d0a-83e2-0cf309e0a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458499250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3458499250
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3315515967
Short name T714
Test name
Test status
Simulation time 3589965615 ps
CPU time 2.2 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:48:32 PM PDT 24
Peak memory 201344 kb
Host smart-4b8db0e5-3a5c-4db6-bac1-168168e67a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315515967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3315515967
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3873481306
Short name T52
Test name
Test status
Simulation time 5721921552 ps
CPU time 4.13 seconds
Started Aug 08 05:48:21 PM PDT 24
Finished Aug 08 05:48:25 PM PDT 24
Peak memory 201384 kb
Host smart-910f83c5-2bec-45ab-9d62-4d47b6c7cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873481306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3873481306
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2947342776
Short name T688
Test name
Test status
Simulation time 502399564622 ps
CPU time 350.47 seconds
Started Aug 08 05:48:29 PM PDT 24
Finished Aug 08 05:54:20 PM PDT 24
Peak memory 201496 kb
Host smart-b4c3606a-0099-41bb-846e-b578d4110808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947342776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2947342776
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1010234057
Short name T741
Test name
Test status
Simulation time 55111179965 ps
CPU time 148.83 seconds
Started Aug 08 05:48:30 PM PDT 24
Finished Aug 08 05:50:59 PM PDT 24
Peak memory 210104 kb
Host smart-cf8c0088-ded1-490c-974c-815006f620f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010234057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1010234057
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.715350354
Short name T513
Test name
Test status
Simulation time 419297319 ps
CPU time 0.68 seconds
Started Aug 08 05:48:41 PM PDT 24
Finished Aug 08 05:48:42 PM PDT 24
Peak memory 201188 kb
Host smart-2f4abc80-d190-4143-a721-6bd6961bf0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715350354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.715350354
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1522880280
Short name T334
Test name
Test status
Simulation time 339176118050 ps
CPU time 708.64 seconds
Started Aug 08 05:48:40 PM PDT 24
Finished Aug 08 06:00:29 PM PDT 24
Peak memory 201512 kb
Host smart-7c8b0cbe-d3a2-4511-ae80-0385b8330279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522880280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1522880280
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2295626246
Short name T712
Test name
Test status
Simulation time 490541632109 ps
CPU time 1117.47 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 06:07:17 PM PDT 24
Peak memory 201464 kb
Host smart-60428c1c-5847-41c1-a622-7b16e86b8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295626246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2295626246
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2676794063
Short name T761
Test name
Test status
Simulation time 166551080230 ps
CPU time 189.97 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:51:49 PM PDT 24
Peak memory 201464 kb
Host smart-a9c3e96a-fb96-45a3-8085-02e74f659d60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676794063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2676794063
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3008368750
Short name T628
Test name
Test status
Simulation time 333109640490 ps
CPU time 129.71 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:50:49 PM PDT 24
Peak memory 201436 kb
Host smart-3f4a5a6f-6633-4e0f-ae26-4fa8fb375846
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008368750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3008368750
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2477403652
Short name T649
Test name
Test status
Simulation time 554726211486 ps
CPU time 1336.19 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 06:10:56 PM PDT 24
Peak memory 201496 kb
Host smart-dea17cd6-bba5-4814-b36d-b41ee5ad6578
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477403652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2477403652
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2079881166
Short name T707
Test name
Test status
Simulation time 211168060353 ps
CPU time 123.32 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:50:43 PM PDT 24
Peak memory 201380 kb
Host smart-fcacc92e-f397-4a5d-969f-f1a737c9f0bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079881166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2079881166
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3048561788
Short name T425
Test name
Test status
Simulation time 23110318453 ps
CPU time 14.38 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:48:53 PM PDT 24
Peak memory 201360 kb
Host smart-04484ed5-284d-47d3-a13a-45a1a069248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048561788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3048561788
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2463271235
Short name T30
Test name
Test status
Simulation time 4665617537 ps
CPU time 12.15 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 05:48:51 PM PDT 24
Peak memory 201376 kb
Host smart-7090cd3e-48da-48d4-bdbc-869446de9330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463271235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2463271235
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1069415189
Short name T544
Test name
Test status
Simulation time 5880055382 ps
CPU time 4.2 seconds
Started Aug 08 05:48:31 PM PDT 24
Finished Aug 08 05:48:35 PM PDT 24
Peak memory 201372 kb
Host smart-3bae4bd0-4ee4-4997-8734-d4adddb44572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069415189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1069415189
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1375069571
Short name T510
Test name
Test status
Simulation time 617290896811 ps
CPU time 1505.54 seconds
Started Aug 08 05:48:39 PM PDT 24
Finished Aug 08 06:13:45 PM PDT 24
Peak memory 208476 kb
Host smart-259bf08b-f92f-4a56-87d1-3cd85fc1e5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375069571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1375069571
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2757991654
Short name T405
Test name
Test status
Simulation time 374843093 ps
CPU time 0.85 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:48:50 PM PDT 24
Peak memory 201272 kb
Host smart-451a213d-6571-44d8-8d73-5e2b97120fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757991654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2757991654
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.601123138
Short name T67
Test name
Test status
Simulation time 329490124771 ps
CPU time 611.53 seconds
Started Aug 08 05:48:50 PM PDT 24
Finished Aug 08 05:59:01 PM PDT 24
Peak memory 201464 kb
Host smart-16496c73-40ba-469e-b58d-871924e4504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601123138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.601123138
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3648460312
Short name T742
Test name
Test status
Simulation time 329350446955 ps
CPU time 377.36 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:55:06 PM PDT 24
Peak memory 201416 kb
Host smart-b340ded7-9493-4a39-9cc3-31ee77205df5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648460312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3648460312
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.13511811
Short name T295
Test name
Test status
Simulation time 329797431877 ps
CPU time 707.01 seconds
Started Aug 08 05:48:51 PM PDT 24
Finished Aug 08 06:00:38 PM PDT 24
Peak memory 201424 kb
Host smart-1f9d1a3e-cf45-4038-8190-87327a985064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13511811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.13511811
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3080366473
Short name T573
Test name
Test status
Simulation time 503686555384 ps
CPU time 1227.61 seconds
Started Aug 08 05:48:51 PM PDT 24
Finished Aug 08 06:09:19 PM PDT 24
Peak memory 201404 kb
Host smart-4dc7f7af-27aa-4d9f-b26d-d6077dc5c5fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080366473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3080366473
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.225389246
Short name T298
Test name
Test status
Simulation time 175777124780 ps
CPU time 101.38 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:50:31 PM PDT 24
Peak memory 201420 kb
Host smart-5bf86a70-4bc1-43f3-af8e-2ad5f4e287c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225389246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.225389246
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3249238504
Short name T675
Test name
Test status
Simulation time 403713718796 ps
CPU time 193.99 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:52:03 PM PDT 24
Peak memory 201468 kb
Host smart-afae3682-acc2-464f-8161-8bffd6d270d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249238504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3249238504
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.585555566
Short name T213
Test name
Test status
Simulation time 89866586333 ps
CPU time 400.44 seconds
Started Aug 08 05:48:47 PM PDT 24
Finished Aug 08 05:55:28 PM PDT 24
Peak memory 201852 kb
Host smart-c1e991d9-2fe8-4359-b4be-5a91fb99d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585555566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.585555566
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2043489269
Short name T696
Test name
Test status
Simulation time 23124022484 ps
CPU time 27.09 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:49:17 PM PDT 24
Peak memory 201280 kb
Host smart-0b4225a3-2c3b-4da7-a4d1-3be6fc99682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043489269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2043489269
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1833979772
Short name T423
Test name
Test status
Simulation time 5151787124 ps
CPU time 6.81 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:48:56 PM PDT 24
Peak memory 201360 kb
Host smart-0b2a4b27-3531-4ddf-b94a-36481bf978fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833979772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1833979772
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2475887929
Short name T587
Test name
Test status
Simulation time 5947313185 ps
CPU time 2.07 seconds
Started Aug 08 05:48:50 PM PDT 24
Finished Aug 08 05:48:52 PM PDT 24
Peak memory 201380 kb
Host smart-a0fdeb9a-16d6-4044-b938-525d3e94b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475887929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2475887929
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2917114960
Short name T57
Test name
Test status
Simulation time 295095823782 ps
CPU time 746.74 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 06:01:16 PM PDT 24
Peak memory 201868 kb
Host smart-3dd6a726-013e-4272-a1ef-aad9e69f350a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917114960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2917114960
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1868004779
Short name T743
Test name
Test status
Simulation time 21722952431 ps
CPU time 48.69 seconds
Started Aug 08 05:48:49 PM PDT 24
Finished Aug 08 05:49:38 PM PDT 24
Peak memory 209800 kb
Host smart-5de85eaf-5694-4a4e-b8c4-f1dc784b11b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868004779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1868004779
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1487024269
Short name T359
Test name
Test status
Simulation time 329743407 ps
CPU time 1.43 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:36 PM PDT 24
Peak memory 201236 kb
Host smart-721b2cf8-e191-442a-8c8e-cc1a649b0be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487024269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1487024269
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1896721270
Short name T772
Test name
Test status
Simulation time 514875704788 ps
CPU time 95.89 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:47:10 PM PDT 24
Peak memory 201416 kb
Host smart-2f0a38b5-d5ae-4275-aca9-7e57dc1aa79a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896721270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1896721270
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1904677481
Short name T159
Test name
Test status
Simulation time 491186355106 ps
CPU time 1162.3 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 201448 kb
Host smart-a5683ddf-f347-4477-8ddd-0fdb44892f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904677481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1904677481
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4060216480
Short name T532
Test name
Test status
Simulation time 329678537143 ps
CPU time 367.99 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:51:41 PM PDT 24
Peak memory 201476 kb
Host smart-134e645f-1c6d-4c80-9868-923b2ea28590
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060216480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4060216480
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2563712354
Short name T700
Test name
Test status
Simulation time 485794407467 ps
CPU time 547.3 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:54:41 PM PDT 24
Peak memory 201524 kb
Host smart-c0745457-7296-4da5-a284-3bd6af5a992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563712354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2563712354
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1782487794
Short name T630
Test name
Test status
Simulation time 486537200974 ps
CPU time 254.69 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:49:48 PM PDT 24
Peak memory 201456 kb
Host smart-c2c298f5-2bfb-4d19-b5e7-801895cbf1b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782487794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1782487794
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4072497159
Short name T691
Test name
Test status
Simulation time 174915528916 ps
CPU time 97.6 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:47:18 PM PDT 24
Peak memory 201380 kb
Host smart-46f428d0-c997-455f-937c-40dfa01e25d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072497159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4072497159
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2474197351
Short name T498
Test name
Test status
Simulation time 394360428451 ps
CPU time 231.21 seconds
Started Aug 08 05:45:26 PM PDT 24
Finished Aug 08 05:49:17 PM PDT 24
Peak memory 201456 kb
Host smart-35e4b296-0a8a-4c7b-850d-22d42fd4f49f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474197351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2474197351
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.481137224
Short name T432
Test name
Test status
Simulation time 131857716465 ps
CPU time 477.65 seconds
Started Aug 08 05:45:47 PM PDT 24
Finished Aug 08 05:53:45 PM PDT 24
Peak memory 201812 kb
Host smart-9eb3920a-7a20-463f-ae87-665423f46635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481137224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.481137224
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4131924084
Short name T402
Test name
Test status
Simulation time 42272636397 ps
CPU time 21.59 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:45:56 PM PDT 24
Peak memory 201352 kb
Host smart-7f95a031-8923-4b0a-b412-6410a3b68262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131924084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4131924084
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1094908090
Short name T636
Test name
Test status
Simulation time 4216797748 ps
CPU time 9.46 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:45:43 PM PDT 24
Peak memory 201276 kb
Host smart-512ebe83-4ec3-4d31-80fc-1a2f51a98058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094908090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1094908090
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3784753229
Short name T87
Test name
Test status
Simulation time 8530542150 ps
CPU time 5.34 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:45:42 PM PDT 24
Peak memory 218232 kb
Host smart-64e5b87e-9099-47ef-a927-24e9cbbc6c4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784753229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3784753229
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.534584750
Short name T584
Test name
Test status
Simulation time 6106591549 ps
CPU time 2.17 seconds
Started Aug 08 05:45:43 PM PDT 24
Finished Aug 08 05:45:45 PM PDT 24
Peak memory 201368 kb
Host smart-e0d1c850-af93-48c5-942d-f0a6ab3f5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534584750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.534584750
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.305318039
Short name T501
Test name
Test status
Simulation time 167369714222 ps
CPU time 44.24 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:46:18 PM PDT 24
Peak memory 201532 kb
Host smart-61e1f5ea-7014-4892-8962-521c3ce888ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305318039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.305318039
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1951724296
Short name T548
Test name
Test status
Simulation time 351372975 ps
CPU time 1.37 seconds
Started Aug 08 05:49:11 PM PDT 24
Finished Aug 08 05:49:13 PM PDT 24
Peak memory 201200 kb
Host smart-42593d52-9fe6-4491-b736-087b18ee42a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951724296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1951724296
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3918963102
Short name T538
Test name
Test status
Simulation time 164863416555 ps
CPU time 197.31 seconds
Started Aug 08 05:48:58 PM PDT 24
Finished Aug 08 05:52:16 PM PDT 24
Peak memory 201460 kb
Host smart-20d22e3c-af9b-4dbe-92dd-2755f893c925
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918963102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3918963102
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.201852734
Short name T519
Test name
Test status
Simulation time 160687749979 ps
CPU time 47.97 seconds
Started Aug 08 05:49:00 PM PDT 24
Finished Aug 08 05:49:49 PM PDT 24
Peak memory 201456 kb
Host smart-904c4f7c-56b4-4b9d-9606-e08ffad60a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201852734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.201852734
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.796461555
Short name T185
Test name
Test status
Simulation time 167066595012 ps
CPU time 77.61 seconds
Started Aug 08 05:48:59 PM PDT 24
Finished Aug 08 05:50:16 PM PDT 24
Peak memory 201460 kb
Host smart-86201da4-90e9-4e90-8d82-3427b320949a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=796461555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.796461555
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1158625198
Short name T315
Test name
Test status
Simulation time 488611359900 ps
CPU time 779.32 seconds
Started Aug 08 05:49:00 PM PDT 24
Finished Aug 08 06:01:59 PM PDT 24
Peak memory 201508 kb
Host smart-735c8dca-fc25-492f-b71f-81e22198fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158625198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1158625198
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4215329662
Short name T462
Test name
Test status
Simulation time 498232320124 ps
CPU time 1112.03 seconds
Started Aug 08 05:49:00 PM PDT 24
Finished Aug 08 06:07:33 PM PDT 24
Peak memory 201500 kb
Host smart-1a0a7f34-2f72-4977-ba66-3b0918fa7043
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215329662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4215329662
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.866589876
Short name T540
Test name
Test status
Simulation time 591235046201 ps
CPU time 302.68 seconds
Started Aug 08 05:48:58 PM PDT 24
Finished Aug 08 05:54:01 PM PDT 24
Peak memory 201380 kb
Host smart-e182c321-d92c-4763-a9f7-7df755e0a6bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866589876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.866589876
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3759594749
Short name T355
Test name
Test status
Simulation time 196358787720 ps
CPU time 456.55 seconds
Started Aug 08 05:48:59 PM PDT 24
Finished Aug 08 05:56:35 PM PDT 24
Peak memory 201444 kb
Host smart-a346a64c-d1cd-4fbe-b493-a525acadfce0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759594749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3759594749
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1772526863
Short name T608
Test name
Test status
Simulation time 106174157822 ps
CPU time 551.25 seconds
Started Aug 08 05:49:09 PM PDT 24
Finished Aug 08 05:58:21 PM PDT 24
Peak memory 201864 kb
Host smart-126bd730-ba9f-48c7-befb-5fbd29c5f8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772526863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1772526863
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2520619996
Short name T367
Test name
Test status
Simulation time 38457033217 ps
CPU time 87.51 seconds
Started Aug 08 05:49:00 PM PDT 24
Finished Aug 08 05:50:28 PM PDT 24
Peak memory 201392 kb
Host smart-d6306ed7-ea11-4e74-9a5c-49077c133f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520619996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2520619996
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1716812926
Short name T358
Test name
Test status
Simulation time 4489701808 ps
CPU time 3.17 seconds
Started Aug 08 05:48:58 PM PDT 24
Finished Aug 08 05:49:02 PM PDT 24
Peak memory 201344 kb
Host smart-4ef79901-c7ca-47e8-bcf0-76cc56f8346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716812926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1716812926
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3254013909
Short name T752
Test name
Test status
Simulation time 5923098059 ps
CPU time 13.74 seconds
Started Aug 08 05:48:59 PM PDT 24
Finished Aug 08 05:49:12 PM PDT 24
Peak memory 201380 kb
Host smart-880f9836-5927-4991-bcbd-e2da1003c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254013909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3254013909
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3775357500
Short name T605
Test name
Test status
Simulation time 1118140226 ps
CPU time 2.11 seconds
Started Aug 08 05:49:09 PM PDT 24
Finished Aug 08 05:49:11 PM PDT 24
Peak memory 201200 kb
Host smart-4223f2d7-3c9b-4be1-a000-de0aa3bc6562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775357500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3775357500
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3375085751
Short name T529
Test name
Test status
Simulation time 224099720261 ps
CPU time 55.05 seconds
Started Aug 08 05:49:09 PM PDT 24
Finished Aug 08 05:50:05 PM PDT 24
Peak memory 211036 kb
Host smart-108a8da2-2c4b-41fc-ae57-40039c23ed27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375085751 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3375085751
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2543027589
Short name T440
Test name
Test status
Simulation time 462623608 ps
CPU time 0.92 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:49:21 PM PDT 24
Peak memory 201272 kb
Host smart-affe2344-f27c-409e-bc89-8dc615d759f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543027589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2543027589
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3350243083
Short name T596
Test name
Test status
Simulation time 508908390289 ps
CPU time 1165.41 seconds
Started Aug 08 05:49:12 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 201436 kb
Host smart-6089a70a-e7bc-4c4a-862f-a43869af59d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350243083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3350243083
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2814672090
Short name T41
Test name
Test status
Simulation time 334762769365 ps
CPU time 396.16 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 05:55:46 PM PDT 24
Peak memory 201432 kb
Host smart-9c3e8531-d6d3-4300-8521-742f388559b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814672090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2814672090
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2857728130
Short name T178
Test name
Test status
Simulation time 484849515769 ps
CPU time 261.28 seconds
Started Aug 08 05:49:11 PM PDT 24
Finished Aug 08 05:53:32 PM PDT 24
Peak memory 201384 kb
Host smart-8adf483a-ef9d-4ece-aa2a-4e5a83e87e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857728130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2857728130
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3758859373
Short name T715
Test name
Test status
Simulation time 503160607051 ps
CPU time 1031.91 seconds
Started Aug 08 05:49:12 PM PDT 24
Finished Aug 08 06:06:24 PM PDT 24
Peak memory 201472 kb
Host smart-ab6fbe85-ef8e-40f9-a693-2c63eaac4366
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758859373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3758859373
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1080176909
Short name T44
Test name
Test status
Simulation time 550504925981 ps
CPU time 640.51 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 05:59:51 PM PDT 24
Peak memory 201464 kb
Host smart-0a8a798e-a776-4948-a8ed-86b7e0632163
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080176909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1080176909
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1801171953
Short name T678
Test name
Test status
Simulation time 394449933492 ps
CPU time 880.75 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 06:03:50 PM PDT 24
Peak memory 201468 kb
Host smart-3416f7a1-0ef5-4074-9f1b-9feeb91e4664
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801171953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1801171953
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3144583916
Short name T666
Test name
Test status
Simulation time 70613571509 ps
CPU time 228.52 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 05:52:58 PM PDT 24
Peak memory 201816 kb
Host smart-0c388db4-43b0-4342-bba5-210f79722c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144583916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3144583916
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1689178925
Short name T479
Test name
Test status
Simulation time 32448096031 ps
CPU time 17.87 seconds
Started Aug 08 05:49:09 PM PDT 24
Finished Aug 08 05:49:27 PM PDT 24
Peak memory 201380 kb
Host smart-056f2d4a-331f-4d14-b037-c6cd9012dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689178925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1689178925
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.256016326
Short name T690
Test name
Test status
Simulation time 3681683002 ps
CPU time 8.57 seconds
Started Aug 08 05:49:11 PM PDT 24
Finished Aug 08 05:49:20 PM PDT 24
Peak memory 201332 kb
Host smart-3e4a4904-637f-45c6-99c3-1e9b2248f225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256016326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.256016326
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3313637979
Short name T586
Test name
Test status
Simulation time 5698206657 ps
CPU time 15.65 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 05:49:25 PM PDT 24
Peak memory 201260 kb
Host smart-60a90014-b01a-4814-9172-1a597a68aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313637979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3313637979
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1329987433
Short name T332
Test name
Test status
Simulation time 662300917796 ps
CPU time 408.22 seconds
Started Aug 08 05:49:19 PM PDT 24
Finished Aug 08 05:56:08 PM PDT 24
Peak memory 201492 kb
Host smart-8ffb8acc-4409-4c56-88fd-cb1d3d61791f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329987433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1329987433
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3466940954
Short name T310
Test name
Test status
Simulation time 304008812673 ps
CPU time 207.43 seconds
Started Aug 08 05:49:10 PM PDT 24
Finished Aug 08 05:52:37 PM PDT 24
Peak memory 211204 kb
Host smart-997416cc-a8c4-4ae5-86fb-5b685fb5f458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466940954 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3466940954
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3860905382
Short name T574
Test name
Test status
Simulation time 423579904 ps
CPU time 0.9 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:49:32 PM PDT 24
Peak memory 201200 kb
Host smart-9b7d9169-0b0e-4ed0-b840-ddba7f28f4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860905382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3860905382
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.28522792
Short name T451
Test name
Test status
Simulation time 369800325625 ps
CPU time 486.49 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:57:27 PM PDT 24
Peak memory 201412 kb
Host smart-cefea3fc-7b8f-456e-9d32-63d0a27c06eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28522792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gatin
g.28522792
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1515043312
Short name T588
Test name
Test status
Simulation time 160048158051 ps
CPU time 185.61 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:52:26 PM PDT 24
Peak memory 201388 kb
Host smart-04b30039-caa4-4446-aaf8-0580ecac0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515043312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1515043312
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1552023024
Short name T316
Test name
Test status
Simulation time 330985106375 ps
CPU time 362.59 seconds
Started Aug 08 05:49:21 PM PDT 24
Finished Aug 08 05:55:24 PM PDT 24
Peak memory 201428 kb
Host smart-6f8164f6-509d-40e3-b3dc-14df01bca2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552023024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1552023024
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1756182789
Short name T395
Test name
Test status
Simulation time 167318177394 ps
CPU time 98.57 seconds
Started Aug 08 05:49:19 PM PDT 24
Finished Aug 08 05:50:58 PM PDT 24
Peak memory 201440 kb
Host smart-5f3606fb-7372-4eee-b7eb-a7eb765d30a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756182789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1756182789
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2868381446
Short name T603
Test name
Test status
Simulation time 166428807813 ps
CPU time 400.73 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:56:01 PM PDT 24
Peak memory 201432 kb
Host smart-58ed2701-6d2f-43da-90eb-d3a46ac314dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868381446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2868381446
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.900939577
Short name T644
Test name
Test status
Simulation time 337806571309 ps
CPU time 844.94 seconds
Started Aug 08 05:49:22 PM PDT 24
Finished Aug 08 06:03:27 PM PDT 24
Peak memory 201380 kb
Host smart-d124c021-47d0-4bc4-ade3-08e0ae357cde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=900939577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.900939577
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.400042127
Short name T702
Test name
Test status
Simulation time 270760539588 ps
CPU time 548.72 seconds
Started Aug 08 05:49:21 PM PDT 24
Finished Aug 08 05:58:29 PM PDT 24
Peak memory 201484 kb
Host smart-79db6783-58b0-4ff3-8052-ea6a30bf842d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400042127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.400042127
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2264325701
Short name T387
Test name
Test status
Simulation time 192651302831 ps
CPU time 412.74 seconds
Started Aug 08 05:49:21 PM PDT 24
Finished Aug 08 05:56:14 PM PDT 24
Peak memory 201380 kb
Host smart-0bca7652-3834-4866-90dd-9364cbd83bb0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264325701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2264325701
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2202648057
Short name T74
Test name
Test status
Simulation time 76279423627 ps
CPU time 334.2 seconds
Started Aug 08 05:49:18 PM PDT 24
Finished Aug 08 05:54:52 PM PDT 24
Peak memory 201848 kb
Host smart-44d7f2b0-e313-4272-b0ad-0d26f3ce7ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202648057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2202648057
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3405306862
Short name T685
Test name
Test status
Simulation time 45750725584 ps
CPU time 103.93 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:51:04 PM PDT 24
Peak memory 201260 kb
Host smart-ba9f3ecc-5e54-4dfc-93e2-c917b4559743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405306862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3405306862
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1961325302
Short name T56
Test name
Test status
Simulation time 3356395126 ps
CPU time 2.35 seconds
Started Aug 08 05:49:20 PM PDT 24
Finished Aug 08 05:49:22 PM PDT 24
Peak memory 201380 kb
Host smart-0a45357c-3165-4346-b8ed-e59d16d424c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961325302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1961325302
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2511359815
Short name T118
Test name
Test status
Simulation time 5963889719 ps
CPU time 3 seconds
Started Aug 08 05:49:22 PM PDT 24
Finished Aug 08 05:49:25 PM PDT 24
Peak memory 201428 kb
Host smart-90c554b2-1165-45b6-9c22-d726b120e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511359815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2511359815
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1652599649
Short name T525
Test name
Test status
Simulation time 278924144538 ps
CPU time 420.28 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:56:32 PM PDT 24
Peak memory 201844 kb
Host smart-370f1de7-38b3-48fc-91ed-47bd5ef6f5af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652599649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1652599649
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2579957117
Short name T148
Test name
Test status
Simulation time 61725245387 ps
CPU time 37.05 seconds
Started Aug 08 05:49:30 PM PDT 24
Finished Aug 08 05:50:07 PM PDT 24
Peak memory 210084 kb
Host smart-69890356-1d02-4600-80ac-4c2efa8c668d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579957117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2579957117
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2861775494
Short name T429
Test name
Test status
Simulation time 307312636 ps
CPU time 1.37 seconds
Started Aug 08 05:49:42 PM PDT 24
Finished Aug 08 05:49:44 PM PDT 24
Peak memory 201240 kb
Host smart-cde94e38-b37c-4d4f-9572-d760f9e9552f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861775494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2861775494
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.4150582662
Short name T340
Test name
Test status
Simulation time 172496849563 ps
CPU time 84.08 seconds
Started Aug 08 05:49:32 PM PDT 24
Finished Aug 08 05:50:56 PM PDT 24
Peak memory 201488 kb
Host smart-9ed51717-20f7-4e3c-a9b2-42c821300d56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150582662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.4150582662
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.79924407
Short name T746
Test name
Test status
Simulation time 500554099040 ps
CPU time 1092.71 seconds
Started Aug 08 05:49:30 PM PDT 24
Finished Aug 08 06:07:43 PM PDT 24
Peak memory 201416 kb
Host smart-8a4c9049-1132-4dcf-a604-8911b352e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79924407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.79924407
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1408403160
Short name T663
Test name
Test status
Simulation time 483860014958 ps
CPU time 542.29 seconds
Started Aug 08 05:49:30 PM PDT 24
Finished Aug 08 05:58:33 PM PDT 24
Peak memory 201524 kb
Host smart-5a748628-f4ef-473c-af00-97a032600750
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408403160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1408403160
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2913827019
Short name T342
Test name
Test status
Simulation time 163436336108 ps
CPU time 146 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:51:57 PM PDT 24
Peak memory 201444 kb
Host smart-cc6eeecc-bd35-4f4f-baca-3133a5d6b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913827019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2913827019
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3423592580
Short name T104
Test name
Test status
Simulation time 332272017628 ps
CPU time 334.1 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:55:05 PM PDT 24
Peak memory 201464 kb
Host smart-71690442-48b4-4459-8cc1-b5e543f0b026
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423592580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3423592580
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.406133744
Short name T563
Test name
Test status
Simulation time 594617229185 ps
CPU time 665.37 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 06:00:36 PM PDT 24
Peak memory 201328 kb
Host smart-7bb4e8c6-1ac8-4992-b1e8-1c107844cdaf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406133744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.406133744
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2746168905
Short name T211
Test name
Test status
Simulation time 68506694542 ps
CPU time 347.73 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:55:19 PM PDT 24
Peak memory 201832 kb
Host smart-06b3c909-d7b9-4e6c-af60-6befd755c707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746168905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2746168905
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3283664366
Short name T569
Test name
Test status
Simulation time 35510971473 ps
CPU time 23.06 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:49:54 PM PDT 24
Peak memory 201536 kb
Host smart-20f3a0e6-0720-46cc-b322-823958027ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283664366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3283664366
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3031088280
Short name T411
Test name
Test status
Simulation time 5148785968 ps
CPU time 3.5 seconds
Started Aug 08 05:49:30 PM PDT 24
Finished Aug 08 05:49:34 PM PDT 24
Peak memory 201308 kb
Host smart-f0ea09ef-5f04-42b6-a7a7-58f892a4ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031088280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3031088280
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2674176348
Short name T7
Test name
Test status
Simulation time 5780658435 ps
CPU time 13.72 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:49:44 PM PDT 24
Peak memory 201404 kb
Host smart-3376e23e-85d4-4957-9ea8-6f0a445d84a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674176348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2674176348
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3856150484
Short name T39
Test name
Test status
Simulation time 268122186791 ps
CPU time 414.06 seconds
Started Aug 08 05:49:32 PM PDT 24
Finished Aug 08 05:56:26 PM PDT 24
Peak memory 202000 kb
Host smart-5c342805-343b-4119-b2be-6729136bdb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856150484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3856150484
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3345520751
Short name T72
Test name
Test status
Simulation time 110641313457 ps
CPU time 245.42 seconds
Started Aug 08 05:49:31 PM PDT 24
Finished Aug 08 05:53:36 PM PDT 24
Peak memory 210144 kb
Host smart-03e72072-de06-4c7b-8796-4aa4040c17d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345520751 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3345520751
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2636393774
Short name T674
Test name
Test status
Simulation time 484453520 ps
CPU time 1.17 seconds
Started Aug 08 05:49:49 PM PDT 24
Finished Aug 08 05:49:50 PM PDT 24
Peak memory 201208 kb
Host smart-57a0efc0-239a-4756-80ad-b2e2bd213852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636393774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2636393774
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3102332711
Short name T283
Test name
Test status
Simulation time 163435755274 ps
CPU time 31.69 seconds
Started Aug 08 05:49:39 PM PDT 24
Finished Aug 08 05:50:10 PM PDT 24
Peak memory 201460 kb
Host smart-ee7c3432-833d-4722-9329-1a87856e3385
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102332711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3102332711
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.53880082
Short name T773
Test name
Test status
Simulation time 162828458114 ps
CPU time 349.97 seconds
Started Aug 08 05:49:39 PM PDT 24
Finished Aug 08 05:55:29 PM PDT 24
Peak memory 201472 kb
Host smart-b515c2cb-a305-47c8-b4fc-b1fea9de2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53880082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.53880082
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.873077836
Short name T600
Test name
Test status
Simulation time 329825321132 ps
CPU time 772.53 seconds
Started Aug 08 05:49:43 PM PDT 24
Finished Aug 08 06:02:35 PM PDT 24
Peak memory 201496 kb
Host smart-3c8d7842-a1d9-4dd8-8366-fce1e1e36092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873077836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.873077836
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.323745671
Short name T591
Test name
Test status
Simulation time 162507401826 ps
CPU time 96.71 seconds
Started Aug 08 05:49:42 PM PDT 24
Finished Aug 08 05:51:19 PM PDT 24
Peak memory 201452 kb
Host smart-34db4a36-2e9b-412c-9cdf-f7d730e51289
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=323745671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.323745671
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3139397339
Short name T795
Test name
Test status
Simulation time 481925372066 ps
CPU time 1093.69 seconds
Started Aug 08 05:49:40 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 201520 kb
Host smart-072d0f70-7d73-4878-9f98-0deb7148f234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139397339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3139397339
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1450067846
Short name T398
Test name
Test status
Simulation time 490662495096 ps
CPU time 196.97 seconds
Started Aug 08 05:49:40 PM PDT 24
Finished Aug 08 05:52:57 PM PDT 24
Peak memory 201412 kb
Host smart-8a96ab45-e13d-45b6-8d2c-0dfe123e6795
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450067846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1450067846
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3173669872
Short name T589
Test name
Test status
Simulation time 360923541200 ps
CPU time 867.04 seconds
Started Aug 08 05:49:40 PM PDT 24
Finished Aug 08 06:04:07 PM PDT 24
Peak memory 201428 kb
Host smart-60a5a39d-4431-4921-a8e6-729f35932d60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173669872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3173669872
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1045571879
Short name T667
Test name
Test status
Simulation time 404516156652 ps
CPU time 226.38 seconds
Started Aug 08 05:49:43 PM PDT 24
Finished Aug 08 05:53:29 PM PDT 24
Peak memory 201444 kb
Host smart-39e28a78-0f47-444b-b0bd-b31b5bb30831
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045571879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1045571879
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.360064540
Short name T556
Test name
Test status
Simulation time 86644198341 ps
CPU time 473.55 seconds
Started Aug 08 05:49:49 PM PDT 24
Finished Aug 08 05:57:43 PM PDT 24
Peak memory 201860 kb
Host smart-9cbef4ab-eb16-4939-8d0a-8419536bc120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360064540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.360064540
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3009529329
Short name T442
Test name
Test status
Simulation time 42167665069 ps
CPU time 6.68 seconds
Started Aug 08 05:49:39 PM PDT 24
Finished Aug 08 05:49:46 PM PDT 24
Peak memory 201280 kb
Host smart-6ebb0915-d5ca-44a7-b164-19c997d6cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009529329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3009529329
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2938037358
Short name T562
Test name
Test status
Simulation time 3726200282 ps
CPU time 4.25 seconds
Started Aug 08 05:49:38 PM PDT 24
Finished Aug 08 05:49:43 PM PDT 24
Peak memory 201344 kb
Host smart-27816027-5da3-447e-aba0-6ad9adf378b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938037358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2938037358
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4063361895
Short name T683
Test name
Test status
Simulation time 5758211246 ps
CPU time 14.67 seconds
Started Aug 08 05:49:41 PM PDT 24
Finished Aug 08 05:49:56 PM PDT 24
Peak memory 201340 kb
Host smart-6b1133c5-d94c-49ea-b4fa-00e4f3287185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063361895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4063361895
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2719834296
Short name T598
Test name
Test status
Simulation time 433840707 ps
CPU time 1.03 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:50:00 PM PDT 24
Peak memory 201200 kb
Host smart-9f6d5752-9692-49fc-b14e-01b3e4ab88b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719834296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2719834296
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2911073031
Short name T180
Test name
Test status
Simulation time 333815995886 ps
CPU time 62.64 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:51:02 PM PDT 24
Peak memory 201512 kb
Host smart-966cb4e0-6812-4ba8-8c29-3de3de387ae7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911073031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2911073031
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.380006899
Short name T254
Test name
Test status
Simulation time 524468736372 ps
CPU time 339.33 seconds
Started Aug 08 05:49:57 PM PDT 24
Finished Aug 08 05:55:36 PM PDT 24
Peak memory 201480 kb
Host smart-f28d0933-f12c-464b-bf7a-51e40134c845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380006899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.380006899
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.665042085
Short name T252
Test name
Test status
Simulation time 507754005079 ps
CPU time 290.27 seconds
Started Aug 08 05:49:48 PM PDT 24
Finished Aug 08 05:54:38 PM PDT 24
Peak memory 201472 kb
Host smart-a2f1294c-120b-4c4a-9e8c-dd4ab412c534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665042085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.665042085
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3191875751
Short name T464
Test name
Test status
Simulation time 487379746691 ps
CPU time 313.14 seconds
Started Aug 08 05:49:47 PM PDT 24
Finished Aug 08 05:55:00 PM PDT 24
Peak memory 201692 kb
Host smart-e2bdb87f-2da2-4202-9492-b974395dba1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191875751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3191875751
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4154783231
Short name T281
Test name
Test status
Simulation time 162100137214 ps
CPU time 36.14 seconds
Started Aug 08 05:49:48 PM PDT 24
Finished Aug 08 05:50:25 PM PDT 24
Peak memory 201468 kb
Host smart-e5db9433-596f-4213-b5aa-50e7fcb3e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154783231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4154783231
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2534051856
Short name T530
Test name
Test status
Simulation time 162702173703 ps
CPU time 381.43 seconds
Started Aug 08 05:49:51 PM PDT 24
Finished Aug 08 05:56:13 PM PDT 24
Peak memory 201400 kb
Host smart-f6461ced-86c7-403d-9d90-f803f5dd6876
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534051856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2534051856
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2957428264
Short name T250
Test name
Test status
Simulation time 546268637003 ps
CPU time 330.55 seconds
Started Aug 08 05:49:52 PM PDT 24
Finished Aug 08 05:55:22 PM PDT 24
Peak memory 201396 kb
Host smart-4f748ec5-1549-4937-a2a2-2498c8cc213b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957428264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2957428264
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4112124247
Short name T662
Test name
Test status
Simulation time 609128025487 ps
CPU time 317.67 seconds
Started Aug 08 05:49:52 PM PDT 24
Finished Aug 08 05:55:10 PM PDT 24
Peak memory 201444 kb
Host smart-b78a6096-2a53-479d-9ea5-15ea3d958cf9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112124247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4112124247
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1917799142
Short name T737
Test name
Test status
Simulation time 90038578107 ps
CPU time 336.52 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:55:35 PM PDT 24
Peak memory 201848 kb
Host smart-c3cea027-b464-4499-ad7f-d851ccca918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917799142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1917799142
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.497984266
Short name T488
Test name
Test status
Simulation time 36060290022 ps
CPU time 41.01 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:50:39 PM PDT 24
Peak memory 201344 kb
Host smart-be2cfac5-0ddc-4380-8073-033dafcc8a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497984266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.497984266
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.603795497
Short name T771
Test name
Test status
Simulation time 5170595017 ps
CPU time 3.76 seconds
Started Aug 08 05:50:01 PM PDT 24
Finished Aug 08 05:50:05 PM PDT 24
Peak memory 201352 kb
Host smart-8a3cabc7-21fc-453c-bc0f-8a06ab4126ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603795497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.603795497
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1761183750
Short name T468
Test name
Test status
Simulation time 6093126485 ps
CPU time 15.45 seconds
Started Aug 08 05:49:52 PM PDT 24
Finished Aug 08 05:50:08 PM PDT 24
Peak memory 201352 kb
Host smart-35832bf0-52f8-4d49-97bc-887ff85b5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761183750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1761183750
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2241182225
Short name T637
Test name
Test status
Simulation time 340860154955 ps
CPU time 661.06 seconds
Started Aug 08 05:49:57 PM PDT 24
Finished Aug 08 06:00:58 PM PDT 24
Peak memory 201432 kb
Host smart-0ee5760c-34e6-4cd1-b17b-4a1b34e5c34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241182225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2241182225
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.266606307
Short name T18
Test name
Test status
Simulation time 76795796724 ps
CPU time 168.68 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:52:47 PM PDT 24
Peak memory 217664 kb
Host smart-aed102c1-eff8-492c-98aa-d5c58cd23b2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266606307 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.266606307
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1921190441
Short name T446
Test name
Test status
Simulation time 325704781 ps
CPU time 0.95 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:50:00 PM PDT 24
Peak memory 201232 kb
Host smart-e8ec3a26-1660-4bfb-9d0b-0ded05944870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921190441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1921190441
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2030244258
Short name T755
Test name
Test status
Simulation time 187632239202 ps
CPU time 365.26 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:56:04 PM PDT 24
Peak memory 201416 kb
Host smart-23d11ddc-83fd-4874-85f2-baaaa693661c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030244258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2030244258
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3219049504
Short name T172
Test name
Test status
Simulation time 173724198492 ps
CPU time 150.34 seconds
Started Aug 08 05:50:02 PM PDT 24
Finished Aug 08 05:52:32 PM PDT 24
Peak memory 201400 kb
Host smart-4961f97f-a530-4e2c-be99-8dba52043b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219049504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3219049504
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1360673231
Short name T633
Test name
Test status
Simulation time 330423978468 ps
CPU time 699.93 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 06:01:38 PM PDT 24
Peak memory 201488 kb
Host smart-2a236d29-2237-489c-b55b-be3b49fa3e04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360673231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1360673231
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3032586324
Short name T789
Test name
Test status
Simulation time 338232807014 ps
CPU time 42.7 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:50:42 PM PDT 24
Peak memory 201416 kb
Host smart-cd493e4a-a43f-4041-b55c-ca54be1c7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032586324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3032586324
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2576383546
Short name T547
Test name
Test status
Simulation time 323634796664 ps
CPU time 723.34 seconds
Started Aug 08 05:49:57 PM PDT 24
Finished Aug 08 06:02:00 PM PDT 24
Peak memory 201472 kb
Host smart-52a301a4-2d96-4a96-b21b-b3484eb5ff2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576383546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2576383546
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1750170785
Short name T193
Test name
Test status
Simulation time 376522133776 ps
CPU time 183.76 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:53:02 PM PDT 24
Peak memory 201368 kb
Host smart-0719853d-c4dc-4d68-92bc-b510db7473c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750170785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1750170785
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1795057261
Short name T703
Test name
Test status
Simulation time 592751460423 ps
CPU time 233.58 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:53:53 PM PDT 24
Peak memory 201428 kb
Host smart-4fdfad59-e08d-4372-8656-b6914acaa306
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795057261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1795057261
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3603706559
Short name T632
Test name
Test status
Simulation time 117205663245 ps
CPU time 425.51 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:57:04 PM PDT 24
Peak memory 201772 kb
Host smart-c1aa29c1-f99d-41bd-8b73-317e6276b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603706559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3603706559
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3689609919
Short name T655
Test name
Test status
Simulation time 35019892556 ps
CPU time 77.17 seconds
Started Aug 08 05:50:00 PM PDT 24
Finished Aug 08 05:51:18 PM PDT 24
Peak memory 201336 kb
Host smart-4a0ef8e0-c44f-472c-a57b-a21b75d71994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689609919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3689609919
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1429285467
Short name T677
Test name
Test status
Simulation time 4354843325 ps
CPU time 3.41 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:50:01 PM PDT 24
Peak memory 201336 kb
Host smart-fe11deaf-de92-4cf4-8e5d-9dea22c17aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429285467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1429285467
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3983650360
Short name T391
Test name
Test status
Simulation time 5790517902 ps
CPU time 4.13 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:50:03 PM PDT 24
Peak memory 201388 kb
Host smart-7e5c9f53-4155-4f76-9a7a-b52a1d5444fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983650360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3983650360
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1798566098
Short name T222
Test name
Test status
Simulation time 497444033174 ps
CPU time 301.38 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:54:59 PM PDT 24
Peak memory 201416 kb
Host smart-c4b0bf5a-60f6-4578-af36-6a76ac4e5622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798566098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1798566098
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4091844658
Short name T673
Test name
Test status
Simulation time 411962199 ps
CPU time 1.58 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 05:50:10 PM PDT 24
Peak memory 201260 kb
Host smart-546f91ec-cdfc-4183-9ef4-44f1e699b5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091844658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4091844658
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2136248115
Short name T155
Test name
Test status
Simulation time 161386427437 ps
CPU time 86.27 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 05:51:34 PM PDT 24
Peak memory 201444 kb
Host smart-b32ad4f4-5953-47a8-9670-90696c19a0c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136248115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2136248115
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4208128342
Short name T308
Test name
Test status
Simulation time 162711962763 ps
CPU time 193.14 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 05:53:21 PM PDT 24
Peak memory 201476 kb
Host smart-eb719327-aefb-4762-9bc2-3d31275125fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208128342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4208128342
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.519317067
Short name T149
Test name
Test status
Simulation time 493910584198 ps
CPU time 178.61 seconds
Started Aug 08 05:50:02 PM PDT 24
Finished Aug 08 05:53:00 PM PDT 24
Peak memory 201400 kb
Host smart-ad7397db-6acb-4211-97a2-5522092fa6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519317067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.519317067
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2512260772
Short name T716
Test name
Test status
Simulation time 326307159465 ps
CPU time 53.97 seconds
Started Aug 08 05:50:11 PM PDT 24
Finished Aug 08 05:51:05 PM PDT 24
Peak memory 201468 kb
Host smart-0f8df667-6956-431b-a16c-1c73327c0d49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512260772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2512260772
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3134456957
Short name T494
Test name
Test status
Simulation time 160874476142 ps
CPU time 370.33 seconds
Started Aug 08 05:49:59 PM PDT 24
Finished Aug 08 05:56:10 PM PDT 24
Peak memory 201440 kb
Host smart-f73fbeb7-add1-4d2a-b9a1-edc7051d7379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134456957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3134456957
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.616912822
Short name T634
Test name
Test status
Simulation time 167659007155 ps
CPU time 384.34 seconds
Started Aug 08 05:49:57 PM PDT 24
Finished Aug 08 05:56:21 PM PDT 24
Peak memory 201472 kb
Host smart-3b96f4a5-1fee-429d-83a6-bd10a862c187
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=616912822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.616912822
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.405992976
Short name T65
Test name
Test status
Simulation time 378750786626 ps
CPU time 822.22 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 06:03:51 PM PDT 24
Peak memory 201544 kb
Host smart-b23d7343-99df-4e75-8cd5-9e1d59c4c633
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405992976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.405992976
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1642229129
Short name T782
Test name
Test status
Simulation time 603457704761 ps
CPU time 1186.54 seconds
Started Aug 08 05:50:10 PM PDT 24
Finished Aug 08 06:09:56 PM PDT 24
Peak memory 201468 kb
Host smart-1c56a8db-fb7d-4ec5-81da-b2c849f5aa3b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642229129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1642229129
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1970797705
Short name T790
Test name
Test status
Simulation time 116240432478 ps
CPU time 319.48 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 05:55:28 PM PDT 24
Peak memory 201676 kb
Host smart-0450fa75-7b96-4588-9f30-af948dea5c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970797705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1970797705
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2328825060
Short name T354
Test name
Test status
Simulation time 41975694363 ps
CPU time 15.23 seconds
Started Aug 08 05:50:10 PM PDT 24
Finished Aug 08 05:50:25 PM PDT 24
Peak memory 201360 kb
Host smart-4c416db8-8f4e-4243-bbd7-40d6bcc02363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328825060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2328825060
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3724650623
Short name T669
Test name
Test status
Simulation time 3645414697 ps
CPU time 1.13 seconds
Started Aug 08 05:50:08 PM PDT 24
Finished Aug 08 05:50:09 PM PDT 24
Peak memory 201364 kb
Host smart-a629c5cb-60ce-401e-8358-b67e28658ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724650623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3724650623
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1921840558
Short name T699
Test name
Test status
Simulation time 5765293459 ps
CPU time 3.95 seconds
Started Aug 08 05:49:58 PM PDT 24
Finished Aug 08 05:50:02 PM PDT 24
Peak memory 201380 kb
Host smart-06cb0abc-de3b-42ed-9835-abc8aa38b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921840558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1921840558
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1317478686
Short name T297
Test name
Test status
Simulation time 1131294022211 ps
CPU time 164.78 seconds
Started Aug 08 05:50:09 PM PDT 24
Finished Aug 08 05:52:54 PM PDT 24
Peak memory 209880 kb
Host smart-b925f628-4f95-4b0f-b6e8-b4aeb254435b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317478686 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1317478686
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.658500560
Short name T739
Test name
Test status
Simulation time 324635002 ps
CPU time 1.05 seconds
Started Aug 08 05:50:23 PM PDT 24
Finished Aug 08 05:50:24 PM PDT 24
Peak memory 201212 kb
Host smart-d124351d-8b8d-491c-baa8-d3e89f12ea4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658500560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.658500560
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4202167441
Short name T223
Test name
Test status
Simulation time 171864648888 ps
CPU time 101.48 seconds
Started Aug 08 05:50:18 PM PDT 24
Finished Aug 08 05:52:00 PM PDT 24
Peak memory 201392 kb
Host smart-2fc45638-c903-4e52-ac21-c38ee37b2962
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202167441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4202167441
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2209128175
Short name T176
Test name
Test status
Simulation time 528489194007 ps
CPU time 120.69 seconds
Started Aug 08 05:50:19 PM PDT 24
Finished Aug 08 05:52:20 PM PDT 24
Peak memory 201420 kb
Host smart-34225acf-a3a4-4716-bfbb-b59667185392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209128175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2209128175
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.153971224
Short name T626
Test name
Test status
Simulation time 329637537374 ps
CPU time 191.2 seconds
Started Aug 08 05:50:18 PM PDT 24
Finished Aug 08 05:53:29 PM PDT 24
Peak memory 201476 kb
Host smart-e2f48e8b-d49d-404c-8863-f1427952c292
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=153971224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.153971224
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4279352180
Short name T403
Test name
Test status
Simulation time 338332011879 ps
CPU time 822.17 seconds
Started Aug 08 05:50:09 PM PDT 24
Finished Aug 08 06:03:51 PM PDT 24
Peak memory 201480 kb
Host smart-ccee157d-3925-49f7-8192-bbce8908aac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279352180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4279352180
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4080806602
Short name T393
Test name
Test status
Simulation time 329186904544 ps
CPU time 783.96 seconds
Started Aug 08 05:50:10 PM PDT 24
Finished Aug 08 06:03:14 PM PDT 24
Peak memory 201448 kb
Host smart-1362215c-f83e-44c8-a62c-cc6302f7d9d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080806602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4080806602
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1173051433
Short name T246
Test name
Test status
Simulation time 407168964850 ps
CPU time 988.74 seconds
Started Aug 08 05:50:19 PM PDT 24
Finished Aug 08 06:06:48 PM PDT 24
Peak memory 201460 kb
Host smart-4a457a40-273e-411a-a89d-bcfead5e039d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173051433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1173051433
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4088081020
Short name T708
Test name
Test status
Simulation time 408135406791 ps
CPU time 229.85 seconds
Started Aug 08 05:50:23 PM PDT 24
Finished Aug 08 05:54:13 PM PDT 24
Peak memory 201452 kb
Host smart-3e26585d-a368-4350-9168-fa82d1b4bc91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088081020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4088081020
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2625914054
Short name T71
Test name
Test status
Simulation time 74547482716 ps
CPU time 410.03 seconds
Started Aug 08 05:50:19 PM PDT 24
Finished Aug 08 05:57:09 PM PDT 24
Peak memory 201848 kb
Host smart-fd9cd171-61f6-420e-849b-c58e27e9640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625914054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2625914054
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3350947579
Short name T490
Test name
Test status
Simulation time 26708782976 ps
CPU time 61.78 seconds
Started Aug 08 05:50:18 PM PDT 24
Finished Aug 08 05:51:20 PM PDT 24
Peak memory 201376 kb
Host smart-a870ba12-4981-46ce-b24e-ffb0677c5d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350947579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3350947579
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3817618877
Short name T592
Test name
Test status
Simulation time 4904206293 ps
CPU time 6.18 seconds
Started Aug 08 05:50:18 PM PDT 24
Finished Aug 08 05:50:25 PM PDT 24
Peak memory 201364 kb
Host smart-0bc19e2f-d2f2-47c8-b6a1-79a03f3c5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817618877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3817618877
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2758999315
Short name T400
Test name
Test status
Simulation time 5795680195 ps
CPU time 4.48 seconds
Started Aug 08 05:50:11 PM PDT 24
Finished Aug 08 05:50:15 PM PDT 24
Peak memory 201328 kb
Host smart-faa2531f-8941-44e1-a5c2-246f740f506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758999315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2758999315
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2638850966
Short name T560
Test name
Test status
Simulation time 478486003 ps
CPU time 1.02 seconds
Started Aug 08 05:50:26 PM PDT 24
Finished Aug 08 05:50:27 PM PDT 24
Peak memory 201240 kb
Host smart-921ba328-8aff-43c1-bbf8-a9449f3ecd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638850966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2638850966
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3569008961
Short name T760
Test name
Test status
Simulation time 175612833200 ps
CPU time 130.42 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:52:37 PM PDT 24
Peak memory 201460 kb
Host smart-2a9efaf1-f334-4c2f-a33a-bbb6f1b624e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569008961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3569008961
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.542063294
Short name T199
Test name
Test status
Simulation time 324516959865 ps
CPU time 182.7 seconds
Started Aug 08 05:50:29 PM PDT 24
Finished Aug 08 05:53:31 PM PDT 24
Peak memory 201476 kb
Host smart-ca760c67-d7e5-44b7-83b4-adf0e2263df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542063294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.542063294
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3030637836
Short name T194
Test name
Test status
Simulation time 330527368687 ps
CPU time 206.85 seconds
Started Aug 08 05:50:25 PM PDT 24
Finished Aug 08 05:53:52 PM PDT 24
Peak memory 201512 kb
Host smart-0fc3656d-9dd0-4864-8105-e8634d98d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030637836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3030637836
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4294849412
Short name T377
Test name
Test status
Simulation time 168067205502 ps
CPU time 100.84 seconds
Started Aug 08 05:50:26 PM PDT 24
Finished Aug 08 05:52:07 PM PDT 24
Peak memory 201444 kb
Host smart-54bb5025-a90f-4d0a-a576-2d437f958037
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294849412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4294849412
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2132023698
Short name T493
Test name
Test status
Simulation time 499004890640 ps
CPU time 300.79 seconds
Started Aug 08 05:50:26 PM PDT 24
Finished Aug 08 05:55:27 PM PDT 24
Peak memory 201384 kb
Host smart-cbd92187-9d9f-40d4-83b5-a96a5bf736b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132023698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2132023698
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1492740815
Short name T28
Test name
Test status
Simulation time 166476759976 ps
CPU time 199.7 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:53:47 PM PDT 24
Peak memory 201364 kb
Host smart-29ceb005-5160-47b5-823f-dae860a25368
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492740815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1492740815
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4276783723
Short name T486
Test name
Test status
Simulation time 164092041549 ps
CPU time 371.05 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:56:38 PM PDT 24
Peak memory 201480 kb
Host smart-66a168a0-9d4e-42c9-bd90-32e3e617198e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276783723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4276783723
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.914282827
Short name T792
Test name
Test status
Simulation time 199723032119 ps
CPU time 166.75 seconds
Started Aug 08 05:50:29 PM PDT 24
Finished Aug 08 05:53:16 PM PDT 24
Peak memory 201420 kb
Host smart-161676d5-3791-4171-8ebf-1cbaed9f184f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914282827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.914282827
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1482893135
Short name T220
Test name
Test status
Simulation time 101847777344 ps
CPU time 357.52 seconds
Started Aug 08 05:50:26 PM PDT 24
Finished Aug 08 05:56:24 PM PDT 24
Peak memory 201860 kb
Host smart-8ebace16-e722-4827-9c32-4a031ecea672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482893135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1482893135
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.632830211
Short name T698
Test name
Test status
Simulation time 43755207951 ps
CPU time 89.95 seconds
Started Aug 08 05:50:26 PM PDT 24
Finished Aug 08 05:51:56 PM PDT 24
Peak memory 201384 kb
Host smart-06636e0b-3bbe-4e74-b063-c1d92e90960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632830211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.632830211
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2247432919
Short name T568
Test name
Test status
Simulation time 3874238715 ps
CPU time 8.58 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:50:36 PM PDT 24
Peak memory 201236 kb
Host smart-ac85ce61-7d1e-4ce5-8cf6-7be425c9c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247432919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2247432919
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3671108933
Short name T796
Test name
Test status
Simulation time 5967825830 ps
CPU time 7.69 seconds
Started Aug 08 05:50:27 PM PDT 24
Finished Aug 08 05:50:35 PM PDT 24
Peak memory 201404 kb
Host smart-b0fe434a-53bb-43be-b7e7-4ed288d2d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671108933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3671108933
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2886400860
Short name T388
Test name
Test status
Simulation time 347143409 ps
CPU time 0.85 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:36 PM PDT 24
Peak memory 201236 kb
Host smart-4f68ac47-8454-4d63-bd6b-300a713ebe0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886400860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2886400860
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.871357482
Short name T785
Test name
Test status
Simulation time 433292991310 ps
CPU time 63.39 seconds
Started Aug 08 05:45:41 PM PDT 24
Finished Aug 08 05:46:44 PM PDT 24
Peak memory 201436 kb
Host smart-895b4ca0-f5e5-4c48-8872-7ec868353a32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871357482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.871357482
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2379480509
Short name T284
Test name
Test status
Simulation time 161025155106 ps
CPU time 360.65 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:51:45 PM PDT 24
Peak memory 201436 kb
Host smart-5f89f20c-d089-494a-99af-7da7ca76a41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379480509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2379480509
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2550767730
Short name T452
Test name
Test status
Simulation time 493717939921 ps
CPU time 1102.83 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 06:03:59 PM PDT 24
Peak memory 201500 kb
Host smart-ab5f86ba-bd3f-4c0a-b683-0b5840100a5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550767730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2550767730
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3041364505
Short name T583
Test name
Test status
Simulation time 161085632359 ps
CPU time 95.84 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 05:47:12 PM PDT 24
Peak memory 201428 kb
Host smart-aa8b0cb0-4978-41ff-909c-ba0b40ad2e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041364505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3041364505
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.750527162
Short name T536
Test name
Test status
Simulation time 503297372559 ps
CPU time 87.97 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:47:12 PM PDT 24
Peak memory 201512 kb
Host smart-779dd670-2237-46de-9a93-68e9ac9f5aba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=750527162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.750527162
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1558413890
Short name T306
Test name
Test status
Simulation time 537062968026 ps
CPU time 1192.23 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 201364 kb
Host smart-497c7fa7-bc55-4b47-8145-fe1278e2be7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558413890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1558413890
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2459850325
Short name T375
Test name
Test status
Simulation time 599742689679 ps
CPU time 1303.09 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 06:07:18 PM PDT 24
Peak memory 201404 kb
Host smart-3542a915-42be-4818-a15b-09cdaebcaa26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459850325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2459850325
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2745926743
Short name T53
Test name
Test status
Simulation time 84397255914 ps
CPU time 470.14 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:53:28 PM PDT 24
Peak memory 201916 kb
Host smart-556906e3-0e75-4dbe-9c0d-e78a381bc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745926743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2745926743
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2014757939
Short name T652
Test name
Test status
Simulation time 27878849155 ps
CPU time 68.4 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:46:52 PM PDT 24
Peak memory 201400 kb
Host smart-d8610317-82e9-44a7-8405-d43dae672fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014757939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2014757939
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2179649383
Short name T109
Test name
Test status
Simulation time 3964068405 ps
CPU time 9.07 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:45:47 PM PDT 24
Peak memory 201280 kb
Host smart-28fdb84a-a24a-41bb-afa9-d80fec244ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179649383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2179649383
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1037710623
Short name T427
Test name
Test status
Simulation time 6061300623 ps
CPU time 4.73 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:45:49 PM PDT 24
Peak memory 201344 kb
Host smart-0d2c0469-34d3-412f-a05d-69ca30fa0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037710623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1037710623
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2011652510
Short name T12
Test name
Test status
Simulation time 177385648999 ps
CPU time 407.83 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:52:26 PM PDT 24
Peak memory 201492 kb
Host smart-13accc2e-96d7-4610-88d1-84ccba59619f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011652510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2011652510
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.893806835
Short name T25
Test name
Test status
Simulation time 56620416100 ps
CPU time 70.33 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:46:45 PM PDT 24
Peak memory 210120 kb
Host smart-5d2a6e25-0ab8-465c-af4d-47871a003f41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893806835 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.893806835
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3653970521
Short name T622
Test name
Test status
Simulation time 470398064 ps
CPU time 1.65 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:37 PM PDT 24
Peak memory 201236 kb
Host smart-0c95c43f-ac0a-4924-8918-a017ff0a2ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653970521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3653970521
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1467101425
Short name T236
Test name
Test status
Simulation time 167956890568 ps
CPU time 103.95 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:47:18 PM PDT 24
Peak memory 201644 kb
Host smart-2c0837ca-6260-48b3-91b3-6d247834e9d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467101425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1467101425
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3368219412
Short name T231
Test name
Test status
Simulation time 243549295252 ps
CPU time 529.74 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:54:38 PM PDT 24
Peak memory 201516 kb
Host smart-4f0d8084-e2bd-4f70-bcb2-52e75ae86007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368219412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3368219412
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.78816980
Short name T621
Test name
Test status
Simulation time 325490360784 ps
CPU time 209.45 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:49:04 PM PDT 24
Peak memory 201416 kb
Host smart-41878c13-45db-4ae0-b6a9-7e82e189ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78816980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.78816980
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1803520016
Short name T516
Test name
Test status
Simulation time 331444255923 ps
CPU time 384.67 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 05:52:14 PM PDT 24
Peak memory 201428 kb
Host smart-c4b8c0bf-4f97-4888-9352-600909382df3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803520016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1803520016
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.682077822
Short name T511
Test name
Test status
Simulation time 321167004950 ps
CPU time 76.5 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 05:46:58 PM PDT 24
Peak memory 201404 kb
Host smart-1ddf125f-a7d8-4f5f-82c2-4e1b976e79fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682077822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.682077822
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2041721632
Short name T473
Test name
Test status
Simulation time 489689833044 ps
CPU time 1053.81 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 06:03:12 PM PDT 24
Peak memory 201340 kb
Host smart-1708ac56-4bc5-4031-bf8d-f78be5051f23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041721632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2041721632
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4230712597
Short name T517
Test name
Test status
Simulation time 564392289133 ps
CPU time 827.83 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:59:28 PM PDT 24
Peak memory 201468 kb
Host smart-2b149dee-a51d-47b5-9653-b670f47f3f0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230712597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4230712597
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.860748778
Short name T399
Test name
Test status
Simulation time 595855727876 ps
CPU time 1301.73 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 06:07:18 PM PDT 24
Peak memory 201448 kb
Host smart-c7e4fea2-7782-4651-9a73-72bc55c31b76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860748778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.860748778
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2931830131
Short name T436
Test name
Test status
Simulation time 100802664123 ps
CPU time 499.82 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:54:00 PM PDT 24
Peak memory 201832 kb
Host smart-0c8a9f18-c8c6-4926-bedc-56594cf5a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931830131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2931830131
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1671007404
Short name T768
Test name
Test status
Simulation time 36819743394 ps
CPU time 85.3 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:47:03 PM PDT 24
Peak memory 201280 kb
Host smart-14308ff5-63dc-4f0c-8a37-250459c3aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671007404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1671007404
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2055421163
Short name T567
Test name
Test status
Simulation time 3529670743 ps
CPU time 2.69 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:45:36 PM PDT 24
Peak memory 201356 kb
Host smart-7959e250-2980-477e-b2e4-b60c5a71b51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055421163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2055421163
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2356226495
Short name T613
Test name
Test status
Simulation time 5847412476 ps
CPU time 7.43 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:45:45 PM PDT 24
Peak memory 201360 kb
Host smart-13e7e5d1-51c0-4371-86b7-84a8c4a9357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356226495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2356226495
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1091645683
Short name T323
Test name
Test status
Simulation time 331762637746 ps
CPU time 196.75 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:48:52 PM PDT 24
Peak memory 201392 kb
Host smart-89ba2707-386c-43bf-8556-5214cf75f418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091645683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1091645683
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3340439843
Short name T69
Test name
Test status
Simulation time 57513943568 ps
CPU time 58.07 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 05:46:32 PM PDT 24
Peak memory 209972 kb
Host smart-076d77e0-fe6e-46c1-b9e8-ca2f472469f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340439843 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3340439843
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3164838818
Short name T404
Test name
Test status
Simulation time 317179387 ps
CPU time 1.15 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:45:39 PM PDT 24
Peak memory 201180 kb
Host smart-dfe6fd21-a67f-4cfa-bdbf-58a80b35aafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164838818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3164838818
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1276232396
Short name T312
Test name
Test status
Simulation time 535145602863 ps
CPU time 1216.97 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 06:05:57 PM PDT 24
Peak memory 201400 kb
Host smart-4e62c171-dd81-46fe-98d4-8a22efe4aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276232396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1276232396
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3517803687
Short name T705
Test name
Test status
Simulation time 332984995022 ps
CPU time 796.05 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:58:53 PM PDT 24
Peak memory 201388 kb
Host smart-a3b23f1a-02c1-439f-947c-dac0531540ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517803687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3517803687
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2059282063
Short name T408
Test name
Test status
Simulation time 164221185147 ps
CPU time 190.6 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:48:47 PM PDT 24
Peak memory 201436 kb
Host smart-ee10d910-3654-433a-964a-27387fe007c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059282063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2059282063
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1208122292
Short name T576
Test name
Test status
Simulation time 329368858178 ps
CPU time 407.33 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:52:27 PM PDT 24
Peak memory 201496 kb
Host smart-bc957a11-2402-4a9a-b93a-eb0bc42c68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208122292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1208122292
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.860686777
Short name T410
Test name
Test status
Simulation time 487929186706 ps
CPU time 153.52 seconds
Started Aug 08 05:45:33 PM PDT 24
Finished Aug 08 05:48:07 PM PDT 24
Peak memory 201484 kb
Host smart-d4a802d5-79b1-495c-907d-52ba5af37dcd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=860686777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.860686777
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3462061849
Short name T301
Test name
Test status
Simulation time 395623727409 ps
CPU time 218.84 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 05:49:15 PM PDT 24
Peak memory 201480 kb
Host smart-3a797d1e-436b-4658-999f-4a2bb0b0e831
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462061849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3462061849
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2394081601
Short name T43
Test name
Test status
Simulation time 389544394357 ps
CPU time 788.36 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:58:44 PM PDT 24
Peak memory 201448 kb
Host smart-4c49b9ba-139a-406c-9b3d-f15879fb323a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394081601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2394081601
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.345049067
Short name T604
Test name
Test status
Simulation time 105299207082 ps
CPU time 515.26 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:54:11 PM PDT 24
Peak memory 201764 kb
Host smart-b6fb7c74-54aa-4b84-93a3-6c1b829ffc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345049067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.345049067
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.33997303
Short name T63
Test name
Test status
Simulation time 34862909270 ps
CPU time 80.06 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:46:59 PM PDT 24
Peak memory 201308 kb
Host smart-55a809db-cc92-4ea2-8ff8-246e1a326a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33997303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.33997303
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3933113646
Short name T718
Test name
Test status
Simulation time 4924158792 ps
CPU time 3.75 seconds
Started Aug 08 05:45:38 PM PDT 24
Finished Aug 08 05:45:42 PM PDT 24
Peak memory 201348 kb
Host smart-1981508b-ea40-42f0-b831-ead3f57e2843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933113646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3933113646
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.112725489
Short name T434
Test name
Test status
Simulation time 5777487709 ps
CPU time 3.17 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 05:45:39 PM PDT 24
Peak memory 201564 kb
Host smart-d2a15ab2-4e1f-4c8b-89e6-f0add7af5cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112725489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.112725489
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.658969001
Short name T521
Test name
Test status
Simulation time 243809645347 ps
CPU time 1320.76 seconds
Started Aug 08 05:45:34 PM PDT 24
Finished Aug 08 06:07:35 PM PDT 24
Peak memory 201804 kb
Host smart-71bc1835-8dff-46fb-978b-0846fa6d866a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658969001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.658969001
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.120330267
Short name T515
Test name
Test status
Simulation time 323574543 ps
CPU time 1.39 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:45:54 PM PDT 24
Peak memory 201248 kb
Host smart-b2185c30-bbe0-4cb6-9dbd-79ea77317eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120330267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.120330267
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3505524560
Short name T237
Test name
Test status
Simulation time 517709081676 ps
CPU time 270.04 seconds
Started Aug 08 05:45:42 PM PDT 24
Finished Aug 08 05:50:12 PM PDT 24
Peak memory 201448 kb
Host smart-58e65564-4897-4c38-b6c9-c29e47bde5b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505524560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3505524560
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1864363644
Short name T228
Test name
Test status
Simulation time 496238596185 ps
CPU time 1112.92 seconds
Started Aug 08 05:45:42 PM PDT 24
Finished Aug 08 06:04:15 PM PDT 24
Peak memory 201512 kb
Host smart-0e577c7e-fb41-4a03-b430-154e42c6f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864363644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1864363644
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.304206143
Short name T749
Test name
Test status
Simulation time 323045989218 ps
CPU time 782.48 seconds
Started Aug 08 05:45:36 PM PDT 24
Finished Aug 08 05:58:39 PM PDT 24
Peak memory 201448 kb
Host smart-04bf9a81-5c00-4314-bcb4-f73e3c2141b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304206143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.304206143
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2467173499
Short name T497
Test name
Test status
Simulation time 162606935496 ps
CPU time 102.65 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:47:20 PM PDT 24
Peak memory 201388 kb
Host smart-33bd9c95-7869-4ff3-869e-13e1ebb3d035
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467173499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2467173499
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1425462195
Short name T676
Test name
Test status
Simulation time 329560677916 ps
CPU time 396.31 seconds
Started Aug 08 05:45:40 PM PDT 24
Finished Aug 08 05:52:16 PM PDT 24
Peak memory 201432 kb
Host smart-3542daee-3551-438d-9474-bbcf7dd67413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425462195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1425462195
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2970881548
Short name T439
Test name
Test status
Simulation time 334220468396 ps
CPU time 765 seconds
Started Aug 08 05:45:37 PM PDT 24
Finished Aug 08 05:58:22 PM PDT 24
Peak memory 201428 kb
Host smart-2240265f-8fba-4222-95ee-f9a3a4c84528
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970881548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2970881548
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.362550396
Short name T248
Test name
Test status
Simulation time 191508517199 ps
CPU time 46.77 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:46:31 PM PDT 24
Peak memory 201396 kb
Host smart-2d2a6a60-59fa-409f-9585-bd06c6c3bfaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362550396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.362550396
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2807545762
Short name T374
Test name
Test status
Simulation time 590324695311 ps
CPU time 385.56 seconds
Started Aug 08 05:45:41 PM PDT 24
Finished Aug 08 05:52:06 PM PDT 24
Peak memory 201484 kb
Host smart-e0b93d61-f003-4fcf-92c0-b4dd03d3779c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807545762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2807545762
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1108607198
Short name T776
Test name
Test status
Simulation time 121538824118 ps
CPU time 463.86 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:53:19 PM PDT 24
Peak memory 201784 kb
Host smart-8040f241-18ca-4304-9a4e-44c27528fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108607198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1108607198
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1134280902
Short name T577
Test name
Test status
Simulation time 39867824920 ps
CPU time 21.41 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:56 PM PDT 24
Peak memory 201264 kb
Host smart-8b8a6cc1-04ad-4368-8b02-23048ae49444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134280902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1134280902
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2173848811
Short name T428
Test name
Test status
Simulation time 5006756321 ps
CPU time 12.55 seconds
Started Aug 08 05:45:35 PM PDT 24
Finished Aug 08 05:45:47 PM PDT 24
Peak memory 201272 kb
Host smart-a50e387b-ab78-4434-bc32-4ac58d5cad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173848811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2173848811
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.96305982
Short name T489
Test name
Test status
Simulation time 5781901664 ps
CPU time 7.03 seconds
Started Aug 08 05:45:41 PM PDT 24
Finished Aug 08 05:45:48 PM PDT 24
Peak memory 201388 kb
Host smart-45916b6b-945e-4409-93f0-c0716df11963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96305982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.96305982
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3060185328
Short name T107
Test name
Test status
Simulation time 218698299542 ps
CPU time 516.75 seconds
Started Aug 08 05:45:45 PM PDT 24
Finished Aug 08 05:54:22 PM PDT 24
Peak memory 201552 kb
Host smart-5d9370ff-dafd-4dbf-9598-61433ba13500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060185328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3060185328
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2979581835
Short name T701
Test name
Test status
Simulation time 41832601335 ps
CPU time 105.54 seconds
Started Aug 08 05:45:56 PM PDT 24
Finished Aug 08 05:47:42 PM PDT 24
Peak memory 217864 kb
Host smart-0cff4593-f72b-4f80-97e7-56bc89bc8e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979581835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2979581835
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1526836478
Short name T618
Test name
Test status
Simulation time 427592673 ps
CPU time 0.65 seconds
Started Aug 08 05:45:50 PM PDT 24
Finished Aug 08 05:45:51 PM PDT 24
Peak memory 201164 kb
Host smart-38ec55ea-113a-4e20-bf41-f29e86654340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526836478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1526836478
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2169307278
Short name T620
Test name
Test status
Simulation time 188273218840 ps
CPU time 100.64 seconds
Started Aug 08 05:45:44 PM PDT 24
Finished Aug 08 05:47:24 PM PDT 24
Peak memory 201392 kb
Host smart-4d40fe02-eaec-4ee5-9285-bb8ec452ca72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169307278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2169307278
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1335950805
Short name T794
Test name
Test status
Simulation time 548961610941 ps
CPU time 1277.19 seconds
Started Aug 08 05:45:48 PM PDT 24
Finished Aug 08 06:07:06 PM PDT 24
Peak memory 201480 kb
Host smart-a6061017-710a-421d-82ea-f02830d793ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335950805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1335950805
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2130294505
Short name T612
Test name
Test status
Simulation time 332865947301 ps
CPU time 360.83 seconds
Started Aug 08 05:45:52 PM PDT 24
Finished Aug 08 05:51:53 PM PDT 24
Peak memory 201432 kb
Host smart-c10e9599-5b45-41cd-ac28-f68edb5a1dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130294505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2130294505
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3669605425
Short name T484
Test name
Test status
Simulation time 166463308888 ps
CPU time 149.62 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:48:19 PM PDT 24
Peak memory 201468 kb
Host smart-2546f2f8-d4f4-41fc-9b93-abf5b2e441df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669605425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3669605425
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3265311830
Short name T225
Test name
Test status
Simulation time 335039002590 ps
CPU time 396.48 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:52:27 PM PDT 24
Peak memory 201496 kb
Host smart-ab4c8d46-71df-45cd-b82e-d6c729e8fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265311830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3265311830
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2100386849
Short name T386
Test name
Test status
Simulation time 329225706816 ps
CPU time 729.97 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:57:59 PM PDT 24
Peak memory 201424 kb
Host smart-1209aa42-b37a-409c-ad3f-8fba3f2b3c6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100386849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2100386849
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1988820910
Short name T444
Test name
Test status
Simulation time 601131078511 ps
CPU time 323.3 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:51:18 PM PDT 24
Peak memory 201544 kb
Host smart-a4d503fd-2890-47de-9a20-bf794e6b5174
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988820910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1988820910
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3788076434
Short name T216
Test name
Test status
Simulation time 89452762744 ps
CPU time 254.82 seconds
Started Aug 08 05:45:45 PM PDT 24
Finished Aug 08 05:50:00 PM PDT 24
Peak memory 201776 kb
Host smart-81bc951c-6bf7-49f0-b371-a4cca38db7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788076434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3788076434
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1144592434
Short name T476
Test name
Test status
Simulation time 31069445187 ps
CPU time 68.33 seconds
Started Aug 08 05:45:49 PM PDT 24
Finished Aug 08 05:46:57 PM PDT 24
Peak memory 201308 kb
Host smart-6fd21c00-f438-44dd-ae5a-26da007488c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144592434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1144592434
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3823061272
Short name T397
Test name
Test status
Simulation time 4497130809 ps
CPU time 5.71 seconds
Started Aug 08 05:45:51 PM PDT 24
Finished Aug 08 05:45:57 PM PDT 24
Peak memory 201556 kb
Host smart-560c334a-cefd-47cc-9dc6-c050aaf33208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823061272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3823061272
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3283951723
Short name T105
Test name
Test status
Simulation time 5624715365 ps
CPU time 13.95 seconds
Started Aug 08 05:45:55 PM PDT 24
Finished Aug 08 05:46:09 PM PDT 24
Peak memory 201392 kb
Host smart-28fe0a7f-88d9-49cd-8fc6-ec55de27f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283951723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3283951723
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1633476200
Short name T174
Test name
Test status
Simulation time 458994758496 ps
CPU time 1285.41 seconds
Started Aug 08 05:45:46 PM PDT 24
Finished Aug 08 06:07:11 PM PDT 24
Peak memory 212400 kb
Host smart-ac798e57-8588-404a-8ed3-fdf3caa48cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633476200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1633476200
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3559297023
Short name T70
Test name
Test status
Simulation time 42810954571 ps
CPU time 123.55 seconds
Started Aug 08 05:45:57 PM PDT 24
Finished Aug 08 05:48:00 PM PDT 24
Peak memory 218264 kb
Host smart-4796762e-4230-4dd7-8add-f693ea0e2b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559297023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3559297023
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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