Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6765	1			T2	20		T3	49		T6	26
testmodes[AdcCtrlTestmodeNormal]	5531	1			T3	51		T5	3		T6	11
testmodes[AdcCtrlTestmodeLowpower]	5747	1			T1	3		T3	39		T7	24
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3574	1			T2	19		T3	17		T6	21
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1772	1			T3	21		T6	5		T7	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1315	1			T3	10		T7	3		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1718	1			T3	19		T6	5		T7	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1969	1			T3	15		T5	2		T6	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1489	1			T3	17		T7	1		T43	30
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1356	1			T3	13		T7	1		T43	36
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1456	1			T3	14		T7	2		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2695	1			T1	2		T3	12		T7	20