Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22910

1

T2

20

T3

139

T5

32

auto[ADC_CTRL_FILTER_COND_OUT]

3296

1

T1

18

T6

12

T7

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20324

1

T2

20

T3

139

T6

99

auto[1]

5882

1

T1

18

T5

32

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T230	12		T231	7		T232	7
values[0]	19	1			T233	1		T234	18		-	-
values[1]	662	1			T1	7		T40	15		T41	13
values[2]	679	1			T6	25		T13	1		T14	22
values[3]	674	1			T13	2		T143	32		T164	5
values[4]	646	1			T1	10		T6	12		T140	20
values[5]	706	1			T27	1		T42	10		T155	3
values[6]	951	1			T1	1		T42	8		T134	14
values[7]	711	1			T40	27		T44	1		T144	18
values[8]	583	1			T135	1		T235	3		T236	12
values[9]	3466	1			T5	32		T6	28		T7	10
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T1	7		T13	1		T40	15
values[1]	617	1			T6	25		T13	2		T14	22
values[2]	632	1			T140	12		T134	7		T143	32
values[3]	697	1			T1	10		T6	12		T27	1
values[4]	816	1			T140	8		T42	10		T134	14
values[5]	934	1			T1	1		T40	27		T42	8
values[6]	2913	1			T5	32		T9	1		T10	27
values[7]	659	1			T7	10		T51	27		T32	11
values[8]	722	1			T27	1		T39	18		T40	33
values[9]	220	1			T6	28		T155	15		T136	9
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T235	1		T18	10		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	7		T13	1		T40	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	14		T13	1		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	1		T32	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T134	7		T149	18		T237	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T140	1		T143	16		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T27	1		T32	2		T157	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	10		T6	6		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T140	1		T134	14		T238	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	10		T138	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	15		T42	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	1		T143	9		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T5	3		T9	1		T10	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T239	4		T240	7		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	7		T161	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	6		T51	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T40	13		T43	2		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	1		T39	10		T41	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T6	14		T155	1		T206	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T136	9		T139	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T235	7		T18	12		T150	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	2		T41	7		T36	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	11		T14	12		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T92	6		T186	9		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T149	14		T237	2		T186	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T140	11		T143	16		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	1		T157	8		T164	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	6		T155	2		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T140	7		T238	6		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T138	1		T147	1		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T40	12		T34	1		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T143	4		T138	14		T174	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T5	29		T141	8		T172	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T240	5		T150	4		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	4		T35	1		T92	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	4		T51	13		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	20		T244	13		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	8		T41	8		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T6	14		T155	14		T246	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T241	9		T247	10		T209	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T230	12		T231	1		T232	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T233	1		T234	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T235	1		T18	10		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	7		T40	13		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	14		T14	10		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T32	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T149	18		T186	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T143	16		T164	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T140	1		T32	2		T134	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	10		T6	6		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	1		T238	5		T174	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	10		T155	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T42	8		T134	14		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	1		T143	9		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	15		T44	1		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T195	12		T239	4		T168	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T35	2		T92	11		T17	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T135	1		T235	1		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T5	3		T6	14		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T7	6		T27	1		T39	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T231	6		T232	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T235	7		T18	12		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	2		T41	7		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	11		T14	12		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T92	6		T186	9		T240	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T149	14		T186	14		T204	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T143	16		T164	2		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T140	7		T32	1		T157	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	6		T140	11		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T238	6		T174	2		T164	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T155	2		T33	1		T235	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	1		T147	16		T92	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T143	4		T138	14		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	12		T144	5		T138	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T195	10		T168	10		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	1		T92	12		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T235	2		T236	3		T87	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1151	1			T5	29		T6	14		T40	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	4		T39	8		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T235	8		T18	16		T150	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	1		T13	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	12		T13	1		T14	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	1		T32	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	1		T149	15		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	12		T143	17		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T27	1		T32	2		T157	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T6	7		T155	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T140	8		T134	1		T238	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	1		T138	2		T147	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T40	13		T42	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	1		T143	5		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T5	32		T9	1		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T239	1		T240	6		T150	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T32	10		T161	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	8		T51	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	21		T43	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	1		T39	9		T41	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T6	15		T155	15		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T136	1		T139	1		T241	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	6		T79	20		T82	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	6		T40	12		T41	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	13		T14	9		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T92	4		T186	1		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T134	6		T149	17		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T143	15		T164	2		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	1		T157	19		T163	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	9		T6	5		T99	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	13		T238	4		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T42	9		T250	11		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	14		T42	7		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T143	8		T138	14		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T10	24		T12	31		T159	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T239	3		T240	6		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	1		T35	1		T92	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	2		T51	13		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	12		T43	1		T136	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	9		T41	7		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	13		T206	13		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T136	8		T209	7		T251	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	1		T231	7		T232	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T233	1		T234	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T235	8		T18	16		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T40	3		T41	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	12		T14	13		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	1		T32	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T149	15		T186	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	1		T143	17		T164	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T140	8		T32	2		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T6	7		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T27	1		T238	7		T174	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	1		T155	3		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T42	1		T134	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	1		T143	5		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	13		T44	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T195	11		T239	1		T168	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T35	2		T92	13		T17	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T135	1		T235	3		T236	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T5	32		T6	15		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T7	8		T27	1		T39	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T230	11		T232	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	6		T19	3		T79	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	6		T40	12		T41	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	13		T14	9		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T92	4		T186	1		T240	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T149	17		T186	10		T100	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T143	15		T164	2		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	1		T134	6		T157	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	9		T6	5		T99	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T238	4		T174	6		T236	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T42	9		T250	11		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	7		T134	13		T174	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T143	8		T138	14		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	14		T144	12		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T195	11		T239	3		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T35	1		T92	10		T244	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T236	8		T240	6		T252	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T6	13		T10	24		T12	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	2		T39	9		T41	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22842

1

T2

20

T3

139

T5

32

auto[ADC_CTRL_FILTER_COND_OUT]

3364

1

T1

18

T6

25

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T1

7

T2

20

T3

139

auto[1]

6043

1

T1

11

T5

32

T7

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T155	3		T253	1		T254	1
values[0]	2	1			T255	2		-	-		-	-
values[1]	621	1			T1	7		T41	13		T42	10
values[2]	684	1			T14	22		T134	14		T155	15
values[3]	555	1			T1	11		T32	1		T135	1
values[4]	2856	1			T5	32		T9	1		T10	27
values[5]	821	1			T7	10		T13	1		T51	27
values[6]	852	1			T6	25		T27	1		T143	32
values[7]	787	1			T27	1		T40	15		T43	2
values[8]	789	1			T6	12		T13	1		T41	16
values[9]	1152	1			T6	28		T13	1		T39	18
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	841	1			T1	7		T41	13		T42	10
values[1]	579	1			T32	1		T134	14		T135	1
values[2]	519	1			T1	11		T14	22		T40	33
values[3]	2949	1			T5	32		T9	1		T10	27
values[4]	785	1			T137	1		T143	32		T235	16
values[5]	928	1			T6	25		T7	10		T27	2
values[6]	653	1			T42	8		T144	18		T145	9
values[7]	957	1			T6	40		T13	1		T40	15
values[8]	754	1			T13	1		T39	18		T140	20
values[9]	159	1			T40	27		T204	29		T256	14
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T155	1		T138	15		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	7		T41	6		T42	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	1		T134	14		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T163	14		T148	1		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	10		T149	12		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	11		T40	13		T157	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T5	3		T9	1		T10	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T134	7		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T143	16		T235	1		T164	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T137	1		T235	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	6		T27	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T6	14		T27	1		T236	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	8		T144	13		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	4		T241	1		T257	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T6	20		T13	1		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T161	1		T44	1		T174	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T39	10		T140	1		T41	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T140	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T40	15		T204	14		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T256	8		T246	14		T25	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T155	14		T138	14		T235	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	7		T238	6		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	4		T34	1		T101	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T175	4		T240	1		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	12		T149	10		T81	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	20		T157	8		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T5	29		T141	8		T51	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	1		T87	10		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T143	16		T235	2		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T235	12		T92	7		T164	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	4		T34	1		T45	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	11		T236	3		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	5		T145	8		T87	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	3		T241	11		T257	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	20		T40	2		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T174	2		T176	13		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T39	8		T140	7		T41	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	11		T155	2		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T40	12		T204	15		T258	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T256	6		T246	11		T25	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T253	1		T254	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T155	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T235	1		T89	9		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	7		T41	6		T42	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	10		T134	14		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T163	14		T238	5		T174	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	1		T135	1		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	11		T157	20		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T5	3		T9	1		T10	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	13		T134	7		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	6		T51	14		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	1		T137	1		T235	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T27	1		T143	16		T45	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	14		T236	9		T35	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	13		T43	2		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T27	1		T203	6		T239	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	6		T13	1		T41	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T44	1		T146	1		T240	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T6	14		T39	10		T40	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	1		T140	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T155	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T235	7		T89	8		T149	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T41	7		T250	12		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	12		T155	14		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T238	6		T174	11		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T81	9		T260	7		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T157	8		T92	12		T150	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T5	29		T141	8		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T40	20		T138	1		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	4		T51	13		T235	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T235	12		T87	10		T92	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T143	16		T45	8		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	11		T236	3		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	2		T34	1		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T203	14		T262	1		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	6		T41	8		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T240	9		T18	8		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	14		T39	8		T40	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T140	11		T33	1		T138	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1