Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22731

1

T1

1

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3475

1

T1

17

T6

40

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19930

1

T1

7

T2

20

T3

139

auto[1]

6276

1

T1

11

T5

32

T6

65

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T241	10		T321	10		-	-
values[0]	99	1			T6	25		T150	5		T151	10
values[1]	689	1			T27	1		T140	8		T135	1
values[2]	3037	1			T1	7		T5	32		T9	1
values[3]	997	1			T27	1		T40	15		T140	12
values[4]	785	1			T1	10		T39	18		T41	13
values[5]	796	1			T1	1		T137	1		T143	13
values[6]	502	1			T6	28		T13	1		T42	8
values[7]	522	1			T7	10		T14	22		T134	7
values[8]	798	1			T6	12		T13	1		T33	3
values[9]	879	1			T13	1		T40	60		T41	16
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1015	1			T6	25		T27	1		T135	1
values[1]	3023	1			T1	7		T5	32		T9	1
values[2]	896	1			T140	12		T134	14		T243	5
values[3]	784	1			T1	10		T27	1		T39	18
values[4]	811	1			T1	1		T13	1		T42	8
values[5]	485	1			T6	28		T136	2		T235	8
values[6]	743	1			T7	10		T14	22		T134	7
values[7]	557	1			T6	12		T13	1		T155	3
values[8]	672	1			T40	33		T41	16		T32	14
values[9]	86	1			T13	1		T40	27		T204	7
minimum	17134	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T6	14		T27	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T161	1		T34	2		T164	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T5	3		T9	1		T10	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	7		T40	13		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T134	14		T243	1		T302	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T140	1		T236	5		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T27	1		T41	6		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	10		T39	10		T51	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T137	1		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	1		T42	8		T143	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T136	2		T35	2		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	14		T235	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	6		T137	1		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	10		T134	7		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T33	2		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	6		T155	1		T163	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T40	13		T41	8		T32	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T32	2		T235	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T204	3		T208	3		T322	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T13	1		T40	15		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16994	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	11		T157	8		T147	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T34	1		T164	12		T176	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T5	29		T141	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	2		T138	1		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T243	4		T302	8		T195	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T140	11		T35	3		T195	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	7		T155	14		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	8		T51	13		T45	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T138	14		T186	9		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T143	4		T174	11		T92	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T35	1		T87	10		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	14		T235	7		T164	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	4		T143	16		T250	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	12		T87	11		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T33	1		T238	6		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	6		T155	2		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	20		T41	8		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	1		T235	12		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T204	4		T181	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T40	12		T323	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T140	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T321	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T241	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	14		T151	10		T324	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T150	1		T325	7		T326	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	1		T135	1		T157	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	1		T161	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1646	1			T5	3		T9	1		T10	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	7		T138	1		T203	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T27	1		T32	1		T134	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T40	13		T140	1		T236	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T41	6		T135	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	10		T39	10		T51	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T137	1		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T143	9		T174	11		T45	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T136	2		T174	6		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	14		T13	1		T42	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	6		T137	1		T238	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T14	10		T134	7		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T33	2		T143	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	6		T87	1		T38	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T40	13		T41	8		T32	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T40	15		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T6	11		T324	12		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T150	4		T325	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T157	8		T147	16		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T140	7		T34	1		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T5	29		T141	8		T172	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T138	1		T203	14		T168	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T174	2		T36	1		T302	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T40	2		T140	11		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T41	7		T155	14		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T39	8		T51	13		T99	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T138	14		T250	13		T186	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T143	4		T174	11		T45	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T35	1		T87	10		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	14		T164	2		T18	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	4		T238	6		T186	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	12		T235	7		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	1		T143	16		T250	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	6		T87	11		T38	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	20		T41	8		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	12		T32	1		T155	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T6	12		T27	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T161	1		T34	2		T164	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T5	32		T9	1		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T40	3		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	1		T243	5		T302	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T140	12		T236	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	1		T41	8		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	1		T39	9		T51	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T137	1		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T42	1		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	1		T35	2		T87	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	15		T235	8		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	8		T137	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	13		T134	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T33	3		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	7		T155	3		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T40	21		T41	9		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T32	2		T235	13		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T204	5		T208	1		T322	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T13	1		T40	13		T187	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17102	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T140	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	13		T157	19		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	1		T164	11		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T10	24		T12	31		T42	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	6		T40	12		T203	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T134	13		T195	13		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T236	4		T35	3		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T41	5		T144	12		T250	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	9		T39	9		T51	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	14		T174	5		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T42	7		T143	8		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T136	1		T35	1		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	13		T164	2		T18	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	2		T143	15		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	9		T134	6		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T238	4		T236	8		T92	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	5		T163	13		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T40	12		T41	7		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T32	1		T164	16		T239	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T204	2		T208	2		T322	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T40	14		T323	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T327	16		T212	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T241	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T6	12		T151	1		T324	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T150	5		T325	14		T326	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	1		T135	1		T157	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T140	8		T161	1		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T5	32		T9	1		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T138	2		T203	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T27	1		T32	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T40	3		T140	12		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	8		T135	1		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T39	9		T51	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T137	1		T138	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T143	5		T174	12		T45	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	1		T174	1		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	15		T13	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	8		T137	1		T238	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	13		T134	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T33	3		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	7		T87	12		T38	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T40	21		T41	9		T32	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T40	13		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T321	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T6	13		T151	9		T324	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T325	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T157	19		T147	11		T175	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	1		T164	11		T252	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T10	24		T12	31		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	6		T203	5		T280	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T134	13		T174	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	12		T236	4		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T41	5		T144	12		T206	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	9		T39	9		T51	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	14		T250	11		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T143	8		T174	10		T45	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T136	1		T174	5		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	13		T42	7		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T238	4		T186	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T14	9		T134	6		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T143	15		T250	9		T92	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	5		T38	2		T204	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T40	12		T41	7		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	14		T32	1		T163	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2