Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20147

1

T1

8

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

6059

1

T1

10

T5

32

T6

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20097

1

T1

17

T2

20

T3

139

auto[1]

6109

1

T1

1

T5

32

T6

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T7	10		T143	13		T265	3
values[0]	27	1			T146	1		T309	14		T308	11
values[1]	600	1			T27	1		T40	15		T41	16
values[2]	729	1			T6	12		T134	7		T235	11
values[3]	798	1			T13	1		T41	13		T43	2
values[4]	706	1			T140	12		T32	1		T144	18
values[5]	693	1			T1	8		T6	28		T13	1
values[6]	609	1			T1	10		T140	8		T51	27
values[7]	567	1			T13	1		T14	22		T137	1
values[8]	712	1			T155	15		T163	14		T138	13
values[9]	3422	1			T5	32		T6	25		T9	1
minimum	17082	1			T2	20		T3	139		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	584	1			T27	1		T41	16		T32	11
values[1]	3157	1			T5	32		T6	12		T9	1
values[2]	750	1			T13	1		T41	13		T143	32
values[3]	613	1			T140	12		T144	18		T138	29
values[4]	660	1			T1	8		T6	28		T13	1
values[5]	669	1			T1	10		T51	27		T137	2
values[6]	576	1			T13	1		T14	22		T163	14
values[7]	784	1			T155	15		T138	2		T147	28
values[8]	1035	1			T6	25		T7	10		T27	1
values[9]	91	1			T143	13		T19	13		T30	19
minimum	17287	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T41	8		T145	1		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T27	1		T32	7		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T235	2		T36	4		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1738	1			T5	3		T6	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T143	16		T174	7		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	1		T41	6		T238	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T174	17		T146	1		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T140	1		T144	13		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	8		T6	14		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	10		T32	1		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T51	14		T137	1		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	10		T137	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T14	10		T163	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	1		T35	2		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T155	1		T138	1		T236	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T147	12		T195	12		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	14		T7	6		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T136	13		T268	1		T250	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T143	9		T171	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T19	9		T30	10		T328	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16991	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T40	13		T42	8		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	8		T145	8		T240	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T32	4		T155	2		T18	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T235	9		T36	2		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1182	1			T5	29		T6	6		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	16		T174	2		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T41	7		T238	6		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T174	11		T204	15		T81	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	11		T144	5		T138	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	14		T39	8		T40	32
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T157	8		T204	18		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T51	13		T237	2		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T243	4		T92	12		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	12		T34	1		T45	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T34	1		T35	1		T87	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T155	14		T138	1		T236	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T147	16		T195	10		T176	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	11		T7	4		T138	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T250	13		T149	14		T176	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T143	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T19	4		T30	9		T328	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	2		T11	2		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T40	2		T235	12		T175	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T7	6		T143	9		T265	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T149	18		T176	1		T19	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T308	11		T329	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T146	1		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	8		T32	2		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	1		T40	13		T42	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T235	2		T37	4		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	6		T134	7		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T143	16		T174	7		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	1		T41	6		T43	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T174	11		T146	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T140	1		T32	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	8		T6	14		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	10		T134	14		T157	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T140	1		T51	14		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	10		T137	1		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T14	10		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T34	1		T35	2		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T155	1		T163	14		T138	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T147	12		T195	12		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	14		T27	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1740	1			T5	3		T9	1		T10	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T7	4		T143	4		T21	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T149	14		T176	13		T19	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T309	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	8		T32	1		T145	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	2		T32	4		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T235	9		T37	1		T150	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	6		T87	11		T89	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	16		T174	2		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T41	7		T238	6		T147	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T174	11		T36	1		T272	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T140	11		T144	5		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	14		T39	8		T40	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T157	8		T164	15		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	7		T51	13		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T243	4		T92	12		T205	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	12		T34	1		T45	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T34	1		T35	1		T87	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T155	14		T138	2		T92	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T147	16		T195	10		T176	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	11		T236	3		T92	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1163	1			T5	29		T141	8		T172	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	9		T145	9		T240	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	1		T32	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T235	11		T36	5		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1548	1			T5	32		T6	7		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T143	17		T174	3		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T41	8		T238	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T174	13		T146	1		T204	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T140	12		T144	6		T138	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	2		T6	15		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T42	1		T32	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	14		T137	1		T139	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T137	1		T243	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T14	13		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	2		T35	2		T87	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T155	15		T138	2		T236	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T147	17		T195	11		T176	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	12		T7	8		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T136	1		T268	1		T250	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T143	5		T171	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T19	10		T30	10		T328	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17138	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T40	3		T42	1		T235	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T41	7		T99	14		T206	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T32	1		T18	6		T262	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T36	1		T37	1		T280	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T6	5		T10	24		T12	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T143	15		T174	6		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T41	5		T238	4		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T174	15		T204	13		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	12		T138	14		T164	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	6		T6	13		T39	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	9		T134	13		T157	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	13		T237	1		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	9		T92	10		T206	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	9		T163	13		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	1		T99	11		T81	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T236	8		T92	4		T203	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T147	11		T195	11		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	13		T7	2		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T136	12		T250	11		T149	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T143	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T19	3		T30	9		T328	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T32	1		T310	1		T330	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T40	12		T42	7		T175	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T7	8		T143	5		T265	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T149	15		T176	14		T19	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T308	1		T329	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T146	1		T309	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	9		T32	2		T145	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	1		T40	3		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T235	11		T37	4		T150	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	7		T134	1		T87	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T143	17		T174	3		T36	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	1		T41	8		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T174	12		T146	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	12		T32	1		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	2		T6	15		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T42	1		T134	1		T157	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	8		T51	14		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	1		T137	1		T243	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T14	13		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	2		T35	2		T87	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T155	15		T163	1		T138	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T147	17		T195	11		T176	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	12		T27	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1534	1			T5	32		T9	1		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T2	20		T3	139		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T7	2		T143	8		T265	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T149	17		T19	3		T328	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T308	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T41	7		T32	1		T99	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	12		T42	7		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	1		T280	21		T21	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	5		T134	6		T89	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T143	15		T174	6		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T41	5		T43	1		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T174	10		T36	1		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T144	12		T138	14		T164	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	6		T6	13		T39	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	9		T134	13		T157	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T51	13		T237	1		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	9		T92	10		T206	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	9		T34	1		T45	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	1		T99	11		T81	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T163	13		T138	9		T92	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T147	11		T195	11		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	13		T236	8		T92	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1369	1			T10	24		T12	31		T159	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2