Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26206

1

T1

18

T2

20

T3

139

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22858

1

T1

7

T2

20

T3

139

auto[ADC_CTRL_FILTER_COND_OUT]

3348

1

T1

11

T6

40

T7

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19644

1

T1

10

T2

20

T3

132

auto[1]

6562

1

T1

8

T3

7

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22181

1

T1

18

T2

20

T3

139

auto[1]

4025

1

T5

29

T6

31

T7

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	603	1			T3	7		T6	28		T7	2
values[0]	31	1			T243	5		T205	2		T283	16
values[1]	706	1			T140	12		T41	13		T174	6
values[2]	2939	1			T5	32		T6	25		T9	1
values[3]	893	1			T41	16		T51	27		T32	3
values[4]	624	1			T40	27		T140	8		T42	8
values[5]	682	1			T1	7		T7	10		T40	33
values[6]	664	1			T1	1		T6	12		T134	7
values[7]	590	1			T13	2		T14	22		T27	1
values[8]	658	1			T1	10		T13	1		T39	18
values[9]	1167	1			T27	1		T40	15		T43	2
minimum	16649	1			T2	20		T3	132		T6	34

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	601	1			T6	25		T140	12		T41	13
values[1]	3039	1			T5	32		T9	1		T10	27
values[2]	880	1			T41	16		T51	27		T32	3
values[3]	637	1			T1	7		T40	60		T140	8
values[4]	673	1			T7	10		T134	21		T136	13
values[5]	517	1			T1	1		T6	12		T13	1
values[6]	780	1			T1	10		T13	1		T14	22
values[7]	601	1			T13	1		T39	18		T40	15
values[8]	997	1			T6	28		T43	2		T135	1
values[9]	142	1			T27	1		T155	3		T138	2
minimum	17339	1			T2	20		T3	139		T6	34

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

4138

1

T1

15

T6

31

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	14		T140	1		T41	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	1		T87	1		T195	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T5	3		T9	1		T10	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T42	10		T32	7		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T41	8		T238	5		T236	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T51	14		T32	2		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	7		T140	1		T42	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	28		T235	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T144	13		T87	1		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	6		T134	21		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	1		T44	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T6	6		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T13	1		T174	7		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	10		T14	10		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T39	10		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	13		T136	11		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T43	2		T135	1		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	14		T161	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T155	1		T204	3		T178	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T27	1		T138	1		T81	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17052	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T243	1		T307	10		T310	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	11		T140	11		T41	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T87	11		T195	5		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T5	29		T141	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T32	4		T155	14		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T41	8		T238	6		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	13		T32	1		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T140	7		T157	8		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	32		T235	7		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T144	5		T87	10		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	4		T138	1		T147	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	1		T272	3		T186	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	6		T35	3		T101	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T174	2		T92	12		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	12		T143	4		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	8		T149	10		T176	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T40	2		T164	2		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T147	16		T92	7		T296	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	14		T235	2		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T155	2		T204	4		T178	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T138	1		T81	9		T315	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	2		T11	2		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T243	4		T307	4		T205	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	470	1			T3	7		T7	2		T32	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T6	14		T138	1		T89	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T283	9		T282	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T243	1		T205	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T140	1		T41	6		T174	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T87	1		T169	12		T307	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T5	3		T6	14		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	10		T32	7		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T41	8		T238	5		T236	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	14		T32	2		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T140	1		T42	8		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	15		T174	11		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	7		T135	1		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	6		T40	13		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	2		T144	13		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T6	6		T134	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	2		T44	1		T174	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	10		T27	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T39	10		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	10		T136	11		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T43	2		T135	1		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T27	1		T40	13		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16533	1			T2	20		T3	132		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T155	2		T92	7		T204	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T6	14		T138	1		T89	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	7		T282	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T243	4		T205	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T140	11		T41	7		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T87	11		T169	8		T307	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T5	29		T6	11		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	4		T138	14		T45	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T41	8		T238	6		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T51	13		T32	1		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T140	7		T157	8		T236	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	12		T174	11		T235	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T87	10		T195	10		T186	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	4		T40	20		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	1		T144	5		T272	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	6		T138	1		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T174	2		T92	12		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	12		T143	4		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	8		T176	13		T283	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T250	13		T164	2		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T147	16		T149	10		T296	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	2		T235	2		T203	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T11	2		T32	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	12		T140	12		T41	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T146	1		T87	12		T195	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T5	32		T9	1		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T42	1		T32	10		T155	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T41	9		T238	7		T236	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T51	14		T32	2		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T140	8		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	34		T235	8		T145	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T144	6		T87	11		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	8		T134	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T44	1		T34	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T6	7		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T174	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T14	13		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T39	9		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	3		T136	2		T139	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T43	1		T135	1		T147	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	15		T161	1		T235	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T155	3		T204	5		T178	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T27	1		T138	2		T81	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17188	1			T2	20		T3	139		T6	34
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T243	5		T307	5		T310	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	13		T41	5		T163	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T195	13		T169	11		T81	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T10	24		T12	31		T159	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	9		T32	1		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	7		T238	4		T236	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	13		T32	1		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	6		T42	7		T157	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	26		T35	1		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T144	12		T195	11		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	2		T134	19		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T34	1		T186	1		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	5		T35	3		T77	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T174	6		T92	10		T239	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	9		T14	9		T143	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	9		T149	11		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	12		T136	9		T265	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T43	1		T147	11		T92	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	13		T89	8		T203	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T204	2		T178	4		T324	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T81	5		T200	16		T313	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T174	5		T225	10		T262	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T307	9		T209	7		T331	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	485	1			T3	7		T7	2		T32	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	15		T138	2		T89	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T283	8		T282	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T243	5		T205	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T140	12		T41	8		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T87	12		T169	9		T307	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T5	32		T6	12		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	1		T32	10		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T41	9		T238	7		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	14		T32	2		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	8		T42	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	13		T174	12		T235	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T135	1		T87	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	8		T40	21		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	2		T144	6		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T6	7		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T44	1		T174	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	13		T27	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T39	9		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T136	2		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T43	1		T135	1		T147	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T27	1		T40	3		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16649	1			T2	20		T3	132		T6	34
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T92	11		T204	2		T178	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T6	13		T89	8		T297	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T283	8		T282	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	5		T174	5		T175	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T169	11		T307	9		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T6	13		T10	24		T12	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T42	9		T32	1		T138	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	7		T238	4		T236	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	13		T32	1		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T42	7		T157	19		T236	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	14		T174	10		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T1	6		T195	11		T186	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	2		T40	12		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T34	1		T144	12		T186	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	5		T134	6		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T174	6		T92	10		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T14	9		T143	8		T244	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	9		T239	14		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	9		T136	9		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T43	1		T147	11		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	12		T265	2		T203	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22068

1

T1

3

T2

20

T3

139

auto[1]

auto[0]

4138

1

T1

15

T6

31

T7

2